target-arm: A64: Add last AdvSIMD Integer to FP ops
This adds the remaining [US]CVTF operations to the SIMD shift-immediate, scalar-shift-immediate, two-reg-misc and scalar-two-reg-misc groups of opcodes. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1394822294-14837-4-git-send-email-peter.maydell@linaro.org [PMM: added scalar 2-misc and scalar-shift-imm encodings] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alex Bennée
Peter Maydell
parent
cf4ab1af29
commit
10113b6903
@ -5907,6 +5907,95 @@ static void handle_scalar_simd_shli(DisasContext *s, bool insert,
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tcg_temp_free_i64(tcg_rd);
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}
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/* Common vector code for handling integer to FP conversion */
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static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
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int elements, int is_signed,
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int fracbits, int size)
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{
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bool is_double = size == 3 ? true : false;
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TCGv_ptr tcg_fpst = get_fpstatus_ptr();
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TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
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TCGv_i64 tcg_int = tcg_temp_new_i64();
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TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
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int pass;
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for (pass = 0; pass < elements; pass++) {
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read_vec_element(s, tcg_int, rn, pass, mop);
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if (is_double) {
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TCGv_i64 tcg_double = tcg_temp_new_i64();
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if (is_signed) {
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gen_helper_vfp_sqtod(tcg_double, tcg_int,
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tcg_shift, tcg_fpst);
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} else {
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gen_helper_vfp_uqtod(tcg_double, tcg_int,
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tcg_shift, tcg_fpst);
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}
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if (elements == 1) {
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write_fp_dreg(s, rd, tcg_double);
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} else {
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write_vec_element(s, tcg_double, rd, pass, MO_64);
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}
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tcg_temp_free_i64(tcg_double);
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} else {
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TCGv_i32 tcg_single = tcg_temp_new_i32();
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if (is_signed) {
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gen_helper_vfp_sqtos(tcg_single, tcg_int,
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tcg_shift, tcg_fpst);
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} else {
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gen_helper_vfp_uqtos(tcg_single, tcg_int,
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tcg_shift, tcg_fpst);
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}
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if (elements == 1) {
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write_fp_sreg(s, rd, tcg_single);
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} else {
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write_vec_element_i32(s, tcg_single, rd, pass, MO_32);
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}
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tcg_temp_free_i32(tcg_single);
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}
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}
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if (!is_double && elements == 2) {
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clear_vec_high(s, rd);
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}
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tcg_temp_free_i64(tcg_int);
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tcg_temp_free_ptr(tcg_fpst);
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tcg_temp_free_i32(tcg_shift);
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}
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/* UCVTF/SCVTF - Integer to FP conversion */
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static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,
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bool is_q, bool is_u,
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int immh, int immb, int opcode,
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int rn, int rd)
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{
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bool is_double = extract32(immh, 3, 1);
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int size = is_double ? MO_64 : MO_32;
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int elements;
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int immhb = immh << 3 | immb;
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int fracbits = (is_double ? 128 : 64) - immhb;
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if (!extract32(immh, 2, 2)) {
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unallocated_encoding(s);
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return;
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}
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if (is_scalar) {
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elements = 1;
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} else {
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elements = is_double ? 2 : is_q ? 4 : 2;
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if (is_double && !is_q) {
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unallocated_encoding(s);
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return;
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}
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}
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/* immh == 0 would be a failure of the decode logic */
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g_assert(immh);
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handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size);
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}
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/* C3.6.9 AdvSIMD scalar shift by immediate
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* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
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* +-----+---+-------------+------+------+--------+---+------+------+
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@ -5934,6 +6023,10 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
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case 0x0a: /* SHL / SLI */
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handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd);
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break;
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case 0x1c: /* SCVTF, UCVTF */
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handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb,
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opcode, rn, rd);
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break;
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default:
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unsupported_encoding(s, insn);
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break;
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@ -6689,10 +6782,16 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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case 0x6d: /* FCMLE (zero) */
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handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd);
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return;
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case 0x1d: /* SCVTF */
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case 0x5d: /* UCVTF */
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{
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bool is_signed = (opcode == 0x1d);
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handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size);
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return;
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}
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x1c: /* FCVTAS */
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case 0x1d: /* SCVTF */
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case 0x3a: /* FCVTPS */
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case 0x3b: /* FCVTZS */
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case 0x3d: /* FRECPE */
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@ -6701,7 +6800,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x5c: /* FCVTAU */
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case 0x5d: /* UCVTF */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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case 0x7d: /* FRSQRTE */
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@ -6877,7 +6975,6 @@ static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u,
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}
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}
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/* C3.6.14 AdvSIMD shift by immediate
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* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
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* +---+---+---+-------------+------+------+--------+---+------+------+
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@ -6907,10 +7004,16 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
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case 0x14: /* SSHLL / USHLL */
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handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd);
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break;
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case 0x1c: /* SCVTF / UCVTF */
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handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb,
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opcode, rn, rd);
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break;
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case 0x1f: /* FCVTZS/ FCVTZU */
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unsupported_encoding(s, insn);
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return;
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default:
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/* We don't currently implement any of the Narrow or saturating shifts;
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* nor do we implement the fixed-point conversions in this
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* encoding group (SCVTF, FCVTZS, UCVTF, FCVTZU).
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/* We don't currently implement any of the Narrow or
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* saturating shifts.
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*/
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unsupported_encoding(s, insn);
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return;
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@ -8255,8 +8358,9 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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/* Floating point: U, size[1] and opcode indicate operation;
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* size[0] indicates single or double precision.
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*/
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int is_double = extract32(size, 0, 1);
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opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
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size = extract32(size, 0, 1) ? 3 : 2;
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size = is_double ? 3 : 2;
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switch (opcode) {
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case 0x2f: /* FABS */
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case 0x6f: /* FNEG */
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@ -8265,6 +8369,18 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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return;
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}
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break;
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case 0x1d: /* SCVTF */
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case 0x5d: /* UCVTF */
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{
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bool is_signed = (opcode == 0x1d) ? true : false;
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int elements = is_double ? 2 : is_q ? 4 : 2;
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if (is_double && !is_q) {
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unallocated_encoding(s);
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return;
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}
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handle_simd_intfp_conv(s, rd, rn, elements, is_signed, 0, size);
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return;
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}
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case 0x2c: /* FCMGT (zero) */
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case 0x2d: /* FCMEQ (zero) */
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case 0x2e: /* FCMLT (zero) */
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@ -8283,7 +8399,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x1c: /* FCVTAS */
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case 0x1d: /* SCVTF */
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case 0x38: /* FRINTP */
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case 0x39: /* FRINTZ */
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case 0x3a: /* FCVTPS */
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@ -8296,7 +8411,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x5c: /* FCVTAU */
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case 0x5d: /* UCVTF */
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case 0x79: /* FRINTI */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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