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cputlb: Change tlb_flush() argument to CPUState

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Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber 2013-09-04 02:19:44 +02:00
parent 31b030d4ab
commit 00c8cb0a36
41 changed files with 143 additions and 87 deletions
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6
cputlb.c
View File

@ -46,9 +46,9 @@ int tlb_flush_count;
* entries from the TLB at any time, so flushing more entries than
* required is only an efficiency issue, not a correctness issue.
*/
void tlb_flush(CPUArchState *env, int flush_global)
void tlb_flush(CPUState *cpu, int flush_global)
{
CPUState *cpu = ENV_GET_CPU(env);
CPUArchState *env = cpu->env_ptr;
#if defined(DEBUG_TLB)
printf("tlb_flush:\n");
@ -93,7 +93,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
env->tlb_flush_addr, env->tlb_flush_mask);
#endif
tlb_flush(env, 1);
tlb_flush(cpu, 1);
return;
}
/* must reset current TB so that interrupts cannot modify the

4
exec.c
View File

@ -1834,14 +1834,12 @@ static void tcg_commit(MemoryListener *listener)
reset the modified entries */
/* XXX: slow ! */
CPU_FOREACH(cpu) {
CPUArchState *env = cpu->env_ptr;
/* FIXME: Disentangle the cpu.h circular files deps so we can
directly get the right CPU from listener. */
if (cpu->tcg_as_listener != listener) {
continue;
}
tlb_flush(env, 1);
tlb_flush(cpu, 1);
}
}

2
hw/sh4/sh7750.c
View File

@ -416,7 +416,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr,
case SH7750_PTEH_A7:
/* If asid changes, clear all registered tlb entries. */
if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) {
tlb_flush(&s->cpu->env, 1);
tlb_flush(CPU(s->cpu), 1);
}
s->cpu->env.pteh = mem_value;
return;

4
include/exec/exec-all.h
View File

@ -99,7 +99,7 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);
/* cputlb.c */
void tlb_flush_page(CPUState *cpu, target_ulong addr);
void tlb_flush(CPUArchState *env, int flush_global);
void tlb_flush(CPUState *cpu, int flush_global);
void tlb_set_page(CPUArchState *env, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
@ -109,7 +109,7 @@ static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
{
}
static inline void tlb_flush(CPUArchState *env, int flush_global)
static inline void tlb_flush(CPUState *cpu, int flush_global)
{
}
#endif

2
target-alpha/cpu.c
View File

@ -258,7 +258,7 @@ static void alpha_cpu_initfn(Object *obj)
cs->env_ptr = env;
cpu_exec_init(env);
tlb_flush(env, 1);
tlb_flush(cs, 1);
alpha_translate_init();

2
target-alpha/sys_helper.c
View File

@ -64,7 +64,7 @@ void helper_call_pal(CPUAlphaState *env, uint64_t pc, uint64_t entry_ofs)
void helper_tbia(CPUAlphaState *env)
{
tlb_flush(env, 1);
tlb_flush(CPU(alpha_env_get_cpu(env)), 1);
}
void helper_tbis(CPUAlphaState *env, uint64_t p)

2
target-arm/cpu.c
View File

@ -149,7 +149,7 @@ static void arm_cpu_reset(CPUState *s)
&env->vfp.fp_status);
set_float_detect_tininess(float_tininess_before_rounding,
&env->vfp.standard_fp_status);
tlb_flush(env, 1);
tlb_flush(s, 1);
/* Reset is a state change for some CPUARMState fields which we
* bake assumptions about into translated code, so we need to
* tb_flush().

39
target-arm/helper.c
View File

@ -303,17 +303,21 @@ void init_cpreg_list(ARMCPU *cpu)
static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
env->cp15.c3 = value;
tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
}
static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
if (env->cp15.c13_fcse != value) {
/* Unlike real hardware the qemu TLB uses virtual addresses,
* not modified virtual addresses, so this causes a TLB flush.
*/
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
env->cp15.c13_fcse = value;
}
}
@ -321,12 +325,14 @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
/* For VMSA (when not using the LPAE long descriptor page table
* format) this register includes the ASID, so do a TLB flush.
* For PMSA it is purely a process ID and no action is needed.
*/
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
env->cp15.c13_context = value;
}
@ -335,7 +341,9 @@ static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate all (TLBIALL) */
tlb_flush(env, 1);
ARMCPU *cpu = arm_env_get_cpu(env);
tlb_flush(CPU(cpu), 1);
}
static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -351,7 +359,9 @@ static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate by ASID (TLBIASID) */
tlb_flush(env, value == 0);
ARMCPU *cpu = arm_env_get_cpu(env);
tlb_flush(CPU(cpu), value == 0);
}
static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -1352,11 +1362,13 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
if (arm_feature(env, ARM_FEATURE_LPAE)) {
/* With LPAE the TTBCR could result in a change of ASID
* via the TTBCR.A1 bit, so do a TLB flush.
*/
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
vmsa_ttbcr_raw_write(env, ri, value);
}
@ -1371,8 +1383,10 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
/* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
env->cp15.c2_control = value;
}
@ -1383,7 +1397,9 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
* must flush the TLB.
*/
if (cpreg_field_is_64bit(ri)) {
tlb_flush(env, 1);
ARMCPU *cpu = arm_env_get_cpu(env);
tlb_flush(CPU(cpu), 1);
}
raw_write(env, ri, value);
}
@ -1708,8 +1724,9 @@ static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate by ASID (AArch64 version) */
ARMCPU *cpu = arm_env_get_cpu(env);
int asid = extract64(value, 48, 16);
tlb_flush(env, asid == 0);
tlb_flush(CPU(cpu), asid == 0);
}
static const ARMCPRegInfo v8_cp_reginfo[] = {
@ -1835,10 +1852,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
env->cp15.c1_sys = value;
/* ??? Lots of these bits are not implemented. */
/* This may enable/disable the MMU, so do a TLB flush. */
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)

2
target-cris/cpu.c
View File

@ -51,7 +51,7 @@ static void cris_cpu_reset(CPUState *s)
vr = env->pregs[PR_VR];
memset(env, 0, offsetof(CPUCRISState, load_info));
env->pregs[PR_VR] = vr;
tlb_flush(env, 1);
tlb_flush(s, 1);
#if defined(CONFIG_USER_ONLY)
/* start in user mode with interrupts enabled. */

2
target-i386/cpu.c
View File

@ -2412,7 +2412,7 @@ static void x86_cpu_reset(CPUState *s)
memset(env, 0, offsetof(CPUX86State, pat));
tlb_flush(env, 1);
tlb_flush(s, 1);
env->old_exception = -1;

17
target-i386/helper.c
View File

@ -385,22 +385,25 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
a20_state = (a20_state != 0);
if (a20_state != ((env->a20_mask >> 20) & 1)) {
CPUState *cs = CPU(cpu);
#if defined(DEBUG_MMU)
printf("A20 update: a20=%d\n", a20_state);
#endif
/* if the cpu is currently executing code, we must unlink it and
all the potentially executing TB */
cpu_interrupt(CPU(cpu), CPU_INTERRUPT_EXITTB);
cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
/* when a20 is changed, all the MMU mappings are invalid, so
we must flush everything */
tlb_flush(env, 1);
tlb_flush(cs, 1);
env->a20_mask = ~(1 << 20) | (a20_state << 20);
}
}
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
{
X86CPU *cpu = x86_env_get_cpu(env);
int pe_state;
#if defined(DEBUG_MMU)
@ -408,7 +411,7 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
#endif
if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
(env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
#ifdef TARGET_X86_64
@ -444,24 +447,28 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
the PDPT */
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
{
X86CPU *cpu = x86_env_get_cpu(env);
env->cr[3] = new_cr3;
if (env->cr[0] & CR0_PG_MASK) {
#if defined(DEBUG_MMU)
printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
#endif
tlb_flush(env, 0);
tlb_flush(CPU(cpu), 0);
}
}
void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
{
X86CPU *cpu = x86_env_get_cpu(env);
#if defined(DEBUG_MMU)
printf("CR4 update: CR4=%08x\n", (uint32_t)env->cr[4]);
#endif
if ((new_cr4 ^ env->cr[4]) &
(CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
CR4_SMEP_MASK | CR4_SMAP_MASK)) {
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
/* SSE handling */
if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) {

2
target-i386/machine.c
View File

@ -325,7 +325,7 @@ static int cpu_post_load(void *opaque, int version_id)
for (i = 0; i < DR7_MAX_BP; i++) {
hw_breakpoint_insert(env, i);
}
tlb_flush(env, 1);
tlb_flush(cs, 1);
return 0;
}

2
target-i386/svm_helper.c
View File

@ -294,7 +294,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
break;
case TLB_CONTROL_FLUSH_ALL_ASID:
/* FIXME: this is not 100% correct but should work for now */
tlb_flush(env, 1);
tlb_flush(cs, 1);
break;
}

2
target-lm32/cpu.c
View File

@ -128,7 +128,7 @@ static void lm32_cpu_reset(CPUState *s)
memset(env, 0, offsetof(CPULM32State, eba));
lm32_cpu_init_cfg_reg(cpu);
tlb_flush(env, 1);
tlb_flush(s, 1);
}
static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)

2
target-m68k/cpu.c
View File

@ -58,7 +58,7 @@ static void m68k_cpu_reset(CPUState *s)
env->cc_op = CC_OP_FLAGS;
/* TODO: We should set PC from the interrupt vector. */
env->pc = 0;
tlb_flush(env, 1);
tlb_flush(s, 1);
}
/* CPU models */

2
target-microblaze/cpu.c
View File

@ -65,7 +65,7 @@ static void mb_cpu_reset(CPUState *s)
memset(env, 0, sizeof(CPUMBState));
env->res_addr = RES_ADDR_NONE;
tlb_flush(env, 1);
tlb_flush(s, 1);
/* Disable stack protector. */
env->shr = ~0;

3
target-microblaze/mmu.c
View File

@ -219,6 +219,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)
void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
{
MicroBlazeCPU *cpu = mb_env_get_cpu(env);
unsigned int i;
D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));
@ -252,7 +253,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
/* Changes to the zone protection reg flush the QEMU TLB.
Fortunately, these are very uncommon. */
if (v != env->mmu.regs[rn]) {
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
env->mmu.regs[rn] = v;
break;

2
target-mips/cpu.c
View File

@ -84,7 +84,7 @@ static void mips_cpu_reset(CPUState *s)
mcc->parent_reset(s);
memset(env, 0, offsetof(CPUMIPSState, mvp));
tlb_flush(env, 1);
tlb_flush(s, 1);
cpu_state_reset(env);
}

3
target-mips/machine.c
View File

@ -191,6 +191,7 @@ static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
CPUMIPSState *env = opaque;
MIPSCPU *cpu = mips_env_get_cpu(env);
int i;
if (version_id != 3)
@ -303,6 +304,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
load_fpu(f, &env->fpus[i]);
/* XXX: ensure compatibility for halted bit ? */
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
return 0;
}

4
target-mips/op_helper.c
View File

@ -1787,8 +1787,10 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
/* TLB management */
static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
{
MIPSCPU *cpu = mips_env_get_cpu(env);
/* Flush qemu's TLB and discard all shadowed entries. */
tlb_flush (env, flush_global);
tlb_flush(CPU(cpu), flush_global);
env->tlb->tlb_in_use = env->tlb->nb_tlb;
}

2
target-moxie/cpu.c
View File

@ -45,7 +45,7 @@ static void moxie_cpu_reset(CPUState *s)
memset(env, 0, sizeof(CPUMoxieState));
env->pc = 0x1000;
tlb_flush(env, 1);
tlb_flush(s, 1);
}
static void moxie_cpu_realizefn(DeviceState *dev, Error **errp)

2
target-openrisc/cpu.c
View File

@ -47,7 +47,7 @@ static void openrisc_cpu_reset(CPUState *s)
memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq));
#endif
tlb_flush(&cpu->env, 1);
tlb_flush(s, 1);
/*tb_flush(&cpu->env); FIXME: Do we need it? */
cpu->env.pc = 0x100;

2
target-openrisc/interrupt.c
View File

@ -43,7 +43,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
/* For machine-state changed between user-mode and supervisor mode,
we need flush TLB when we enter&exit EXCP. */
tlb_flush(env, 1);
tlb_flush(cs, 1);
env->esr = env->sr;
env->sr &= ~SR_DME;

2
target-openrisc/interrupt_helper.c
View File

@ -51,7 +51,7 @@ void HELPER(rfe)(CPUOpenRISCState *env)
}
if (need_flush_tlb) {
tlb_flush(&cpu->env, 1);
tlb_flush(cs, 1);
}
#endif
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;

2
target-openrisc/sys_helper.c
View File

@ -45,7 +45,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
case TO_SPR(0, 17): /* SR */
if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
(rb & (SR_IME | SR_DME | SR_SM))) {
tlb_flush(env, 1);
tlb_flush(cs, 1);
}
env->sr = rb;
env->sr |= SR_FO; /* FO is const equal to 1 */

4
target-ppc/excp_helper.c
View File

@ -616,7 +616,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
}
/* If we disactivated any translation, flush TLBs */
if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
tlb_flush(env, 1);
tlb_flush(cs, 1);
}
#ifdef TARGET_PPC64
@ -671,7 +671,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
/* XXX: The BookE changes address space when switching modes,
we should probably implement that as different MMU indexes,
but for the moment we do it the slow way and flush all. */
tlb_flush(env, 1);
tlb_flush(cs, 1);
}
}

2
target-ppc/helper_regs.h
View File

@ -83,7 +83,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
if (((value >> MSR_IR) & 1) != msr_ir ||
((value >> MSR_DR) & 1) != msr_dr) {
/* Flush all tlb when changing translation mode */
tlb_flush(env, 1);
tlb_flush(cs, 1);
excp = POWERPC_EXCP_NONE;
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}

4
target-ppc/misc_helper.c
View File

@ -62,10 +62,12 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
if (likely(env->pb[num] != value)) {
env->pb[num] = value;
/* Should be optimized */
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
}

6
target-ppc/mmu-hash64.c
View File

@ -99,6 +99,7 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
void helper_slbia(CPUPPCState *env)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
int n, do_invalidate;
do_invalidate = 0;
@ -116,12 +117,13 @@ void helper_slbia(CPUPPCState *env)
}
}
if (do_invalidate) {
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
}
void helper_slbie(CPUPPCState *env, target_ulong addr)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
ppc_slb_t *slb;
slb = slb_lookup(env, addr);
@ -136,7 +138,7 @@ void helper_slbie(CPUPPCState *env, target_ulong addr)
* and we still don't have a tlb_flush_mask(env, n, mask)
* in QEMU, we just invalidate all TLBs
*/
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
}

44
target-ppc/mmu_helper.c
View File

@ -231,6 +231,7 @@ static inline int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
ppc6xx_tlb_t *tlb;
int nr, max;
@ -244,7 +245,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
tlb = &env->tlb.tlb6[nr];
pte_invalidate(&tlb->pte0);
}
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
@ -644,6 +645,7 @@ static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address,
/* Helpers specific to PowerPC 40x implementations */
static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
ppcemb_tlb_t *tlb;
int i;
@ -651,7 +653,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
tlb = &env->tlb.tlbe[i];
tlb->prot &= ~PAGE_VALID;
}
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,
@ -862,6 +864,7 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
static void booke206_flush_tlb(CPUPPCState *env, int flags,
const int check_iprot)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
int tlb_size;
int i, j;
ppcmas_tlb_t *tlb = env->tlb.tlbm;
@ -878,7 +881,7 @@ static void booke206_flush_tlb(CPUPPCState *env, int flags,
tlb += booke206_tlb_size(env, i);
}
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
static hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
@ -1918,7 +1921,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
break;
case POWERPC_MMU_BOOKE:
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
break;
case POWERPC_MMU_BOOKE206:
booke206_flush_tlb(env, -1, 0);
@ -1931,7 +1934,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
case POWERPC_MMU_2_06a:
case POWERPC_MMU_2_06d:
#endif /* defined(TARGET_PPC64) */
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
break;
default:
/* XXX: TODO */
@ -2009,7 +2012,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
* and we still don't have a tlb_flush_mask(env, n, mask) in QEMU,
* we just invalidate all TLBs
*/
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
break;
#endif /* defined(TARGET_PPC64) */
default:
@ -2026,6 +2029,8 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
/* Special registers manipulation */
void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value);
assert(!env->external_htab);
if (env->spr[SPR_SDR1] != value) {
@ -2048,7 +2053,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
env->htab_mask = ((value & SDR_32_HTABMASK) << 16) | 0xFFFF;
env->htab_base = value & SDR_32_HTABORG;
}
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
}
@ -2066,6 +2071,8 @@ target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__,
(int)srnum, value, env->sr[srnum]);
#if defined(TARGET_PPC64)
@ -2098,11 +2105,11 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
page = (16 << 20) * srnum;
end = page + (16 << 20);
for (; page != end; page += TARGET_PAGE_SIZE) {
tlb_flush_page(env, page);
tlb_flush_page(CPU(cpu), page);
}
}
#else
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
#endif
}
}
@ -2424,6 +2431,7 @@ target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address)
void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
target_ulong value)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
ppcemb_tlb_t *tlb;
target_ulong EPN, RPN, size;
int do_flush_tlbs;
@ -2459,13 +2467,13 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
}
tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
if (do_flush_tlbs) {
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
break;
case 1:
RPN = value & 0xFFFFFC0F;
if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN) {
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
tlb->RPN = RPN;
break;
@ -2577,9 +2585,11 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
env->spr[pidn] = pid;
/* changing PIDs mean we're in a different address space now */
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
void helper_booke206_tlbwe(CPUPPCState *env)
@ -2674,7 +2684,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {
tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);
} else {
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
}
@ -2798,7 +2808,7 @@ void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address)
if (address & 0x8) {
/* flush TLB1 entries */
booke206_invalidate_ea_tlb(env, 1, address);
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
} else {
/* flush TLB0 entries */
booke206_invalidate_ea_tlb(env, 0, address);
@ -2814,6 +2824,7 @@ void helper_booke206_tlbilx0(CPUPPCState *env, target_ulong address)
void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
int i, j;
int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID);
ppcmas_tlb_t *tlb = env->tlb.tlbm;
@ -2830,11 +2841,12 @@ void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address)
}
tlb += booke206_tlb_size(env, i);
}
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
int i, j;
ppcmas_tlb_t *tlb;
int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID);
@ -2870,7 +2882,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
tlb->mas1 &= ~MAS1_VALID;
}
}
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type)

2
target-ppc/translate_init.c
View File

@ -8435,7 +8435,7 @@ static void ppc_cpu_reset(CPUState *s)
#endif /* TARGET_PPC64 */
/* Flush all TLBs */
tlb_flush(env, 1);
tlb_flush(s, 1);
}
static void ppc_cpu_initfn(Object *obj)

4
target-s390x/cpu.c
View File

@ -98,7 +98,7 @@ static void s390_cpu_reset(CPUState *s)
#if !defined(CONFIG_USER_ONLY)
s->halted = 1;
#endif
tlb_flush(env, 1);
tlb_flush(s, 1);
}
/* S390CPUClass::initial_reset() */
@ -153,7 +153,7 @@ static void s390_cpu_full_reset(CPUState *s)
#if !defined(CONFIG_USER_ONLY)
s->halted = 1;
#endif
tlb_flush(env, 1);
tlb_flush(s, 1);
}
#if !defined(CONFIG_USER_ONLY)

13
target-s390x/mem_helper.c
View File

@ -810,6 +810,7 @@ void HELPER(tr)(CPUS390XState *env, uint32_t len, uint64_t array,
#if !defined(CONFIG_USER_ONLY)
void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
S390CPU *cpu = s390_env_get_cpu(env);
int i;
uint64_t src = a2;
@ -824,11 +825,12 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
}
}
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
S390CPU *cpu = s390_env_get_cpu(env);
int i;
uint64_t src = a2;
@ -842,7 +844,7 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
}
}
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
@ -935,6 +937,7 @@ uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2)
/* compare and swap and purge */
uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2)
{
S390CPU *cpu = s390_env_get_cpu(env);
uint32_t cc;
uint32_t o1 = env->regs[r1];
uint64_t a2 = r2 & ~3ULL;
@ -944,7 +947,7 @@ uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2)
cpu_stl_data(env, a2, env->regs[(r1 + 1) & 15]);
if (r2 & 0x3) {
/* flush TLB / ALB */
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
cc = 0;
} else {
@ -1040,7 +1043,9 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr)
/* flush local tlb */
void HELPER(ptlb)(CPUS390XState *env)
{
tlb_flush(env, 1);
S390CPU *cpu = s390_env_get_cpu(env);
tlb_flush(CPU(cpu), 1);
}
/* store using real address */

2
target-sh4/cpu.c
View File

@ -54,7 +54,7 @@ static void superh_cpu_reset(CPUState *s)
scc->parent_reset(s);
memset(env, 0, offsetof(CPUSH4State, id));
tlb_flush(env, 1);
tlb_flush(s, 1);
env->pc = 0xA0000000;
#if defined(CONFIG_USER_ONLY)

2
target-sh4/helper.c
View File

@ -585,7 +585,7 @@ void cpu_load_tlb(CPUSH4State * env)
entry->v = 0;
}
tlb_flush(s, 1);
tlb_flush(CPU(sh_env_get_cpu(s)), 1);
}
uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,

2
target-sparc/cpu.c
View File

@ -34,7 +34,7 @@ static void sparc_cpu_reset(CPUState *s)
scc->parent_reset(s);
memset(env, 0, offsetof(CPUSPARCState, version));
tlb_flush(env, 1);
tlb_flush(s, 1);
env->cwp = 0;
#ifndef TARGET_SPARC64
env->wim = 1;

18
target-sparc/ldst_helper.c
View File

@ -871,7 +871,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
case 2: /* flush region (16M) */
case 3: /* flush context (4G) */
case 4: /* flush entire */
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
break;
default:
break;
@ -896,7 +896,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
disabled mode are invalid in normal mode */
if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
(env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
break;
case 1: /* Context Table Pointer Register */
@ -907,7 +907,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
if (oldreg != env->mmuregs[reg]) {
/* we flush when the MMU context changes because
QEMU has no MMU context support */
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
break;
case 3: /* Synchronous Fault Status Register with Clear */
@ -1663,7 +1663,9 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
int asi, int size)
{
CPUState *cs = CPU(sparc_env_get_cpu(env));
SPARCCPU *cpu = sparc_env_get_cpu(env);
CPUState *cs = CPU(cpu);
#ifdef DEBUG_ASI
dump_asi("write", addr, asi, size, val);
#endif
@ -1872,7 +1874,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
#ifdef DEBUG_MMU
dump_mmu(stdout, fprintf, env);
#endif
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
return;
}
@ -1961,13 +1963,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
env->dmmu.mmu_primary_context = val;
/* can be optimized to only flush MMU_USER_IDX
and MMU_KERNEL_IDX entries */
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
break;
case 2: /* Secondary context */
env->dmmu.mmu_secondary_context = val;
/* can be optimized to only flush MMU_USER_SECONDARY_IDX
and MMU_KERNEL_SECONDARY_IDX entries */
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
break;
case 5: /* TSB access */
DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
@ -2397,7 +2399,7 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
/* flush neverland mappings created during no-fault mode,
so the sequential MMU faults report proper fault types */
if (env->mmuregs[0] & MMU_NF) {
tlb_flush(env, 1);
tlb_flush(cs, 1);
}
}
#else

3
target-sparc/machine.c
View File

@ -112,6 +112,7 @@ void cpu_save(QEMUFile *f, void *opaque)
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
CPUSPARCState *env = opaque;
SPARCCPU *cpu = sparc_env_get_cpu(env);
int i;
uint32_t tmp;
@ -212,6 +213,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_be64s(f, &env->ssr);
cpu_get_timer(f, env->hstick);
#endif
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
return 0;
}

2
target-unicore32/cpu.c
View File

@ -121,7 +121,7 @@ static void uc32_cpu_initfn(Object *obj)
env->regs[31] = 0x03000000;
#endif
tlb_flush(env, 1);
tlb_flush(cs, 1);
if (tcg_enabled() && !inited) {
inited = true;

4
target-unicore32/helper.c
View File

@ -50,6 +50,8 @@ uint32_t HELPER(clz)(uint32_t x)
void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
uint32_t cop)
{
UniCore32CPU *cpu = uc32_env_get_cpu(env);
/*
* movc pp.nn, rn, #imm9
* rn: UCOP_REG_D
@ -118,7 +120,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
case 6:
if ((cop <= 6) && (cop >= 2)) {
/* invalid all tlb */
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
return;
}
break;

4
target-xtensa/op_helper.c
View File

@ -487,10 +487,12 @@ void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
{
XtensaCPU *cpu = xtensa_env_get_cpu(env);
v = (v & 0xffffff00) | 0x1;
if (v != env->sregs[RASID]) {
env->sregs[RASID] = v;
tlb_flush(env, 1);
tlb_flush(CPU(cpu), 1);
}
}