qemu/tcg
Peter Maydell 8377e3fb85 tcg: Allow top bit of SIMD_DATA_BITS to be set in simd_desc()
In simd_desc() we create a SIMD descriptor from various pieces
including an arbitrary data value from the caller.  We try to
sanitize these to make sure everything will fit: the 'data' value
needs to fit in the SIMD_DATA_BITS (== 22) sized field.  However we
do that sanitizing with:
   tcg_debug_assert(data == sextract32(data, 0, SIMD_DATA_BITS));

This works for the case where the data is supposed to be considered
as a signed integer (which can then be returned via simd_data()).
However, some callers want to treat the data value as unsigned.

Specifically, for the Arm SVE operations, make_svemte_desc()
assembles a data value as a collection of fields, and it needs to use
all 22 bits.  Currently if MTE is enabled then its MTEDESC SIZEM1
field may have the most significant bit set, and then it will trip
this assertion.

Loosen the assertion so that we only check that the data value will
fit into the field in some way, either as a signed or as an unsigned
value.  This means we will fail to detect some kinds of bug in the
callers, but we won't spuriously assert for intentional use of the
data field as unsigned.

Cc: qemu-stable@nongnu.org
Fixes: db432672dc ("tcg: Add generic vector expanders")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2601
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-ID: <20241115172515.1229393-1-peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-11-16 08:42:25 -08:00
..
aarch64 tcg/aarch64: Support TCG_TARGET_HAS_tst_vec 2024-05-22 19:05:25 -07:00
arm include/exec/memop: Rename get_alignment_bits 2024-10-13 11:27:03 -07:00
i386 tcg/i386: Implement vector TST{EQ,NE} for avx512 2024-09-22 06:54:50 +02:00
loongarch64 tcg/loongarch64: remove break after g_assert_not_reached() 2024-09-24 13:53:35 +02:00
mips tcg: Add TCGConst argument to tcg_target_const_match 2024-02-03 23:53:48 +00:00
ppc tcg/ppc: Fix tcg_out_rlw_rc 2024-10-22 13:45:03 -07:00
riscv tcg/riscv: Enable native vector support for TCG host 2024-10-22 11:57:25 -07:00
s390x tcg/s390x: fix constraint for 32-bit TSTEQ/TSTNE 2024-10-17 19:41:22 +02:00
sparc64 include/exec/memop: Rename get_alignment_bits 2024-10-13 11:27:03 -07:00
tci tcg/tci: Support TCG_COND_TST{EQ,NE} 2024-02-05 22:45:41 +00:00
debuginfo.c accel/tcg: Move perf and debuginfo support to tcg/ 2024-01-29 21:04:10 +10:00
meson.build meson: Drop the .fa library suffix 2024-07-03 18:41:26 +02:00
optimize.c tcg/optimize: Optimize bitsel_vec 2024-09-22 06:54:49 +02:00
perf.c accel/tcg: Move perf and debuginfo support to tcg/ 2024-01-29 21:04:10 +10:00
region.c tcg: Make the cleanup-on-error path unique 2024-01-23 13:22:46 +10:00
tcg-common.c tcg: Silent -Wmissing-field-initializers warning 2023-02-27 22:29:01 +01:00
tcg-internal.h tcg: Export vec_gen_6 2024-09-22 06:54:49 +02:00
tcg-ldst.c.inc tcg: Move TCGLabelQemuLdst to tcg.c 2023-05-05 17:21:03 +01:00
tcg-op-gvec.c tcg: Allow top bit of SIMD_DATA_BITS to be set in simd_desc() 2024-11-16 08:42:25 -08:00
tcg-op-ldst.c include/exec/memop: Rename get_alignment_bits 2024-10-13 11:27:03 -07:00
tcg-op-vec.c tcg: Export vec_gen_6 2024-09-22 06:54:49 +02:00
tcg-op.c tcg: Propagate new TCGOp to add_as_label_use 2024-09-22 06:54:49 +02:00
tcg-pool.c.inc tcg: Introduce tcg_splitwx_to_{rx,rw} 2021-01-07 05:09:41 -10:00
tcg.c tcg: Reset data_gen_ptr correctly 2024-10-22 11:57:25 -07:00
tci.c tcg: Make tcg/helper-info.h self-contained 2024-04-30 16:12:05 -07:00