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tcg/s390x: fix constraint for 32-bit TSTEQ/TSTNE

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32-bit TSTEQ and TSTNE is subject to the same constraints as
for 64-bit, but setcond_i32 and negsetcond_i32 were incorrectly
using TCG_CT_CONST ("i") instead of TCG_CT_CONST_CMP ("C").

Adjust the constraint and make tcg_target_const_match use the
same sequence as tgen_cmp2: first check if the constant is a
valid operand for TSTEQ/TSTNE, then accept everything for 32-bit
non-test comparisons, finally check if the constant is a valid
operand for 64-bit non-test comparisons.

Reported-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Cc: qemu-stable@nongnu.org

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2024-10-17 11:09:52 +02:00
parent 45f519950d
commit 615586cb35
1 changed files with 16 additions and 8 deletions
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24
tcg/s390x/tcg-target.c.inc
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@ -565,6 +565,20 @@ static bool tcg_target_const_match(int64_t val, int ct,
}
if (ct & TCG_CT_CONST_CMP) {
if (is_tst_cond(cond)) {
if (is_const_p16(uval) >= 0) {
return true; /* TMxx */
}
if (risbg_mask(uval)) {
return true; /* RISBG */
}
return false;
}
if (type == TCG_TYPE_I32) {
return true;
}
switch (cond) {
case TCG_COND_EQ:
case TCG_COND_NE:
@ -584,13 +598,7 @@ static bool tcg_target_const_match(int64_t val, int ct,
break;
case TCG_COND_TSTNE:
case TCG_COND_TSTEQ:
if (is_const_p16(uval) >= 0) {
return true; /* TMxx */
}
if (risbg_mask(uval)) {
return true; /* RISBG */
}
break;
/* checked above, fallthru */
default:
g_assert_not_reached();
}
@ -3231,9 +3239,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i32:
case INDEX_op_rotr_i64:
return C_O1_I2(r, r, ri);
case INDEX_op_setcond_i32:
case INDEX_op_negsetcond_i32:
return C_O1_I2(r, r, ri);
case INDEX_op_setcond_i64:
case INDEX_op_negsetcond_i64:
return C_O1_I2(r, r, rC);