Commit Graph

193 Commits

Author SHA1 Message Date
Max Filippov 1b3e71f8ee target-xtensa: add missing window check for entry
Entry opcode needs to check if moving to new register frame would cause
register window overflow. Entry used in function prologue never
overflows because preceding windowed call* opcode writes return address
to the target register window frame, causing overflow exceptions at the
point of call. But when a sequence of entry opcodes is used for register
window spilling there may not be a call or other opcode that would cause
window check between entries and they would not raise overflow exception
themselves resulting in data corruption.

Cc: qemu-stable@nongnu.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-11-10 17:59:13 +03:00
Peter Maydell eb5f222b5c Xtensa fixes and improvements 2014-11-03:
- build fixes for cores w/o windowed registers and with profiling
   interrupts;
 - fix uImage load address for MMUv2 cores;
 - add script for automatic core import from xtensa configuration overlay.
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Merge remote-tracking branch 'remotes/xtensa/tags/20141103-xtensa' into staging

Xtensa fixes and improvements 2014-11-03:
- build fixes for cores w/o windowed registers and with profiling
  interrupts;
- fix uImage load address for MMUv2 cores;
- add script for automatic core import from xtensa configuration overlay.

# gpg: Signature made Sun 02 Nov 2014 22:04:44 GMT using RSA key ID F83FA044
# gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>"
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>"

* remotes/xtensa/tags/20141103-xtensa:
  MAINTAINERS: update xtensa boards
  target-xtensa: fix build for cores w/o windowed registers
  target-xtensa: add core importing script
  hw/xtensa/xtfpga: treat uImage load address as virtual
  hw/core/loader: implement address translation in uimage loader
  target-xtensa: avoid duplicate timer interrupt delivery
  target-xtensa: tests: pre-process tests linker script
  target-xtensa: add definition for XTHAL_INTTYPE_PROFILING

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-11-03 16:43:32 +00:00
Max Filippov ab5824134f target-xtensa: fix build for cores w/o windowed registers
Cores without windowed registers don't have window overflow/underflow
vectors. Move these vectors to a separate group defined conditionally.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-11-03 01:00:37 +03:00
Max Filippov 9bea2e91a6 target-xtensa: add core importing script
This script copies configuration and gdb information from the xtensa
configuration overlay archive and registers new xtensa core.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-11-03 01:00:37 +03:00
Max Filippov dec71d2d63 target-xtensa: add definition for XTHAL_INTTYPE_PROFILING
There's new interrupt type in the recent Xtensa releases that may appear
in configuration overlay. Add definition so that new cores that use it
could be automatically imported.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-11-03 00:51:43 +03:00
Peter Maydell 11693a6cf0 target-xtensa: mark XtensaConfig structs as unused
The XtensaConfig structs will be defined but not used if they are
for the opposite endianness from that of the binary being built;
keep the compiler from complaining about this by marking them
with the 'unused' attribute.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-11-02 10:04:34 +03:00
Peter Maydell 2472b6c07b gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flag
GDB assumes that watchpoint set via the gdbstub remote protocol will
behave in the same way as hardware watchpoints for the target. In
particular, whether the CPU stops with the PC before or after the insn
which triggers the watchpoint is target dependent. Allow guest CPU
code to specify which behaviour to use. This fixes a bug where with
guest CPUs which stop before the accessing insn GDB would manually
step forward over what it thought was the insn and end up one insn
further forward than it should be.

We set this flag for the CPU architectures which set
gdbarch_have_nonsteppable_watchpoint in gdb 7.7:
ARM, CRIS, LM32, MIPS and Xtensa.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: Max Filippov <jcmvbkbc@gmail.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: Michael Walle <michael@walle.cc> (for lm32)
Message-id: 1410545057-14014-1-git-send-email-peter.maydell@linaro.org
2014-10-06 14:25:43 +01:00
Richard Henderson 37f3616aa8 target-xtensa: Use cpu_exec_interrupt qom hook
Cc: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
Message-id: 1410626734-3804-8-git-send-email-rth@twiddle.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25 18:54:21 +01:00
Peter Maydell 86025ee443 cpu-exec: Make debug_excp_handler a QOM CPU method
Make the debug_excp_handler target specific hook into a QOM
CPU method.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12 14:06:48 +01:00
Lluís Vilanova a7e30d84ce trace: [tcg] Include TCG-tracing header on all targets
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-08-12 14:26:12 +01:00
Paolo Bonzini f08b617018 softmmu: introduce cpu_ldst.h
This will collect all load and store helpers soon.  For now
it is just a replacement for softmmu_exec.h, which this patch
stops including directly, but we also include it where this will
be necessary in order to simplify the next patch.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-05 16:10:33 +02:00
Paolo Bonzini 0f590e749f softmmu: commonize helper definitions
They do not need to be in op_helper.c.  Because cputlb.c now includes
softmmu_template.h twice for each size, io_readX must be elided the
second time through.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-05 16:10:33 +02:00
Paolo Bonzini d94f0a8ecb softmmu: move ALIGNED_ONLY to cpu.h
Prepare for moving softmmu_header.h inclusion out of .c files

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-05 16:10:33 +02:00
Paolo Bonzini 93e22326d6 softmmu: make do_unaligned_access a method of CPU
We will reference it from more files in the next patch.  To avoid
ruining the small steps we're making towards multi-target, make
it a method of CPU rather than just a global.

Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-05 16:10:31 +02:00
Richard Henderson 2ef6175aa7 tcg: Invert the inclusion of helper.h
Rather than include helper.h with N values of GEN_HELPER, include a
secondary file that sets up the macros to include helper.h.  This
minimizes the files that must be rebuilt when changing the macros
for file N.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-28 09:33:54 -07:00
Max Filippov 433d33c555 target-xtensa: fix cross-page jumps/calls at the end of TB
Use tb->pc instead of dc->pc to check for cross-page jumps.
When TB translation stops at the page boundary dc->pc points to the next
page allowing chaining to TBs in it, which is wrong.

Cc: qemu-stable@nongnu.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-05-26 12:33:54 +04:00
Andreas Färber 0c591eb0a9 cputlb: Change tlb_set_page() argument to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13 19:52:47 +01:00
Andreas Färber 00c8cb0a36 cputlb: Change tlb_flush() argument to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13 19:52:47 +01:00
Andreas Färber 31b030d4ab cputlb: Change tlb_flush_page() argument to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13 19:52:47 +01:00
Andreas Färber 0ea8cb8895 cpu-exec: Change cpu_resume_from_signal() argument to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13 19:20:48 +01:00
Andreas Färber 75a34036d4 exec: Change cpu_watchpoint_{insert,remove{,_by_ref,_all}} argument
Use CPUState. This lets us drop a few local env usages.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13 19:20:48 +01:00
Andreas Färber 3f38f309b2 translate-all: Change cpu_restore_state() argument to CPUState
This lets us drop some local variables in tlb_fill() functions.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13 19:20:47 +01:00
Andreas Färber 5638d180d6 cpu-exec: Change cpu_loop_exit() argument to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13 19:20:47 +01:00
Andreas Färber d5a11fefef exec: Change tlb_fill() argument to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13 19:20:47 +01:00
Andreas Färber f0c3c505a8 cpu: Move breakpoints field from CPU_COMMON to CPUState
Most targets were using offsetof(CPUFooState, breakpoints) to determine
how much of CPUFooState to clear on reset. Use the next field after
CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13 19:20:47 +01:00
Andreas Färber ff4700b05c cpu: Move watchpoint fields from CPU_COMMON to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13 19:20:47 +01:00
Andreas Färber 27103424c4 cpu: Move exception_index field from CPU_COMMON to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13 19:20:46 +01:00
Andreas Färber 8c2e1b0093 cpu: Turn cpu_has_work() into a CPUClass hook
Default to false.

Tidy variable naming and inline cast uses while at it.

Tested-by: Jia Liu <proljc@gmail.com> (or32)
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13 19:01:49 +01:00
Andreas Färber 1cf5ccbca8 target-xtensa: Clean up ENV_GET_CPU() usage
Commits a00817cc4c and
fdfba1a298 added usages of ENV_GET_CPU()
macro in target-specific code.

Use xtensa_env_get_cpu() instead.

Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13 19:01:49 +01:00
Max Filippov 604e1f9cd0 target-xtensa: provide HW confg ID registers
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-24 04:47:02 +04:00
Max Filippov 676056d4f1 target-xtensa: refactor standard core configuration
Coalesce all standard configuration sections into single
DEFAULT_SECTIONS macro for all cores. This allows to add new features in
a single place: overlay_tool.h

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-24 04:47:02 +04:00
Max Filippov e848dd4248 target-xtensa: add basic checks to icache opcodes
Check privilege level for privileged instructions (IHU, III, IIU and IPFL
are privileged), memory accessibility for instructions that reference memory
(IH* and IPFL) and windowed register validity for all instruction cache
instructions.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-24 04:47:01 +04:00
Max Filippov 7c84259019 target-xtensa: add basic checks to dcache opcodes
Check privilege level for privileged instructions (DHI, DHU, DII, DIU, DIWB,
DIWBI, DPFL are privileged), memory accessibility for instructions that
reference memory (all DH* and DPFL) and windowed register validity for all
data cache instructions.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-24 04:47:01 +04:00
Max Filippov 6502668237 target-xtensa: add RRRI4 opcode format fields
This encoding is used by cache instructions.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-24 04:47:01 +04:00
Edgar E. Iglesias fdfba1a298 exec: Make ldl_*_phys input an AddressSpace
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11 22:56:54 +10:00
Edgar E. Iglesias 29d8ec7bee exec: Make tb_invalidate_phys_addr input an AS
No functional change.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11 22:55:55 +10:00
Max Filippov ebbfd5a094 target-xtensa: add missing DEBUG section to dc233c config
This fixes missing debug feature opcodes of dc233c core variant.

Cc: qemu-stable@nongnu.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-11-08 09:26:07 +04:00
Max Filippov ca529f8e13 target-xtensa: add in_asm logging
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-10-15 17:23:46 +04:00
Richard Henderson 5cd8f6210f tcg: Move helper registration into tcg_context_init
No longer needs to be done on a per-target basis.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10 11:43:37 -07:00
Richard Henderson b1669e5e32 target: Include softmmu_exec.h where forgotten
Several targets forgot to include softmmu_exec.h, which would
break them with a header cleanup to follow.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02 09:08:30 -07:00
Richard Henderson 8cfd04959a tcg: Change tcg_gen_exit_tb argument to uintptr_t
And update all users.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02 09:08:30 -07:00
Alex Bligh bc72ad6754 aio / timers: Switch entire codebase to the new timer API
This is an autogenerated patch using scripts/switch-timer-api.

Switch the entire code base to using the new timer API.

Note this patch may introduce some line length issues.

Signed-off-by: Alex Bligh <alex@alex.org.uk>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-22 19:14:24 +02:00
Anthony Liguori 64160cd2a3 xtensa queue 2013-07-29
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Merge remote-tracking branch 'filippov/tags/20130729-xtensa' into staging

xtensa queue 2013-07-29

* filippov/tags/20130729-xtensa:
  target-xtensa: check register window inline
  target-xtensa: don't generate dead code to access invalid SRs
  tests/tcg/xtensa: Fix out-of-tree build
  target-xtensa: avoid double-stopping at breakpoints
  target-xtensa: add fallthrough markers
  target-xtensa: add extui unit test

Conflicts:
	configure

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-08-05 08:06:25 -05:00
Max Filippov 908c67fca4 target-xtensa: check register window inline
This lowers time spent in helper_window_check as reported by perf top
from ~8% to ~0.15% accelerating register-intensive tests by ~20%.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-29 18:35:45 +04:00
Max Filippov 0857a06ef7 target-xtensa: don't generate dead code to access invalid SRs
This fixes the following test failure caused by access to undefined SR:

    qemu-system-xtensa -M sim -cpu dc232b -nographic -semihosting  -kernel ./test_sr.tst
    QEMU 1.4.50 monitor - type 'help' for more information
    (qemu) QEMU 1.4.50 monitor - type 'help' for more information
    (qemu) qemu-system-xtensa: tcg/tcg.c:1673: temp_save: Assertion `s->temps[temp].val_type == 2 || s->temps[temp].fixed_reg' failed.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-29 18:35:45 +04:00
Max Filippov a00817cc4c target-xtensa: avoid double-stopping at breakpoints
env->exception_taken is set every time an exception is taken. It is used
to allow single-stepping to stop at the first exception handler
instruction. This however must exclude debug exceptions, as otherwise
first step from the instruction where breakpoint was hit stops at that
same instruction.
Also don't check env->exception_taken directly from the
gen_intermediate_code_internal, instead allocate and use TB flag
XTENSA_TBFLAG_EXCEPTION.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-29 18:35:45 +04:00
Max Filippov 5739006b9a target-xtensa: add fallthrough markers
Explicitly mark cases where we are deliberately falling through to the
following code.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-29 18:24:27 +04:00
Andreas Färber 14a10fc399 cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"
Commit c643bed99 moved qemu_init_vcpu() calls to common CPUState code.
This causes x86 cpu-add to fail with "KVM: setting VAPIC address failed".

The reason for the failure is that CPUClass::kvm_fd is not yet
initialized in the following call graph:
->x86_cpu_realizefn
 ->x86_cpu_apic_realize
  ->qdev_init
   ->device_set_realized
    ->device_reset (hotplugged == 1)
     ->apic_reset_common
      ->vapic_base_update
       ->kvm_apic_vapic_base_update
This causes attempted KVM vCPU ioctls to fail.

By contrast, in the non-hotplug case the APIC is reset much later, when
the vCPU is already initialized.

As a quick and safe solution, move the qemu_init_vcpu() call back into
the targets' realize functions.

Reported-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com>
Acked-by: Igor Mammedov <imammedo@redhat.com> (for i386)
Tested-by: Jia Liu <proljc@gmail.com> (for openrisc)
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29 15:29:15 +02:00
Andreas Färber 5b50e790f9 cpu: Introduce CPUClass::gdb_{read,write}_register()
Completes migration of target-specific code to new target-*/gdbstub.c.

Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-27 00:04:17 +02:00
Andreas Färber 986a299893 gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions
This avoids polluting the global namespace with a non-prefixed macro and
makes it obvious in the call sites that we return.

Semi-automatic conversion using, e.g.,
 sed -i 's/GET_REGL(/return gdb_get_regl(mem_buf, /g' target-*/gdbstub.c
followed by manual tweaking for sparc's GET_REGA() and Coding Style.

Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-27 00:04:17 +02:00