mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Xtensa fixes and improvements 2014-11-03:

Browse Source 
- build fixes for cores w/o windowed registers and with profiling
   interrupts;
 - fix uImage load address for MMUv2 cores;
 - add script for automatic core import from xtensa configuration overlay.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUVqp8AAoJEFH5zJH4P6BEPPoP/RfvGWxWoaC0D4Qxb/NQ7AU9
 wxFSRBiLcSs3ujmV1x9J+t1mxOmhVQDpf8LFSAYWBirHNT8MnN/7AtVwZdCM+XYG
 1j+npJA+JXNGv75TU/Yn/+uZ6uxnZN3GNqz/Bix3jQvL0ghirlFiZUYzuVKSczmX
 NlPgcQwznMuDMPDzVzRqrDBEuCBQlMizNvuhDLsE1R4Iiyzluor8N/qqKRz/rnPD
 5TZ/O4cZ22JbY0hhKh9hmKq3shQhLZpw5Q1ZRU60ORQRve03bXlsOhLl4c9XcdvZ
 ee4bqdX8SR2NVds0n3/CmScCPHqPAZyqzKoOvwYrZPHwG97GtfhGEsPDUILnd6XE
 jYAXBIX+j3Ba0CypbusAV//+Y5T9YmMqsYdDAzO8mMnzgCeVF74zbg1t6Fgq2LNs
 0K/nZ2RCWdGoKZBJEYZyeIaejbiFhRmoJjqZdR3Wsgd1f2ok1NzfhGzMQEjAUL50
 m//xXEBk1/QsKZCTc854HsKDW+Wih8MxHLAvLN55c8Ya2in9GY3sJRzXaKlVETUF
 Oeo6ijhPVDOwtwSuQcfH+NZxRB5rzqYqyGxJrfVIgjyPSNXgZudWOdPWIsYl/bPD
 hn0xh/xiHdpqws2sHytaJTg3A+AMuocPaB3RQLMq4TkUyMZn7zI5dK6oSqXllsjB
 yN/qrhsp54cIldttG8QB
 =M8u6
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/xtensa/tags/20141103-xtensa' into staging

Xtensa fixes and improvements 2014-11-03:
- build fixes for cores w/o windowed registers and with profiling
  interrupts;
- fix uImage load address for MMUv2 cores;
- add script for automatic core import from xtensa configuration overlay.

# gpg: Signature made Sun 02 Nov 2014 22:04:44 GMT using RSA key ID F83FA044
# gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>"
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>"

* remotes/xtensa/tags/20141103-xtensa:
  MAINTAINERS: update xtensa boards
  target-xtensa: fix build for cores w/o windowed registers
  target-xtensa: add core importing script
  hw/xtensa/xtfpga: treat uImage load address as virtual
  hw/core/loader: implement address translation in uimage loader
  target-xtensa: avoid duplicate timer interrupt delivery
  target-xtensa: tests: pre-process tests linker script
  target-xtensa: add definition for XTHAL_INTTYPE_PROFILING

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2014-11-03 16:43:32 +00:00
commit eb5f222b5c
19 changed files with 249 additions and 146 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
MAINTAINERS
View File

@ -583,12 +583,13 @@ Xtensa Machines
sim
M: Max Filippov <jcmvbkbc@gmail.com>
S: Maintained
F: hw/xtensa/xtensa_sim.c
F: hw/xtensa/sim.c
Avnet LX60
XTFPGA (LX60, LX200, ML605, KC705)
M: Max Filippov <jcmvbkbc@gmail.com>
S: Maintained
F: hw/xtensa/xtensa_lx60.c
F: hw/xtensa/xtfpga.c
F: hw/net/opencores_eth.c
Devices
-------

2
hw/arm/boot.c
View File

@ -580,7 +580,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
entry = elf_entry;
if (kernel_size < 0) {
kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
&is_linux);
&is_linux, NULL, NULL);
}
/* On aarch64, it's the bootloader's job to uncompress the kernel. */
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {

17
hw/core/loader.c
View File

@ -477,7 +477,9 @@ static ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src,
/* Load a U-Boot image. */
static int load_uboot_image(const char *filename, hwaddr *ep, hwaddr *loadaddr,
int *is_linux, uint8_t image_type)
int *is_linux, uint8_t image_type,
uint64_t (*translate_fn)(void *, uint64_t),
void *translate_opaque)
{
int fd;
int size;
@ -511,6 +513,9 @@ static int load_uboot_image(const char *filename, hwaddr *ep, hwaddr *loadaddr,
switch (hdr->ih_type) {
case IH_TYPE_KERNEL:
address = hdr->ih_load;
if (translate_fn) {
address = translate_fn(translate_opaque, address);
}
if (loadaddr) {
*loadaddr = hdr->ih_load;
}
@ -587,15 +592,19 @@ out:
}
int load_uimage(const char *filename, hwaddr *ep, hwaddr *loadaddr,
int *is_linux)
int *is_linux,
uint64_t (*translate_fn)(void *, uint64_t),
void *translate_opaque)
{
return load_uboot_image(filename, ep, loadaddr, is_linux, IH_TYPE_KERNEL);
return load_uboot_image(filename, ep, loadaddr, is_linux, IH_TYPE_KERNEL,
translate_fn, translate_opaque);
}
/* Load a ramdisk. */
int load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz)
{
return load_uboot_image(filename, NULL, &addr, NULL, IH_TYPE_RAMDISK);
return load_uboot_image(filename, NULL, &addr, NULL, IH_TYPE_RAMDISK,
NULL, NULL);
}
/* This simply prevents g_malloc in the function below from allocating

3
hw/m68k/an5206.c
View File

@ -74,7 +74,8 @@ static void an5206_init(MachineState *machine)
NULL, NULL, 1, ELF_MACHINE, 0);
entry = elf_entry;
if (kernel_size < 0) {
kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL);
kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL,
NULL, NULL);
}
if (kernel_size < 0) {
kernel_size = load_image_targphys(kernel_filename, KERNEL_LOAD_ADDR,

3
hw/m68k/dummy_m68k.c
View File

@ -50,7 +50,8 @@ static void dummy_m68k_init(MachineState *machine)
NULL, NULL, 1, ELF_MACHINE, 0);
entry = elf_entry;
if (kernel_size < 0) {
kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL);
kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL,
NULL, NULL);
}
if (kernel_size < 0) {
kernel_size = load_image_targphys(kernel_filename,

3
hw/m68k/mcf5208.c
View File

@ -279,7 +279,8 @@ static void mcf5208evb_init(MachineState *machine)
NULL, NULL, 1, ELF_MACHINE, 0);
entry = elf_entry;
if (kernel_size < 0) {
kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL);
kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL,
NULL, NULL);
}
if (kernel_size < 0) {
kernel_size = load_image_targphys(kernel_filename, 0x40000000,

3
hw/microblaze/boot.c
View File

@ -154,7 +154,8 @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
if (kernel_size < 0) {
hwaddr uentry, loadaddr;
kernel_size = load_uimage(kernel_filename, &uentry, &loadaddr, 0);
kernel_size = load_uimage(kernel_filename, &uentry, &loadaddr, 0,
NULL, NULL);
boot_info.bootstrap_pc = uentry;
high = (loadaddr + kernel_size + 3) & ~3;
}

2
hw/openrisc/openrisc_sim.c
View File

@ -72,7 +72,7 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
entry = elf_entry;
if (kernel_size < 0) {
kernel_size = load_uimage(kernel_filename,
&entry, NULL, NULL);
&entry, NULL, NULL, NULL, NULL);
}
if (kernel_size < 0) {
kernel_size = load_image_targphys(kernel_filename,

3
hw/ppc/e500.c
View File

@ -830,7 +830,8 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
* Hrm. No ELF image? Try a uImage, maybe someone is giving us an
* ePAPR compliant kernel
*/
kernel_size = load_uimage(filename, &bios_entry, &loadaddr, NULL);
kernel_size = load_uimage(filename, &bios_entry, &loadaddr, NULL,
NULL, NULL);
if (kernel_size < 0) {
fprintf(stderr, "qemu: could not load firmware '%s'\n", filename);
exit(1);

3
hw/ppc/ppc440_bamboo.c
View File

@ -253,7 +253,8 @@ static void bamboo_init(MachineState *machine)
/* Load kernel. */
if (kernel_filename) {
success = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
success = load_uimage(kernel_filename, &entry, &loadaddr, NULL,
NULL, NULL);
if (success < 0) {
success = load_elf(kernel_filename, NULL, NULL, &elf_entry,
&elf_lowaddr, NULL, 1, ELF_MACHINE, 0);

4
hw/xtensa/pic_cpu.c
View File

@ -31,14 +31,14 @@
void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d)
{
uint32_t old_ccount = env->sregs[CCOUNT];
uint32_t old_ccount = env->sregs[CCOUNT] + 1;
env->sregs[CCOUNT] += d;
if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
int i;
for (i = 0; i < env->config->nccompare; ++i) {
if (env->sregs[CCOMPARE + i] - old_ccount <= d) {
if (env->sregs[CCOMPARE + i] - old_ccount < d) {
xtensa_timer_irq(env, i, 1);
}
}

3
hw/xtensa/xtfpga.c
View File

@ -328,7 +328,8 @@ static void lx_init(const LxBoardDesc *board, MachineState *machine)
} else {
hwaddr ep;
int is_linux;
success = load_uimage(kernel_filename, &ep, NULL, &is_linux);
success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
translate_phys_addr, cpu);
if (success > 0 && is_linux) {
entry_point = ep;
} else {

4
include/hw/loader.h
View File

@ -30,7 +30,9 @@ int load_elf(const char *filename, uint64_t (*translate_fn)(void *, uint64_t),
int load_aout(const char *filename, hwaddr addr, int max_sz,
int bswap_needed, hwaddr target_page_size);
int load_uimage(const char *filename, hwaddr *ep,
hwaddr *loadaddr, int *is_linux);
hwaddr *loadaddr, int *is_linux,
uint64_t (*translate_fn)(void *, uint64_t),
void *translate_opaque);
/**
* load_ramdisk:

1
target-xtensa/cpu.h
View File

@ -266,6 +266,7 @@ typedef enum {
INTTYPE_TIMER,
INTTYPE_DEBUG,
INTTYPE_WRITE_ERR,
INTTYPE_PROFILING,
INTTYPE_MAX
} interrupt_type;

53
target-xtensa/import_core.sh Executable file
View File

@ -0,0 +1,53 @@
#! /bin/bash -e
OVERLAY="$1"
NAME="$2"
FREQ=40000
BASE=$(dirname "$0")
TARGET="$BASE"/core-$NAME
[ $# -ge 2 -a -f "$OVERLAY" ] || { cat <<EOF
Usage: $0 overlay-archive-to-import core-name [frequency-in-KHz]
overlay-archive-to-import: file name of xtensa-config-overlay.tar.gz
to import configuration from.
core-name: QEMU name of the imported core. Must be valid
C identifier.
frequency-in-KHz: core frequency (40MHz if not specified).
EOF
exit
}
[ $# -ge 3 ] && FREQ="$3"
mkdir -p "$TARGET"
tar -xf "$OVERLAY" -C "$TARGET" --strip-components=1 \
--xform='s/core/core-isa/' config/core.h
tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \
sed -n '1,/*\//p;/pc/,/a15/p' > "$TARGET"/gdb-config.c
NUM_REGS=$(grep XTREG "$TARGET"/gdb-config.c | wc -l)
cat <<EOF > "${TARGET}.c"
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/gdbstub.h"
#include "qemu/host-utils.h"
#include "core-$NAME/core-isa.h"
#include "overlay_tool.h"
static const XtensaConfig $NAME __attribute__((unused)) = {
.name = "$NAME",
.gdb_regmap = {
.num_regs = $NUM_REGS,
.reg = {
#include "core-$NAME/gdb-config.c"
}
},
.clock_freq_khz = $FREQ,
DEFAULT_SECTIONS
};
REGISTER_CORE($NAME)
EOF
grep -q core-${NAME}.o "$BASE"/Makefile.objs || \
echo "obj-y += core-${NAME}.o" >> "$BASE"/Makefile.objs

32
target-xtensa/overlay_tool.h
View File

@ -108,20 +108,27 @@
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
#endif
#if XCHAL_HAVE_WINDOWED
#define WINDOW_VECTORS \
[EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
XCHAL_WINDOW_VECTORS_VADDR, \
[EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
XCHAL_WINDOW_VECTORS_VADDR, \
[EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
XCHAL_WINDOW_VECTORS_VADDR, \
[EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
XCHAL_WINDOW_VECTORS_VADDR, \
[EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
XCHAL_WINDOW_VECTORS_VADDR, \
[EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
XCHAL_WINDOW_VECTORS_VADDR,
#else
#define WINDOW_VECTORS
#endif
#define EXCEPTION_VECTORS { \
[EXC_RESET] = XCHAL_RESET_VECTOR_VADDR, \
[EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
XCHAL_WINDOW_VECTORS_VADDR, \
[EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
XCHAL_WINDOW_VECTORS_VADDR, \
[EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
XCHAL_WINDOW_VECTORS_VADDR, \
[EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
XCHAL_WINDOW_VECTORS_VADDR, \
[EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
XCHAL_WINDOW_VECTORS_VADDR, \
[EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
XCHAL_WINDOW_VECTORS_VADDR, \
WINDOW_VECTORS \
[EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
[EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
[EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
@ -163,6 +170,7 @@
#define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
#define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
#define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
#define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING
#define INTERRUPT(i) { \

10
tests/tcg/xtensa/Makefile
View File

@ -13,6 +13,7 @@ SIMFLAGS = --xtensa-core=DC_B_232L --exit_with_target_code $(EXTFLAGS)
SIMDEBUG = --gdbserve=0
endif
HOST_CC = gcc
CC = $(CROSS)gcc
AS = $(CROSS)gcc -x assembler-with-cpp
LD = $(CROSS)ld
@ -21,7 +22,7 @@ XTENSA_SRC_PATH = $(SRC_PATH)/tests/tcg/xtensa
INCLUDE_DIRS = $(XTENSA_SRC_PATH) $(SRC_PATH)/target-xtensa/core-$(CORE)
XTENSA_INC = $(addprefix -I,$(INCLUDE_DIRS))
LDFLAGS = -T$(XTENSA_SRC_PATH)/linker.ld
LDFLAGS = -Tlinker.ld
CRT = crt.o vectors.o
@ -59,13 +60,16 @@ TESTCASES += test_windowed.tst
all: build
linker.ld: $(XTENSA_SRC_PATH)/linker.ld.S
$(HOST_CC) $(XTENSA_INC) -E -P $< -o $@
%.o: $(XTENSA_SRC_PATH)/%.c
$(CC) $(XTENSA_INC) $(CFLAGS) -c $< -o $@
%.o: $(XTENSA_SRC_PATH)/%.S
$(CC) $(XTENSA_INC) $(ASFLAGS) -c $< -o $@
%.tst: %.o $(XTENSA_SRC_PATH)/macros.inc $(CRT) Makefile
%.tst: %.o linker.ld $(XTENSA_SRC_PATH)/macros.inc $(CRT) Makefile
$(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $< -o $@
build: $(TESTCASES)
@ -85,4 +89,4 @@ host-debug-%.tst: %.tst
gdb --args $(SIM) $(SIMFLAGS) ./$<
clean:
$(RM) -fr $(TESTCASES) $(CRT)
$(RM) -fr $(TESTCASES) $(CRT) linker.ld

112
tests/tcg/xtensa/linker.ld
View File

@ -1,112 +0,0 @@
OUTPUT_FORMAT("elf32-xtensa-le")
ENTRY(_start)
__DYNAMIC = 0;
MEMORY {
ram : ORIGIN = 0xd0000000, LENGTH = 0x08000000 /* 128M */
rom : ORIGIN = 0xfe000000, LENGTH = 0x00001000 /* 4k */
}
SECTIONS
{
.init :
{
*(.init)
*(.init.*)
} > rom
.vector :
{
. = 0x00000000;
*(.vector.window_overflow_4)
*(.vector.window_overflow_4.*)
. = 0x00000040;
*(.vector.window_underflow_4)
*(.vector.window_underflow_4.*)
. = 0x00000080;
*(.vector.window_overflow_8)
*(.vector.window_overflow_8.*)
. = 0x000000c0;
*(.vector.window_underflow_8)
*(.vector.window_underflow_8.*)
. = 0x00000100;
*(.vector.window_overflow_12)
*(.vector.window_overflow_12.*)
. = 0x00000140;
*(.vector.window_underflow_12)
*(.vector.window_underflow_12.*)
. = 0x00000180;
*(.vector.level2)
*(.vector.level2.*)
. = 0x000001c0;
*(.vector.level3)
*(.vector.level3.*)
. = 0x00000200;
*(.vector.level4)
*(.vector.level4.*)
. = 0x00000240;
*(.vector.level5)
*(.vector.level5.*)
. = 0x00000280;
*(.vector.level6)
*(.vector.level6.*)
. = 0x000002c0;
*(.vector.level7)
*(.vector.level7.*)
. = 0x00000300;
*(.vector.kernel)
*(.vector.kernel.*)
. = 0x00000340;
*(.vector.user)
*(.vector.user.*)
. = 0x000003c0;
*(.vector.double)
*(.vector.double.*)
} > ram
.text :
{
_ftext = .;
*(.text .stub .text.* .gnu.linkonce.t.* .literal .literal.*)
_etext = .;
} > ram
.rodata :
{
. = ALIGN(4);
_frodata = .;
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
_erodata = .;
} > ram
.data :
{
. = ALIGN(4);
_fdata = .;
*(.data .data.* .gnu.linkonce.d.*)
*(.data1)
_gp = ALIGN(16);
*(.sdata .sdata.* .gnu.linkonce.s.*)
_edata = .;
} > ram
.bss :
{
. = ALIGN(4);
_fbss = .;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
_ebss = .;
_end = .;
} > ram
}
PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4);

130
tests/tcg/xtensa/linker.ld.S Normal file
View File

@ -0,0 +1,130 @@
#include <core-isa.h>
#if XTENSA_HAVE_BE
OUTPUT_FORMAT("elf32-xtensa-be")
#else
OUTPUT_FORMAT("elf32-xtensa-le")
#endif
ENTRY(_start)
__DYNAMIC = 0;
MEMORY {
ram : ORIGIN = XCHAL_VECBASE_RESET_VADDR, LENGTH = 0x08000000 /* 128M */
rom : ORIGIN = XCHAL_RESET_VECTOR_VADDR, LENGTH = 0x00001000 /* 4k */
}
SECTIONS
{
.init :
{
*(.init)
*(.init.*)
} > rom
.vector :
{
. = XCHAL_WINDOW_OF4_VECOFS;
*(.vector.window_overflow_4)
*(.vector.window_overflow_4.*)
. = XCHAL_WINDOW_UF4_VECOFS;
*(.vector.window_underflow_4)
*(.vector.window_underflow_4.*)
. = XCHAL_WINDOW_OF8_VECOFS;
*(.vector.window_overflow_8)
*(.vector.window_overflow_8.*)
. = XCHAL_WINDOW_UF8_VECOFS;
*(.vector.window_underflow_8)
*(.vector.window_underflow_8.*)
. = XCHAL_WINDOW_OF12_VECOFS;
*(.vector.window_overflow_12)
*(.vector.window_overflow_12.*)
. = XCHAL_WINDOW_UF12_VECOFS;
*(.vector.window_underflow_12)
*(.vector.window_underflow_12.*)
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
. = XCHAL_INTLEVEL2_VECOFS;
*(.vector.level2)
*(.vector.level2.*)
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3
. = XCHAL_INTLEVEL3_VECOFS;
*(.vector.level3)
*(.vector.level3.*)
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4
. = XCHAL_INTLEVEL4_VECOFS;
*(.vector.level4)
*(.vector.level4.*)
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5
. = XCHAL_INTLEVEL5_VECOFS;
*(.vector.level5)
*(.vector.level5.*)
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6
. = XCHAL_INTLEVEL6_VECOFS;
*(.vector.level6)
*(.vector.level6.*)
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7
. = XCHAL_INTLEVEL7_VECOFS;
*(.vector.level7)
*(.vector.level7.*)
#endif
. = XCHAL_KERNEL_VECOFS;
*(.vector.kernel)
*(.vector.kernel.*)
. = XCHAL_USER_VECOFS;
*(.vector.user)
*(.vector.user.*)
. = XCHAL_DOUBLEEXC_VECOFS;
*(.vector.double)
*(.vector.double.*)
} > ram
.text :
{
_ftext = .;
*(.text .stub .text.* .gnu.linkonce.t.* .literal .literal.*)
_etext = .;
} > ram
.rodata :
{
. = ALIGN(4);
_frodata = .;
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
_erodata = .;
} > ram
.data :
{
. = ALIGN(4);
_fdata = .;
*(.data .data.* .gnu.linkonce.d.*)
*(.data1)
_gp = ALIGN(16);
*(.sdata .sdata.* .gnu.linkonce.s.*)
_edata = .;
} > ram
.bss :
{
. = ALIGN(4);
_fbss = .;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
_ebss = .;
_end = .;
} > ram
}
PROVIDE(_fstack = (ORIGIN(ram) & 0xf0000000) + LENGTH(ram) - 16);