Commit Graph

676 Commits

Author SHA1 Message Date
Stefan Weil
6681fca3fc Remove unnecessary break statements
Fix these warnings from cppcheck:

hw/display/cirrus_vga.c:2603:
hw/sd/sd.c:348:
hw/timer/exynos4210_mct.c:1033:
target-arm/translate.c:9886:
target-s390x/mem_helper.c:518:
target-unicore32/translate.c:1936:
 style: Consecutive return, break, continue, goto or throw statements are unnecessary.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-06-01 14:25:38 +04:00
Peter Maydell
5b35b4e91d target-arm: Remove gen_{ld,st}* definitions
All the uses of the gen_{ld,st}* functions are gone now, so remove
the functions themselves.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26 10:05:21 +00:00
Peter Maydell
e2592fad17 target-arm: Remove gen_{ld,st}* from thumb2 decoder
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26 10:05:20 +00:00
Peter Maydell
c40c85560b target-arm: Remove gen_{ld,st}* from Thumb insns
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26 10:05:20 +00:00
Peter Maydell
5a839c0d54 target-arm: Remove gen_{ld,st}* from basic ARM insns
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26 10:05:20 +00:00
Peter Maydell
94ee24e7fb target-arm: Remove use of gen_{ld,st}* from ldrex/strex
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26 10:05:20 +00:00
Peter Maydell
58ab8e9646 target-arm: Remove uses of gen_{ld,st}* from Neon code
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26 10:05:20 +00:00
Peter Maydell
29531141a7 target-arm: Remove uses of gen_{ld,st}* from iWMMXt code
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26 10:05:18 +00:00
Peter Maydell
8ed1237d64 target-arm: Remove gen_ld64() and gen_st64()
gen_ld64() and gen_st64() are used only in one place, so just
expand them out.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26 10:05:05 +00:00
Peter Maydell
39d5492a18 target-arm: Don't use TCGv when we mean TCGv_i32
TCGv changes size depending on the compile time value of
TARGET_LONG_BITS.  This is useful for generating code for MIPS style
"instructions are the same but the register width changes" CPUs, and
also for the generic bits of QEMU which operate on "width of a
virtual address" values, but mostly in the ARM target code we were
using it purely as a shorthand for "any 32 bit value".

This needs to change in preparation for AArch64 support, since an
AArch64-capable v8 core will have 64 bit virtual addresses but still
use 32 bit values for the 32 bit instruction set.

This patch mechanically converts all the occurrences of TCGv,
tcg_temp_new(), tcg_temp_free(), tcg_temp_local_new() and
TCGV_UNUSED() to their explicitly 32 bit counterparts.  This is
correct for everything except the arguments to tcg_gen_qemu_{ld,st}*,
which really do need to be TCGv and so will require a 32-to-64
conversion when building the 32 bit code for AArch64.  Those changes
will be in a separate patch for easier review.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26 10:04:54 +00:00
Peter Maydell
536f25e4c7 target-arm: Fix incorrect check of kvm_vcpu_ioctl return value
kvm_vcpu_ioctl() returns -ETHING on error, not ETHING -- correct
an incorrect check in kvm_arch_init_vcpu(). This would not have
had any significant ill-effects -- we would just have propagated
the less useful ENOENT up to the caller rather than the more
accurate EINVAL in the unlikely case that the kernel didn't
have VFP-D32 support.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-05-03 18:47:22 +01:00
Peter Maydell
e91f229a25 target-arm: Correctly restore FPSCR
Use the helper functions to save and restore the FPSCR, so that
we correctly propagate rounding mode and flushing behaviour into
the float_status fields. This also allows us to stop saving the
vector length/stride fields separately.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-04-19 12:24:19 +01:00
Peter Maydell
602131e944 target-arm: Add some missing CPU state fields to VMState
A number of CPU state fields were accidentally omitted from
our migration state: some OMAP specific cp15 registers, and 
some related to state for load/store exclusive insns. Add them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-04-19 12:24:19 +01:00
Juan Quintela
3cc1d20823 target-arm: port ARM CPU save/load to use VMState
Port the ARM CPU save/load code to use VMState. Some state is
saved in a slightly different order to simplify things -- for
example arrays are saved one after the other rather than 'striped',
and we always save all 32 VFP registers even if the CPU happens
to only have 16.

Use one subsection for each feature.  This means that we don't need to
bump the version field each time that a new feature gets introduced.

Signed-off-by: Juan Quintela <quintela@redhat.com>
[PMM: fixed conflicts, updated to use cpu_class_set_vmsd(),  updated
 with new/removed fields since original patch, changed to use custom
 VMStateInfo for cpsr rather than presave/postload hooks, corrected
 subsection names so vmload doesn't fail]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-04-19 12:24:19 +01:00
Peter Chubb
3b3284486b target-arm: Reinsert missing return statement in ARM mode SRS decode
Since patch
   81465888c5
   target-arm: factor out handling of SRS instruction
the ARM mode SRS instruction has not worked in QEMU.

The problem is a missing return directive that was removed in the
refactoring, so after decoding the instruction, qemu would fall through
to generate an UNDEF exception for an illegal instruction.

Signed-off-by: Peter Chubb <peter.chubb@nicta.com.au>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-04-19 12:24:18 +01:00
Peter Maydell
bd2be15003 arm: fix location of some include files
The recent rearrangement of include files had some minor errors:
 devices.h is not ARM specific and should not be in arm/
 arm.h should be in arm/

Move these two headers to correct this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-15 15:16:01 +02:00
Paolo Bonzini
0d09e41a51 hw: move headers to include/
Many of these should be cleaned up with proper qdev-/QOM-ification.
Right now there are many catch-all headers in include/hw/ARCH depending
on cpu.h, and this makes it necessary to compile these files per-target.
However, fixing this does not belong in these patches.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-08 18:13:10 +02:00
Andreas Färber
e6f010cc27 target-arm: Override do_interrupt for ARMv7-M profile
Enable ARMCPUInfo to specify a custom class_init functions.
Introduce arm_v7m_class_init() and use it for "cortex-m3" model.

Instead of forwarding from arm_cpu_do_interrupt() to do_interrupt_v7m(),
override CPUClass::do_interrupt with arm_v7m_cpu_do_interrupt()
in arm_v7m_class_init().

Acked-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-12 10:35:55 +01:00
Andreas Färber
97a8ea5a3a cpu: Replace do_interrupt() by CPUClass::do_interrupt method
This removes a global per-target function and thus takes us one step
closer to compiling multiple targets into one executable.

It will also allow to override the interrupt handling for certain CPU
families.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-12 10:35:55 +01:00
Andreas Färber
c3affe5670 cpu: Pass CPUState to cpu_interrupt()
Move it to qom/cpu.h to avoid issues with include order.

Change pc_acpi_smi_interrupt() opaque to X86CPU.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-12 10:35:55 +01:00
Andreas Färber
259186a7d2 cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.
Explicitly zero them on reset since they were located before
breakpoints.

Pass PowerPCCPU to kvmppc_handle_halt().

Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-12 10:35:55 +01:00
Peter Maydell
eb035b48d5 target-arm: Use MemoryListener to identify GIC base address for KVM
When using an in-kernel GIC with KVM, we need to tell the kernel where
the GIC's memory mapped registers live. Do this by registering a
MemoryListener which tracks where the board model maps the A15's
private peripherals, so we can finish the GIC initialisation
when the GIC is actually mapped.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2013-03-05 00:45:25 +00:00
Peter Maydell
81635574f6 ARM KVM: save and load VFP registers from kernel
Add support for saving and restoring VFP register state from the
kernel. This includes a check that the KVM-created CPU has full
VFP support (as the TCG Cortex-A15 model always does), since for
the moment ARM QEMU doesn't have any way to tweak optional features
on created CPUs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2013-03-05 00:45:13 +00:00
Christoffer Dall
494b00c76a ARM: KVM: Add support for KVM on ARM architecture
Add basic support for KVM on ARM architecture.

Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
[PMM: Minor tweaks and code cleanup, switch to ONE_REG]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2013-03-05 00:45:06 +00:00
Peter Maydell
f5206413af target-arm: Drop CPUARMState* argument from bank_number()
Drop the CPUARMState* argument from bank_number(), since we only
use it for passing to cpu_abort(). Use hw_error() instead.
This avoids propagating further interfaces using env pointers.

In the long term this function's callers need auditing to fix
problems where badly behaved guests can pass invalid bank numbers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
2013-03-05 00:34:40 +00:00
Peter Maydell
00115976bb target-arm: Don't decode RFE or SRS on M profile cores
M profile cores do not have the RFE or SRS instructions, so
correctly UNDEF these insn patterns on those cores.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-03-05 00:31:17 +00:00
Peter Maydell
81465888c5 target-arm: Factor out handling of SRS instruction
Factor out the handling of the SRS instruction rather than
duplicating it between the Thumb and ARM decoders. This in
passing fixes two bugs in the Thumb decoder's SRS handling
which didn't exist in the ARM decoder:
 * (LP:1079080) storing CPSR rather than SPSR (fixed in the
   ARM decoder in commit c67b6b71 in 2009)
 * failing to free the 'addr' TCG temp in the writeback case

Reported-by: Cesson Vincent <vcesson@stmi.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-03-05 00:31:17 +00:00
Peter Maydell
806f352d3d gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
The gen_icount_start/end functions are now somewhat misnamed since they
are useful for generic "start/end of TB" code, used for more than just
icount. Rename them to gen_tb_start/end.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-03-03 14:29:08 +00:00
Andreas Färber
fadf982584 cpu: Introduce ENV_OFFSET macros
Introduce ENV_OFFSET macros which can be used in non-target-specific
code that needs to generate TCG instructions which reference CPUState
fields given the cpu_env register that TCG targets set up with a
pointer to the CPUArchState struct.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-03-03 14:28:28 +00:00
Richard Henderson
e77f083292 target-arm: Fix sbc_CC carry
While T0+~T1+CF = T0-T1+CF-1 is true for the low 32-bits,
it does not produce the correct carry-out to bit 33.  Do
exactly what the manual says.

Using the ~T1 makes the add and subtract code paths nearly
identical, so have sbc_CC use adc_CC.

Cc: Peter Maydell <peter.maydell@linaro.org>
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-02-25 14:32:36 -06:00
Peter Crosthwaite
8c3ac601bd arm/translate.c: Fix adc_CC/sbc_CC implementation
commits 49b4c31efc and
2de68a4900 reworked the implementation of adc_CC
and sub_CC. The new implementations (on the TCG_TARGET_HAS_add2_i32 code path)
are incorrect. The new logic is:

CF:NF = 0:A +/- 0:CF
CF:NF = CF:A +/- 0:B

The lower 32 bits of the intermediate result stored in NF needs to be passes
into the second addition in place of A (s/CF:A/CF:NF):

CF:NF = 0:A +/- 0:CF
CF:NF = CF:NF +/- 0:B

This patch fixes the issue.

Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-02-25 14:32:36 -06:00
Richard Henderson
2de68a4900 target-arm: Implement sbc_cc inline
Use sub2 if available, otherwise use 64-bit arithmetic.

Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23 17:25:29 +00:00
Richard Henderson
49b4c31efc target-arm: Implement adc_cc inline
Use add2 if available, otherwise use 64-bit arithmetic.

Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23 17:25:29 +00:00
Richard Henderson
e3482cb806 target-arm: Use add2 in gen_add_CC
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23 17:25:29 +00:00
Richard Henderson
c9f10124a2 target-arm: Use mul[us]2 and add2 in umlal et al
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23 17:25:29 +00:00
Richard Henderson
831d7fe800 target-arm: Use mul[us]2 in gen_mul[us]_i64_i32
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23 17:25:29 +00:00
Andreas Färber
c05efcb18e cpu: Add CPUArchState pointer to CPUState
The target-specific ENV_GET_CPU() macros have allowed us to navigate
from CPUArchState to CPUState. The reverse direction was not supported.
Avoid introducing CPU_GET_ENV() macros by initializing an untyped
pointer that is initialized in derived instance_init functions.

The field may not be called "env" due to it being poisoned.

Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-02-16 14:51:00 +01:00
Andreas Färber
79614b781d target-arm: Move TCG initialization to ARMCPU initfn
Ensures that a QOM-created ARMCPU is usable.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-02-16 14:50:58 +01:00
Andreas Färber
149692667f target-arm: Update ARMCPU to QOM realizefn
Turn arm_cpu_realize() into a QOM realize function, no longer called
via cpu.h prototype. To maintain the semantics of cpu_init(), set
realized = true explicitly in cpu_arm_init().

Move GDB coprocessor registration, CPU reset and vCPU initialization
into the realizefn.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-02-16 14:50:56 +01:00
Andreas Färber
51492fd1a9 target-arm: Rename CPU types
In the initial conversion of CPU models to QOM types, model names were
mapped 1:1 to type names. As a side effect this gained us a type "any",
which is now a device.

To avoid "-device any" silliness and to pave the way for compiling
multiple targets into one executable, adopt a <name>-<arch>-cpu scheme.
This leads to names like arm926-arm-cpu but is easiest to handle.

No functional changes for -cpu arguments or -cpu ? output.

Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-01-30 16:03:57 +00:00
Peter Maydell
e4c1cfa5cb target-arm: Fix TCG temp leaks for WI and UNDEF VFP sysreg writes
Fix a leak of a TCG temporary in code paths for VFP system register
writes for cases which UNDEF or are write-ignored.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-01-30 16:01:58 +00:00
Andreas Färber
245fb54db5 target-arm: Catch attempt to instantiate abstract type in cpu_init()
This fixes -cpu arm-cpu asserting.

Cc: qemu-stable@nongnu.org
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-27 23:33:34 +01:00
Andreas Färber
5900d6b2d5 target-arm: Detect attempt to instantiate non-CPU type in cpu_init()
Consolidate model checking into a new arm_cpu_class_by_name().

If the name matches an existing type, also check whether that type is
actually (a sub-type of) TYPE_ARM_CPU.

This fixes, e.g., -cpu tmp105 asserting.

Cc: qemu-stable <qemu-stable@nongnu.org>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-27 14:52:04 +01:00
Andreas Färber
55e5c28502 cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using a
negative offset. Therefore the field is placed last in CPUState.

Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.

Move common parts of mips cpu_state_reset() to mips_cpu_reset().

Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
[AF: Rebased onto ppc CPU subclasses and openpic changes]
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-15 04:09:13 +01:00
Alex_Rozenman@mentor.com
314e2296dc target-arm: Fix SWI (SVC) instruction in M profile.
When do_interrupt_v7m is called with EXCP_SWI, the PC already
points to the next instruction. Don't modify it here.

Signed-off-by: Alex Rozenman <Alex_Rozenman@mentor.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-01-11 15:21:22 +00:00
Eduardo Habkost
918fd0839e target-arm: use type_register() instead of type_register_static()
The type_register_static() interface is documented as:

  type_register_static:
  @info: The #TypeInfo of the new type.

  @info and all of the strings it points to should exist for the life
  time that the type is registered.

But cpu_register() uses a stack variable for the 'info' argument, so it
has to use type_register() instead of type_register_static().

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-01-11 15:21:22 +00:00
Andreas Färber
501a7ce727 Merge branch 'master' of git://git.qemu.org/qemu into qom-cpu
Adapt header include paths.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-12-23 00:40:49 +01:00
Andreas Färber
92a3136174 cpu: Introduce CPUListState struct
This generalizes {ARM,M68k,Alpha}CPUListState to avoid declaring it for
each target. Place it in cpu-common.h to avoid circular dependencies.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
2012-12-19 14:08:56 +01:00
Paolo Bonzini
6b4c305cbd fpu: move public header file to include/fpu
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19 08:32:46 +01:00
Paolo Bonzini
9c17d615a6 softmmu: move include files to include/sysemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19 08:32:45 +01:00