qemu/target-arm
Peter Crosthwaite 8c3ac601bd arm/translate.c: Fix adc_CC/sbc_CC implementation
commits 49b4c31efc and
2de68a4900 reworked the implementation of adc_CC
and sub_CC. The new implementations (on the TCG_TARGET_HAS_add2_i32 code path)
are incorrect. The new logic is:

CF:NF = 0:A +/- 0:CF
CF:NF = CF:A +/- 0:B

The lower 32 bits of the intermediate result stored in NF needs to be passes
into the second addition in place of A (s/CF:A/CF:NF):

CF:NF = 0:A +/- 0:CF
CF:NF = CF:NF +/- 0:B

This patch fixes the issue.

Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-02-25 14:32:36 -06:00
..
arm-semi.c exec: move include files to include/exec/ 2012-12-19 08:31:31 +01:00
cpu-qom.h target-arm: Update ARMCPU to QOM realizefn 2013-02-16 14:50:56 +01:00
cpu.c cpu: Add CPUArchState pointer to CPUState 2013-02-16 14:51:00 +01:00
cpu.h target-arm: Update ARMCPU to QOM realizefn 2013-02-16 14:50:56 +01:00
helper.c target-arm: Use mul[us]2 and add2 in umlal et al 2013-02-23 17:25:29 +00:00
helper.h target-arm: Implement sbc_cc inline 2013-02-23 17:25:29 +00:00
iwmmxt_helper.c exec: move include files to include/exec/ 2012-12-19 08:31:31 +01:00
machine.c target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE 2012-07-12 10:59:54 +00:00
Makefile.objs target-arm: final conversion to AREG0 free mode 2012-09-15 17:44:32 +00:00
neon_helper.c exec: move include files to include/exec/ 2012-12-19 08:31:31 +01:00
op_addsub.h Correct spelling of licensed 2011-07-23 11:26:12 -05:00
op_helper.c target-arm: Implement sbc_cc inline 2013-02-23 17:25:29 +00:00
translate.c arm/translate.c: Fix adc_CC/sbc_CC implementation 2013-02-25 14:32:36 -06:00