Commit Graph

80586 Commits

Author SHA1 Message Date
Philippe Mathieu-Daudé
a6b2f1fc36 hw/arm/aspeed: Map the UART5 device unconditionally
The UART5 is present on the machine regardless there is a
character device connected to it. Map it unconditionally.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200905212415.760452-1-f4bug@amsat.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2020-09-18 09:04:36 +02:00
Peter Maydell
de39a045bd vga: fix qxl modular build.
vga: add support for virtio-gpu modular builds.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.22 (GNU/Linux)
 
 iQIcBAABCgAGBQJfYLzlAAoJEEy22O7T6HE4vN0P/0c4XugdxErBoiO+1ZDQ9u6Y
 C2B1rGilpyWfVAEIrTFLtt8gUEfY5buZna8ztAP2put0dh+rygpehbQio1VrfGCU
 3NjvRocVRGutHXAhMI8hVPeb1r3Dq9wJlAIwVhllxJvfDuG6sQkC5bsBFQLjMC3/
 KAYlXr+vyNlCKU1nQH9pgGuNzi+43508GV8ZHLg6U+K7UDErBFUT/j3yVi23IWED
 j8QAdSdZHv93Tggvsg11ydY6jTfJM3IQtDKSYzTx4kwLPeJ297zaGRchku/+KreQ
 vwNlJ93qWTbXTQFJ3DeEuYVXQuCSs+I0P9eMQJFlMkYTwBtUaHvLYkyHN8cOmfGV
 9TdVswdTSFYsLEBHY6ZotzBUEEmhOpcoM7AxRCzmgC/JLE6NVqAv9flVF8TpcbS0
 cdiTaoc86nYqNfPjuZG8TCklo4XHQdluSW0VxvCtwyU8HK54sWs4TO25OwVTr/rP
 VSZWOwkJLSM0k8QrkK4dtmLhLefpd/B91qrD3MUdhKkSPXlK8VZtCwPiTLRr8tbA
 1aPuxxkniEb3miYjjnR7rQcP9CWI4ulLaDgY1js2yX31PJRAGf2emZ0eQEc7nbVI
 yFnEVBElsCeHLbMoLRBMxZMhbD5ICUqudzkKFrmaR2yV66l5qoehhDGziKePQTD6
 CqT9I9SORBVlpAvFJQNs
 =SYNP
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200915-pull-request' into staging

vga: fix qxl modular build.
vga: add support for virtio-gpu modular builds.

# gpg: Signature made Tue 15 Sep 2020 14:08:53 BST
# gpg:                using RSA key 4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138

* remotes/kraxel/tags/vga-20200915-pull-request:
  virtio-gpu: build modular
  virtio-gpu: make virtio_gpu_ops static
  object_initialize: try module load
  meson: remove duplicate qxl sources
  meson: fix module config
  meson: fix qxl dependencies

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-15 14:25:05 +01:00
Gerd Hoffmann
7b0de5b796 virtio-gpu: build modular
Only build virtio-gpu-device modular (the code which actually depends on
the external virglrenderer library).  virtio-gpu-pci and virtio-vga are
compiled into core qemu still.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20200914134224.29769-7-kraxel@redhat.com
2020-09-15 14:11:49 +02:00
Gerd Hoffmann
3b593b3fe4 virtio-gpu: make virtio_gpu_ops static
Reference it via ops pointer instead, simliar to the vga one.
Removes hard symbol reference, needed to build virtio-gpu modular.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20200914134224.29769-6-kraxel@redhat.com
2020-09-15 14:11:49 +02:00
Gerd Hoffmann
64f7aece8e object_initialize: try module load
Needed to allow virtio-gpu-pci initialize the
virtio-gpu-device child device.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20200914134224.29769-5-kraxel@redhat.com
2020-09-15 14:11:49 +02:00
Gerd Hoffmann
f84698ee8b meson: remove duplicate qxl sources
We should add sources to the softmmu_ss or module_ss but not both.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20200914134224.29769-4-kraxel@redhat.com
2020-09-15 14:11:49 +02:00
Gerd Hoffmann
3e292c51ff meson: fix module config
Use all config symbols not only the host ones.
Needed to make sure device configs like CONFIG_QXL
are used for modules too.

Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20200914134224.29769-3-kraxel@redhat.com
2020-09-15 14:11:49 +02:00
Gerd Hoffmann
e3624e8b18 meson: fix qxl dependencies
Add pixman and spice deps to qxl module.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20200914134224.29769-2-kraxel@redhat.com
2020-09-15 14:11:49 +02:00
Peter Maydell
6c938efc27 seccomp branch queue
-----BEGIN PGP SIGNATURE-----
 
 iQFFBAABCAAvFiEE1n4bUJN0hrQHI9ur3zLnwPD/+aIFAl9gnlMRHG90dWJvQHJl
 ZGhhdC5jb20ACgkQ3zLnwPD/+aKVvAgApy9G0dw9vnhf4ohJWfbQqtTvYlrohNJP
 qZtyvAwvO6WAN+j+rj1ZFYYIApzFvlJkslXg14ClyZzg+ySoRVxVJpDjsl+pJ3W+
 zxqbNJlPIkCVelI6MRM2VtdupdjP3oD7Sbba6aICb0t4ScQ8ayjR/PHHZhnJsDaW
 FckihG2AvFrm9kM+hMLX9PbcgZ8dgya0ge6u1TtbbZHZs24UPg97xrTIBtRBpxXi
 mqdMcGrBVzZtWV1L9BbqZl5J6a5ryrrFly9fpqorQU0Lm2wL7U2lfNtubXL8ZzpK
 fCB4cvLNBUHyzzyj/rR9wrl4t0oJQHCWAcK3IY1hyp6tIS8seBKttw==
 =2VG+
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/otubo/tags/pull-seccomp-20200915' into staging

seccomp branch queue

# gpg: Signature made Tue 15 Sep 2020 11:58:27 BST
# gpg:                using RSA key D67E1B50937486B40723DBABDF32E7C0F0FFF9A2
# gpg:                issuer "otubo@redhat.com"
# gpg: Good signature from "Eduardo Otubo (Senior Software Engineer) <otubo@redhat.com>" [full]
# Primary key fingerprint: D67E 1B50 9374 86B4 0723  DBAB DF32 E7C0 F0FF F9A2

* remotes/otubo/tags/pull-seccomp-20200915:
  seccomp: fix killing of whole process instead of thread

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-15 13:05:11 +01:00
Daniel P. Berrangé
e474e3aacf seccomp: fix killing of whole process instead of thread
Back in 2018 we introduced support for killing the whole QEMU process
instead of just one thread, when a seccomp rule is violated:

  commit bda08a5764
  Author: Marc-André Lureau <marcandre.lureau@redhat.com>
  Date:   Wed Aug 22 19:02:48 2018 +0200

    seccomp: prefer SCMP_ACT_KILL_PROCESS if available

Fast forward a year and we introduced a patch to avoid killing the
process for resource control syscalls tickled by Mesa.

  commit 9a1565a03b
  Author: Daniel P. Berrangé <berrange@redhat.com>
  Date:   Wed Mar 13 09:49:03 2019 +0000

    seccomp: don't kill process for resource control syscalls

Unfortunately a logic bug effectively reverted the first commit
mentioned so that we go back to only killing the thread, not the whole
process.

Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Acked-by: Eduardo Otubo <otubo@redhat.com>
2020-09-15 12:56:26 +02:00
Peter Maydell
9b14671aec Block patches:
- Several qcow2 fixes and refactorings
 - Let qemu-img convert try to stay at cluster boundaries
 - Stable child names for quorum (with x-blockdev-change)
 - Explicitly drop vhdx 4k sector support, as it was never actually
   working
 - rbd: Mark @namespace a strong runtime option
 - iotests.py improvements
 - Drop unused runtime_opts objects
 - Skip a test case in 030 when run through make check-block
 -----BEGIN PGP SIGNATURE-----
 
 iQFFBAABCAAwFiEEkb62CjDbPohX0Rgp9AfbAGHVz0AFAl9glvkSHG1yZWl0ekBy
 ZWRoYXQuY29tAAoJEPQH2wBh1c9A/0cH+MR1uFlqNuL4Q8vnZPyEEB6FniWgIF/K
 oMivXdZe9F5UjUPx+2I8iOpzBnT+lMGQZzaNSOZtI9Rv6JqBTjA9xlVWyVo5SVzF
 cNfVE00lCnBRsYGiycOkOyTnP0PuxlFJDRwdozgumch3akN/0Ep9npL7So2BMwVf
 hrPH4VVAihf0ZZaEH9JN2Sgm8/ffpXFcGtg8uoS1NqgK42fGWp4sip6mPFulNDBE
 4HFLv98/hKqBlU5+sYe9mKo7SJSbqEXMxR7AHmDxM9qBbzFF2SPkZoSEaZlqw+bz
 YlR/EDVVbAAAOfKeG8DPjfNwZHVdusMmOpzKTG9QhEOxyK2Vbef1lQ==
 =7AVw
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-09-15' into staging

Block patches:
- Several qcow2 fixes and refactorings
- Let qemu-img convert try to stay at cluster boundaries
- Stable child names for quorum (with x-blockdev-change)
- Explicitly drop vhdx 4k sector support, as it was never actually
  working
- rbd: Mark @namespace a strong runtime option
- iotests.py improvements
- Drop unused runtime_opts objects
- Skip a test case in 030 when run through make check-block

# gpg: Signature made Tue 15 Sep 2020 11:27:05 BST
# gpg:                using RSA key 91BEB60A30DB3E8857D11829F407DB0061D5CF40
# gpg:                issuer "mreitz@redhat.com"
# gpg: Good signature from "Max Reitz <mreitz@redhat.com>" [full]
# Primary key fingerprint: 91BE B60A 30DB 3E88 57D1  1829 F407 DB00 61D5 CF40

* remotes/maxreitz/tags/pull-block-2020-09-15: (22 commits)
  block/rbd: add 'namespace' to qemu_rbd_strong_runtime_opts[]
  qcow2: Convert qcow2_alloc_cluster_offset() into qcow2_alloc_host_offset()
  qcow2: Make preallocate_co() resize the image to the correct size
  block/qcow: remove runtime opts
  block/rbd: remove runtime_opts
  qcow2: Return the original error code in qcow2_co_pwrite_zeroes()
  qcow2: Make qcow2_free_any_clusters() free only one cluster
  qcow2: Handle QCowL2Meta on error in preallocate_co()
  block/vhdx: Support vhdx image only with 512 bytes logical sector size
  iotests: Skip test_stream_parallel in test 030 when doing "make check"
  qemu-img: Explicit number replaced by a constant
  qcow2: Rewrite the documentation of qcow2_alloc_cluster_offset()
  qcow2: Don't check nb_clusters when removing l2meta from the list
  qcow2: Fix removal of list members from BDRVQcow2State.cluster_allocs
  qcow2: Use macros for the L1, refcount and bitmap table entry sizes
  qemu-img: avoid unaligned read requests during convert
  block/quorum.c: stable children names
  qemu-iotests: Simplify FilePath __init__
  qemu-iotests: Merge FilePaths and FilePath
  qemu-iotests: Support varargs syntax in FilePaths
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-15 11:48:40 +01:00
Stefano Garzarella
7bae7c805d block/rbd: add 'namespace' to qemu_rbd_strong_runtime_opts[]
Commit 19ae9ae014 ("block/rbd: Add support for ceph namespaces")
introduced namespace support for RBD, but we forgot to add the
new 'namespace' options to qemu_rbd_strong_runtime_opts[].

The 'namespace' is used to identify the image, so it is a strong
option since it can changes the data of a BDS.

Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1821528
Fixes: 19ae9ae014 ("block/rbd: Add support for ceph namespaces")
Cc: Florian Florensa <fflorensa@online.net>
Signed-off-by: Stefano Garzarella <sgarzare@redhat.com>
Message-Id: <20200914190553.74871-1-sgarzare@redhat.com>
Reviewed-by: Jason Dillaman <dillaman@redhat.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:31:10 +02:00
Alberto Garcia
bfd0989acf qcow2: Convert qcow2_alloc_cluster_offset() into qcow2_alloc_host_offset()
qcow2_alloc_cluster_offset() takes an (unaligned) guest offset and
returns the (aligned) offset of the corresponding cluster in the qcow2
image.

In practice none of the callers need to know where the cluster starts
so this patch makes the function calculate and return the final host
offset directly. The function is also renamed accordingly.

See 388e581615 for a similar change to qcow2_get_cluster_offset().

Signed-off-by: Alberto Garcia <berto@igalia.com>
Message-Id: <9bfef50ec9200d752413be4fc2aeb22a28378817.1599833007.git.berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:31:10 +02:00
Alberto Garcia
8e958260c5 qcow2: Make preallocate_co() resize the image to the correct size
This function preallocates metadata structures and then extends the
image to its new size, but that new size calculation is wrong because
it doesn't take into account that the host_offset variable is always
cluster-aligned.

This problem can be reproduced with preallocation=metadata when the
original size is not cluster-aligned but the new size is. In this case
the final image size will be shorter than expected.

   qemu-img create -f qcow2 img.qcow2 31k
   qemu-img resize --preallocation=metadata img.qcow2 128k

Signed-off-by: Alberto Garcia <berto@igalia.com>
Message-Id: <adeb8b059917b141d5f5b3bd2a016262d3052c79.1599833007.git.berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
[mreitz: Mark compat=0.10 unsupported for iotest 125]
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:30:36 +02:00
John Snow
c1dadda02c block/qcow: remove runtime opts
Introduced by d85f4222b4,
These were seemingly never used at all.

Signed-off-by: John Snow <jsnow@redhat.com>
Message-Id: <20200806211345.2925343-3-jsnow@redhat.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:13 +02:00
John Snow
30b70f070f block/rbd: remove runtime_opts
This saw its last use in 4bfb274165.

Signed-off-by: John Snow <jsnow@redhat.com>
Message-Id: <20200806211345.2925343-2-jsnow@redhat.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:13 +02:00
Alberto Garcia
580384d637 qcow2: Return the original error code in qcow2_co_pwrite_zeroes()
This function checks the current status of a (sub)cluster in order to
see if an unaligned 'write zeroes' request can be done efficiently by
simply updating the L2 metadata and without having to write actual
zeroes to disk.

If the situation does not allow using the fast path then the function
returns -ENOTSUP and the caller falls back to writing zeroes.

If can happen however that the aforementioned check returns an actual
error code so in this case we should pass it to the caller.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Message-Id: <20200909123739.719-1-berto@igalia.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:13 +02:00
Alberto Garcia
3fec237fca qcow2: Make qcow2_free_any_clusters() free only one cluster
This function takes an L2 entry and a number of clusters to free.
Although in principle it can free any type of cluster (using the L2
entry to determine its type) in practice the API is broken because
compressed clusters have a variable size and there is no way to free
more than one without having the L2 entry of each one of them.

The good news all callers are passing nb_clusters=1 so we can simply
get rid of that parameter.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Message-Id: <77cea0f4616f921d37e971b3c5b18a2faa24b173.1599573989.git.berto@igalia.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:13 +02:00
Alberto Garcia
1a52b73dba qcow2: Handle QCowL2Meta on error in preallocate_co()
If qcow2_alloc_cluster_offset() or qcow2_alloc_cluster_link_l2() fail
then this function simply returns the error code, potentially leaking
the QCowL2Meta structure and leaving stale items in s->cluster_allocs.

A second problem is that this function calls qcow2_free_any_clusters()
on failure but passing a host cluster offset instead of an L2 entry.
Luckily for normal uncompressed clusters a raw offset also works like
a valid L2 entry so it works just the same, but we should be using
qcow2_free_clusters() instead.

This patch fixes both problems by using qcow2_handle_l2meta().

Signed-off-by: Alberto Garcia <berto@igalia.com>
Message-Id: <cd3a6b9abd43f9c0b60be413d760f0cacc67eb66.1599573989.git.berto@igalia.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:13 +02:00
Swapnil Ingle
83a6a90009 block/vhdx: Support vhdx image only with 512 bytes logical sector size
block/vhdx uses qemu block layer where sector size is always 512 bytes.
This may have issues  with 4K logical sector sized vhdx image.

For e.g qemu-img convert on such images fails with following assert:

$qemu-img convert -f vhdx -O raw 4KTest1.vhdx test.raw
qemu-img: util/iov.c:388: qiov_slice: Assertion `offset + len <=
qiov->size' failed.
Aborted

This patch adds an check to return ENOTSUP for vhdx images which
have logical sector size other than 512 bytes.

Signed-off-by: Swapnil Ingle <swapnil.ingle@nutanix.com>
Message-Id: <1596794594-44531-1-git-send-email-swapnil.ingle@nutanix.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:13 +02:00
Thomas Huth
33fe08fcaf iotests: Skip test_stream_parallel in test 030 when doing "make check"
The test_stream_parallel test still occasionally fails in the CI.
Thus let's disable it during "make check" for now so that it does
not cause trouble during merge tests. We can enable it again once
the problem has been resolved.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20200907113824.134788-1-thuth@redhat.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:13 +02:00
Yi Li
c075c42f9b qemu-img: Explicit number replaced by a constant
Signed-off-by: Yi Li <yili@winhong.com>
Message-Id: <20200819013607.32280-1-yili@winhong.com>
Reviewed-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:13 +02:00
Alberto Garcia
2b60c5b996 qcow2: Rewrite the documentation of qcow2_alloc_cluster_offset()
The current text corresponds to an earlier, simpler version of this
function and it does not explain how it works now.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Message-Id: <bb5bd06f07c5a05b0818611de0d06ec5b66c8df3.1599150873.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:13 +02:00
Alberto Garcia
f7bd5bba1b qcow2: Don't check nb_clusters when removing l2meta from the list
In the past, when a new cluster was allocated the l2meta structure was
a variable in the stack so it was necessary to have a way to tell
whether it had been initialized and contained valid data or not. The
nb_clusters field was used for this purpose. Since commit f50f88b9fe
this is no longer the case, l2meta (nowadays a pointer to a list) is
only allocated when needed and nb_clusters is guaranteed to be > 0 so
this check is unnecessary.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Message-Id: <ab0b67c29c7ba26e598db35f12aa5ab5982539c1.1599150873.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:13 +02:00
Alberto Garcia
184581fa4d qcow2: Fix removal of list members from BDRVQcow2State.cluster_allocs
When a write request needs to allocate new clusters (or change the L2
bitmap of existing ones) a QCowL2Meta structure is created so the L2
metadata can be later updated and any copy-on-write can be performed
if necessary.

A write request can span a region consisting of an arbitrary
combination of previously unallocated and allocated clusters, and if
the unallocated ones can be put contiguous to the existing ones then
QEMU will do so in order to minimize the number of write operations.

In practice this means that a write request has not just one but a
number of QCowL2Meta structures. All of them are added to the
cluster_allocs list that is stored in BDRVQcow2State and is used to
detect overlapping requests. After the write request finishes all its
associated QCowL2Meta are removed from that list. calculate_l2_meta()
takes care of creating and putting those structures in the list, and
qcow2_handle_l2meta() takes care of removing them.

The problem is that the error path in handle_alloc() also tries to
remove an item in that list, a remnant from the time when this was
handled there (that code would not even be correct anymore because
it only removes one struct and not all the ones from the same write
request).

This can trigger a double removal of the same item from the list,
causing a crash. This is not easy to reproduce in practice because
it requires that do_alloc_cluster_offset() fails after a successful
previous allocation during the same write request, but it can be
reproduced with the included test case.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Message-Id: <3440a1c4d53c4fe48312b478c96accb338cbef7c.1599150873.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:13 +02:00
Alberto Garcia
02b1ecfa10 qcow2: Use macros for the L1, refcount and bitmap table entry sizes
This patch replaces instances of sizeof(uint64_t) in the qcow2 driver
with macros that indicate what those sizes are actually referring to.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Message-Id: <20200828110828.13833-1-berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:12 +02:00
Peter Lieven
af8d43d393 qemu-img: avoid unaligned read requests during convert
in case of large continous areas that share the same allocation status
it happens that the value of s->sector_next_status is unaligned to the
cluster size or even request alignment of the source. Avoid this by
stripping down the s->sector_next_status position to cluster boundaries.

Signed-off-by: Peter Lieven <pl@kamp.de>
Message-Id: <20200901125129.6398-1-pl@kamp.de>
[mreitz: Disable vhdx for 251]
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:12 +02:00
Lukas Straub
5eb9a3c7b0 block/quorum.c: stable children names
If we remove the child with the highest index from the quorum,
decrement s->next_child_index. This way we get stable children
names as long as we only remove the last child.

Signed-off-by: Lukas Straub <lukasstraub2@web.de>
Fixes: https://bugs.launchpad.net/bugs/1881231
Reviewed-by: Zhang Chen <chen.zhang@intel.com>
Reviewed-by: Alberto Garcia <berto@igalia.com>
Message-Id: <5d5f930424c1c770754041aa8ad6421dc4e2b58e.1596536719.git.lukasstraub2@web.de>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:12 +02:00
Nir Soffer
7cc002a06c qemu-iotests: Simplify FilePath __init__
Use list comprehension instead of append loop.

Signed-off-by: Nir Soffer <nsoffer@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <20200828232152.205833-6-nsoffer@redhat.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:12 +02:00
Nir Soffer
3192fad7f7 qemu-iotests: Merge FilePaths and FilePath
FilePath creates now one temporary file:

    with FilePath("a") as a:

Or more:

    with FilePath("a", "b", "c") as (a, b, c):

This is also the behavior of the file_path() helper, used by some of the
tests. Now we have only 2 helpers for creating temporary files instead
of 3.

Signed-off-by: Nir Soffer <nsoffer@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <20200828232152.205833-5-nsoffer@redhat.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:12 +02:00
Nir Soffer
a242b19e80 qemu-iotests: Support varargs syntax in FilePaths
Accept variable number of names instead of a sequence:

    with FilePaths("a", "b", "c") as (a, b, c):

The disadvantage is that base_dir must be used as kwarg:

    with FilePaths("a", "b", base_dir=soc_dir) as (sock1, sock2):

But this is more clear and calling optional argument as positional
arguments is bad idea anyway.

Signed-off-by: Nir Soffer <nsoffer@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <20200828232152.205833-4-nsoffer@redhat.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:12 +02:00
Nir Soffer
f765af87c2 qemu-iotests: Fix FilePaths docstring
When this class was extracted from FilePath, the docstring was not
updated for generating multiple files, and the example usage was
referencing unrelated file.

While fixing the docstring, add example for creating sockets, which
should use iotests.sock_dir instead of the default base_dir.

Fixes: de263986b5
Signed-off-by: Nir Soffer <nsoffer@redhat.com>
Message-Id: <20200828232152.205833-3-nsoffer@redhat.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:12 +02:00
Nir Soffer
a7971702f4 qemu-iotests: Fix FilePaths cleanup
If os.remove() fails to remove one of the paths, for example if the file
was removed by the test, the cleanup loop would exit silently, without
removing the rest of the files.

Fixes: de263986b5
Signed-off-by: Nir Soffer <nsoffer@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <20200828232152.205833-2-nsoffer@redhat.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15 11:05:12 +02:00
Peter Maydell
2d2c73d0e3 * hw/misc/a9scu: Do not allow invalid CPU count
* hw/misc/a9scu: Minor cleanups
  * hw/timer/armv7m_systick: assert that board code set system_clock_scale
  * decodetree: Improve identifier matching
  * target/arm: Clean up neon fp insn size field decode
  * target/arm: Remove KVM support for 32-bit Arm hosts
  * hw/arm/mps2: New board models mps2-an386, mps2-an500
  * Deprecate Unicore32 port
  * Deprecate lm32 port
  * target/arm: Count PMU events when MDCR.SPME is set
  * hw/arm: versal-virt: Correct the tx/rx GEM clocks
  * New Nuvoton iBMC board models npcm750-evb, quanta-gsj
 -----BEGIN PGP SIGNATURE-----
 
 iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAl9fhe4ZHHBldGVyLm1h
 eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3q+XD/47GZyfreMdEZecVVnpJIPx
 mUUy9IdaQddeB7WDqtB5rSRRSGUa2gtvu9bsRgLUjqVLwWHq++JeZabJYB0chCzn
 u0yAO3eMjeffTBooSJ318aBc2pENGoZPwg1JnMpZyL4W/JvXoPD5CUhqXZOmKBoz
 wSIS7nVp6U68G6kAICDOME9z7uXiTrIwA6tFoT87IQxy5BaWcK69e05vJO3coa/d
 GfmV1G13DNNRov9DjVVOFVY9Zwovo9rvZIKsD0+qr/cTWRAHxr7tq9XD9xyMwxsM
 AM3KqH9OiA3U5h771vkbch/NHTte65mYC7cGplpiq+l+4DP0txErPn3hwNX2CE2g
 nsYJbL+NKmbIh9Gj6xVaRgQZyzsl0KgsgS+ZOo9gRyIH8bjgdIsnphffYEnurFnA
 R1f8UHPxZwdJXkcS6RXNb3PYXUb4qcJDrsx1AGpccgQ9jyvBzWiGgOUaaqv6l/Ds
 btehspmxOl/FQd9s7YufhN/azLfsuKP5xxWdE9oYWbC2GcsmghBcyR1P00TcZQRH
 WERWzGUw31OQfXJhGjoBOMkw2PVIoGMVa1/BGb+wO7G8oRg9uFo7BVFz4F5YBGQB
 5Ai5BmqcLlWtAQJNCHJZH5oqRtQIQN6A7poBk52ifSENlZAcocYPIKsxqf6HH9gQ
 CYhEsgk7IYP2YdnQyi5Lhg==
 =mWuB
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200914-1' into staging

 * hw/misc/a9scu: Do not allow invalid CPU count
 * hw/misc/a9scu: Minor cleanups
 * hw/timer/armv7m_systick: assert that board code set system_clock_scale
 * decodetree: Improve identifier matching
 * target/arm: Clean up neon fp insn size field decode
 * target/arm: Remove KVM support for 32-bit Arm hosts
 * hw/arm/mps2: New board models mps2-an386, mps2-an500
 * Deprecate Unicore32 port
 * Deprecate lm32 port
 * target/arm: Count PMU events when MDCR.SPME is set
 * hw/arm: versal-virt: Correct the tx/rx GEM clocks
 * New Nuvoton iBMC board models npcm750-evb, quanta-gsj

# gpg: Signature made Mon 14 Sep 2020 16:02:06 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200914-1: (32 commits)
  tests/acceptance: console boot tests for quanta-gsj
  docs/system: Add Nuvoton machine documentation
  hw/arm/npcm7xx: add board setup stub for CPU and UART clocks
  hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
  hw/ssi: NPCM7xx Flash Interface Unit device model
  hw/mem: Stubbed out NPCM7xx Memory Controller model
  hw/nvram: NPCM7xx OTP device model
  hw/arm: Load -bios image as a boot ROM for npcm7xx
  roms: Add virtual Boot ROM for NPCM7xx SoCs
  hw/arm: Add two NPCM7xx-based machines
  hw/arm: Add NPCM730 and NPCM750 SoC models
  hw/timer: Add NPCM7xx Timer device model
  hw/misc: Add NPCM7xx Clock Controller device model
  hw/misc: Add NPCM7xx System Global Control Registers device model
  hw/arm: versal-virt: Correct the tx/rx GEM clocks
  target/arm: Count PMU events when MDCR.SPME is set
  Deprecate lm32 port
  Deprecate Unicore32 port
  docs/system/arm/mps2.rst: Make board list consistent
  hw/arm/mps2: New board model mps2-an500
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 16:03:08 +01:00
Havard Skinnemoen
4fe986dd44 tests/acceptance: console boot tests for quanta-gsj
This adds two acceptance tests for the quanta-gsj machine.

One test downloads a lightly patched openbmc flash image from github and
verifies that it boots all the way to the login prompt.

The other test downloads a kernel, initrd and dtb built from the same
openbmc source and verifies that the kernel detects all CPUs and boots
to the point where it can't find the root filesystem (because we have no
flash image in this case).

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-15-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 14:24:59 +01:00
Havard Skinnemoen
82c703fea4 docs/system: Add Nuvoton machine documentation
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-14-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 14:24:59 +01:00
Havard Skinnemoen
2ddae9cc04 hw/arm/npcm7xx: add board setup stub for CPU and UART clocks
When booting directly into a kernel, bypassing the boot loader, the CPU and
UART clocks are not set up correctly. This makes the system appear very
slow, and causes the initrd boot test to fail when optimization is off.

The UART clock must run at 24 MHz. The default 25 MHz reference clock
cannot achieve this, so switch to PLL2/2 @ 480 MHz, which works
perfectly with the default /20 divider.

The CPU clock should run at 800 MHz, so switch it to PLL1/2. PLL1 runs
at 800 MHz by default, so we need to double the feedback divider as well
to make it run at 1600 MHz (so PLL1/2 runs at 800 MHz).

We don't bother checking for PLL lock because we know our emulated PLLs
lock instantly.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-13-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 14:24:59 +01:00
Havard Skinnemoen
0eb73f2346 hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
This allows these NPCM7xx-based boards to boot from a flash image, e.g.
one built with OpenBMC. For example like this:

IMAGE=${OPENBMC}/build/tmp/deploy/images/gsj/image-bmc
qemu-system-arm -machine quanta-gsj -nographic \
	-drive file=${IMAGE},if=mtd,bus=0,unit=0,format=raw,snapshot=on

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200911052101.2602693-12-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 14:24:59 +01:00
Havard Skinnemoen
b821242c7b hw/ssi: NPCM7xx Flash Interface Unit device model
This implements a device model for the NPCM7xx SPI flash controller.

Direct reads and writes, and user-mode transactions have been tested in
various modes. Protection features are not implemented yet.

All the FIU instances are available in the SoC's address space,
regardless of whether or not they're connected to actual flash chips.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-11-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 14:24:59 +01:00
Havard Skinnemoen
1351f89246 hw/mem: Stubbed out NPCM7xx Memory Controller model
This just implements the bare minimum to cause the boot block to skip
memory initialization.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-10-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 14:24:59 +01:00
Havard Skinnemoen
c752bb079b hw/nvram: NPCM7xx OTP device model
This supports reading and writing OTP fuses and keys. Only fuse reading
has been tested. Protection is not implemented.

Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-9-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 14:24:59 +01:00
Havard Skinnemoen
4e89ccd685 hw/arm: Load -bios image as a boot ROM for npcm7xx
If a -bios option is specified on the command line, load the image into
the internal ROM memory region, which contains the first instructions
run by the CPU after reset.

If -bios is not specified, the vbootrom included with qemu is loaded by
default.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-8-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 14:24:59 +01:00
Havard Skinnemoen
d1cb5eda67 roms: Add virtual Boot ROM for NPCM7xx SoCs
This is a minimalistic boot ROM written specifically for use with QEMU.
It supports loading the second-stage loader from SPI flash into RAM, SMP
boot, and not much else.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-7-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 14:24:59 +01:00
Havard Skinnemoen
b773acf4a6 hw/arm: Add two NPCM7xx-based machines
This adds two new machines, both supported by OpenBMC:

  - npcm750-evb: Nuvoton NPCM750 Evaluation Board.
  - quanta-gsj: A board with a NPCM730 chip.

They rely on the NPCM7xx SoC device to do the heavy lifting. They are
almost completely identical at the moment, apart from the SoC type,
which currently only changes the reset contents of one register
(GCR.MDLR), but they might grow apart a bit more as more functionality
is added.

Both machines can boot the Linux kernel into /bin/sh.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-6-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 14:24:58 +01:00
Havard Skinnemoen
2d8f048c25 hw/arm: Add NPCM730 and NPCM750 SoC models
The Nuvoton NPCM7xx SoC family are used to implement Baseboard
Management Controllers in servers. While the family includes four SoCs,
this patch implements limited support for two of them: NPCM730 (targeted
for Data Center applications) and NPCM750 (targeted for Enterprise
applications).

This patch includes little more than the bare minimum needed to boot a
Linux kernel built with NPCM7xx support in direct-kernel mode:

  - Two Cortex-A9 CPU cores with built-in periperhals.
  - Global Configuration Registers.
  - Clock Management.
  - 3 Timer Modules with 5 timers each.
  - 4 serial ports.

The chips themselves have a lot more features, some of which will be
added to the model at a later stage.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-5-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 14:24:58 +01:00
Havard Skinnemoen
85fdd74ff0 hw/timer: Add NPCM7xx Timer device model
The NPCM730 and NPCM750 SoCs have three timer modules each holding five
timers and some shared registers (e.g. interrupt status).

Each timer runs at 25 MHz divided by a prescaler, and counts down from a
configurable initial value to zero. When zero is reached, the interrupt
flag for the timer is set, and the timer is disabled (one-shot mode) or
reloaded from its initial value (periodic mode).

This implementation is sufficient to boot a Linux kernel configured for
NPCM750. Note that the kernel does not seem to actually turn on the
interrupts.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-4-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 14:24:58 +01:00
Havard Skinnemoen
e331f79eb8 hw/misc: Add NPCM7xx Clock Controller device model
Enough functionality to boot the Linux kernel has been implemented. This
includes:

  - Correct power-on reset values so the various clock rates can be
    accurately calculated.
  - Clock enables stick around when written.

In addition, a best effort attempt to implement SECCNT and CNTR25M was
made even though I don't think the kernel needs them.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-3-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 14:24:58 +01:00
Havard Skinnemoen
e5a7ba8788 hw/misc: Add NPCM7xx System Global Control Registers device model
Implement a device model for the System Global Control Registers in the
NPCM730 and NPCM750 BMC SoCs.

This is primarily used to enable SMP boot (the boot ROM spins reading
the SCRPAD register) and DDR memory initialization; other registers are
best effort for now.

The reset values of the MDLR and PWRON registers are determined by the
SoC variant (730 vs 750) and board straps respectively.

Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-2-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 14:24:15 +01:00
Edgar E. Iglesias
07fe5bb537 hw/arm: versal-virt: Correct the tx/rx GEM clocks
Correct the GEMs tx/rx clocks to use the 125Mhz fixed-clock.
This matches the setup with the fixed-link 100Mbit PHY.
It also avoids the following warnings from the Linux kernel
driver:

eth0: unable to generate target frequency: 125000000 Hz

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20200909174647.662864-2-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 14:24:15 +01:00
Aaron Lindsay
db1f3afb17 target/arm: Count PMU events when MDCR.SPME is set
This check was backwards when introduced in commit
033614c47d:

    target/arm: Filter cycle counter based on PMCCFILTR_EL0

Cc: qemu-stable@nongnu.org
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14 14:24:15 +01:00