Commit Graph

40679 Commits

Author SHA1 Message Date
Cornelia Huck
9f70b85c40 pc-bios/s390-ccw: rebuild image
Contains:
- Device detection in higher subchannel sets

Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-09-07 16:10:43 +02:00
Alexander Yarygin
0f79b89bc2 pc-bios/s390-ccw: Device detection in higher subchannel sets
If no bootdevice was specified, we try to autodetect a suitable IPL
device. Current code only searched in subchannel set 0; extend this
search to higher subchannel sets as well.

Signed-off-by: Alexander Yarygin <yarygin@linux.vnet.ibm.com>
Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com>
Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-09-07 16:10:43 +02:00
Cornelia Huck
f7822aa8b6 s390x/event-facility: fix location of receive mask
For read event mask, we assumed that the layout of the sccb was

|sccb header|event buffer header|receive mask|...|

The correct layout, however, is

|sccb header|receive mask|...|

as in-buffer and

|sccb header|event buffer header|...|

as out-buffer.

Fix this: This makes selective read work.

Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-09-07 16:10:43 +02:00
Cornelia Huck
6b7741c2be s390x/css: start with cleared cstat/dstat
When executing the start function, we should start with a clear state
regarding subchannel and device status; it is easy to forget updating one
of them after the ccw has been processed.

Note that we don't need to care about resetting the various control
fields: They are cleared by tsch(), and if they were still pending,
we wouldn't be able to execute the start function in the first
place.

Also note that we don't want to clear cstat/dstat if a suspended
subchannel is resumed.

This fixes a bug where we would continue to present channel-program
check in cstat even though later ccw requests for the subchannel
finished without error (i.e. cstat should be 0).

Cc: qemu-stable@nongnu.org
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com>
2015-09-07 16:10:43 +02:00
Cornelia Huck
3335ddddf9 s390x/event-facility: fix receive mask check
For selective read event, we need to check if any event is requested
that is not active instead of whether none of the requested events is
active.

Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com>
Reviewed-by: Eric Farman <farman@linux.vnet.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-09-07 16:10:42 +02:00
Cornelia Huck
fa4463e043 s390x/css: ccw-0 enforces count > 0
Type-0 ccws need to have a count > 0 for any command other than TIC.
Generate a channel-program check if this is not the case.

Reviewed-by: Matthew Rosato <mjrosato@linux.vnet.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-09-07 16:10:42 +02:00
Pierre Morel
fde8206b80 s390x/css: handle ccw-0 TIC correctly
In CCW-0 format TIC command 4 highest bits are ignored in the subchannel.
In CCW-1 format the TIC command 4 highest bits must be 0.
To convert TIC from CCW-0 to CCW-1 we clear the 4 highest bits
to guarantee compatibility.

Signed-off-by: Pierre Morel <pmorel@linux.vnet.ibm.com>
Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-09-07 16:10:42 +02:00
Peter Maydell
4169198617 Block layer patches
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.22 (GNU/Linux)
 
 iQIcBAABAgAGBQJV6fTdAAoJEH8JsnLIjy/WniYP/iSJcVpTj/nEGDPDVrAGAldE
 W3CiFSRbaFTiLvYXp7MDRv5+tV5+ttykhhRlWjOx5BgU616zHh0IiVxuvvGwwCdM
 wl84TpqZ0tUvPFtvZOFE96JS3jcgbz2nu0PA4axIKeIL7aG7L4te35L7Bq7jGwjM
 qrJ5Fg6B4f9Ji8vhphbmCdeZ5slc/mRE7vMAn+5flxvInl3oLexcSUQ9+LZ0iYS5
 ktmGjGNQq1f0Z83hY6k6JKodz0THOPjVh5+seKaJSJjUVpxsMhj+xLDYtEnR2CwV
 13ObNTozStu4IYThD9ydoG2qSFnQGbnn+TrDuyJrhor5wZlmSXolwDGu3qthbBro
 tW9WnvK9fpVPEEyfDNs9NnKiYFERchbgckqTz7MxWJMCdXdPcYIAzFO2SlO1Mznl
 Kv4nEJouOP2CCq/Q6FmUD585uOM8QculKn1Mx8XdPVFvkoYKsvxXWcqRLsf29/Az
 PCt09br+WQE6vbEIGuQjcgBSAgkUDwcuH7jqsyeoiRuKZdAUVyIpsgl4GT28HHk9
 NE8R1TQoBi+4iOvPTWltoSGKi4pj9svqKuHA2YjIaUQtQ18oZleBhVz9Ugm4BFIM
 Se3vUVDKiCNidEITxAmU24ZEXyS+3yTKQQzrvO9zT/b4HJHkOq7I9WIRyqRagCpX
 oBTcbZ9QuuYYF3Z9f2Wi
 =4Pz4
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging

Block layer patches

# gpg: Signature made Fri 04 Sep 2015 20:45:33 BST using RSA key ID C88F2FD6
# gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>"

* remotes/kevin/tags/for-upstream:
  quorum: validate vote threshold against num_children even if read-pattern is fifo
  qcow2: reorder fields in Qcow2CachedTable to reduce padding
  docs: document how to configure the qcow2 L2/refcount caches
  qcow2: add option to clean unused cache entries after some time
  qcow2: mark the memory as no longer needed after qcow2_cache_empty()
  iotests: Warn if python subprocess is killed
  iotests: Do not suppress segfaults in bash tests
  iotests: Respect -nodefaults in tests 41 and 55
  iotests: More options for VM.add_drive()
  qemu-img: Fix crash in amend invocation
  block/raw-posix: Use raw_normalize_devicepath()
  qemu-iotests: s390x: fix test 130
  qemu-iotests: s390x: fix test 049, reject negative sizes in QemuOpts
  qemu-iotests: s390x: fix test 041 and 055
  qemu-iotests: disable default qemu devices for cross-platform compatibility
  qemu-iotests: qemu machine type support

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 11:23:08 +01:00
Peter Maydell
298fae3897 target-arm queue:
* cleanup to use g_new() and friends
  * support semihosting in A64
  * add SMBIOS support to mach-virt
  * remove hw_error() usages
  * fix bug in the AArch32:AArch64 register mapping
  * add a second PCI memory window in highmem on virt board
  * fix bug in arm_excp_unmasked()
  * add i.MX31 SoC
  * remove restriction on handling affinity values in virt board
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABCAAGBQJV7VugAAoJEDwlJe0UNgzeRDEP+weGwHL5bZcHESw9eecJVfmc
 Fv8i+dhXz9aMoOYncvWvyHliou611705nnVo5Mcj/iBimr2ELlH/joBLa4DvkDAM
 AFPZvTgFsAC0bhFSy6gDVI9Q3kIbZ7b4a2TQTbewE61HeE7AERjWphwB6zYp/dDb
 4POeOEPx8C53I4nM61+RdQgwW1zvGMuyb04R1PUyfiAQ33CoAfM/DfH4q6JzZGnq
 kDEfModgo0zT4jfXJ2Pp+a5BIyan3YyuiILOrVCNvEQOcnc2Nl9jN1/IuJNYHOPG
 i5HXrYQya/DyCxmK3SX2JqYZdILcEqYF9q4cjpf92pmwmh3wwzIyfBAfmJ+lmi0A
 tjQ+Q3OVjHZ1ztVvRWofbhUpiYuqKO8y2m1pn4cR1VwR3ZHp2zRzfgfux4h3eSZF
 F33zfnGyPi23lHOnj0l3hvo3piWONYUQ22GJcCE7YC/Ammx4j5yG+5rsikofR3nD
 mqjHsxaZyqdpm/MXWv8o97tBWEMARvRg6GkJeFAxrkhaha/QMCvmNrlWLr+mnIQy
 ggVv4KSbs+aKlXJvCuh3P2z3tmVKoijluHJ7vHvVi9iKfe3SjY/JDpKaQXKqaSRU
 iqm4PZjIP7VmY9+ZboEM7leu7M+4aD/K1jjC43kvvombZgDnDdHumbsZIusjHSMD
 rUdXdgT140zJdWMB5dYl
 =VFdD
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150907' into staging

target-arm queue:
 * cleanup to use g_new() and friends
 * support semihosting in A64
 * add SMBIOS support to mach-virt
 * remove hw_error() usages
 * fix bug in the AArch32:AArch64 register mapping
 * add a second PCI memory window in highmem on virt board
 * fix bug in arm_excp_unmasked()
 * add i.MX31 SoC
 * remove restriction on handling affinity values in virt board

# gpg: Signature made Mon 07 Sep 2015 10:40:48 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"

* remotes/pmaydell/tags/pull-target-arm-20150907: (27 commits)
  arm/virt: Add full-sized CPU affinity handling
  target-arm: Refactor CPU affinity handling
  i.MX: Add i2C devices to i.MX31 SOC
  i.MX: Add qtest support for I2C device emulator.
  i.MX: Add the i.MX25 PDK platform
  i.MX: Add SOC support for i.MX25
  i.MX: Add FEC Ethernet Emulator
  i.MX: Add I2C controller emulator
  i.MX: KZM: use standalone i.MX31 SOC support
  i.MX: Add SOC support for i.MX31
  target-arm: Fix arm_excp_unmasked() function
  hw/arm/virt: Add high MMIO PCI region, 512G in size
  target-arm: Fix AArch32:AArch64 general-purpose register mapping
  arm: Remove hw_error() usages.
  arm: cpu: assert() on no-EL2 virt IRQ error condition.
  smbios: implement smbios support for mach-virt
  smbios: add smbios 3.0 support
  target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
  target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block
  target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:43:18 +01:00
Pavel Fedin
8d45c54d4f arm/virt: Add full-sized CPU affinity handling
At least with KVM, currently there's no reason why QEMU would not be
capable of handling Aff3 != 0. This commit fixes up FDT creation in such
a case.

Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Message-id: eef5a86e6d9a313780dbc23b35fcb65df42a3e9e.1441366248.git.p.fedin@samsung.com
[PMM: folded two overlong lines]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:31 +01:00
Pavel Fedin
0f4a9e45ec target-arm: Refactor CPU affinity handling
Introduces reusable definitions for CPU affinity masks/shifts and gets rid
of hardcoded magic numbers.

Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Message-id: 7e6def4d0d91ae64615cdd2035b94d408d0a23c6.1441366248.git.p.fedin@samsung.com
[PMM: folded overlong line]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:31 +01:00
Jean-Christophe Dubois
d4e26d106a i.MX: Add i2C devices to i.MX31 SOC
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: fb20e6bf5cf946c4530b2cfb55c7e37f5a0fc051.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:31 +01:00
Jean-Christophe Dubois
7f3986278b i.MX: Add qtest support for I2C device emulator.
This is using a ds1338 RTC chip on the I2C bus. This RTC chip is
not present on the real 3DS PDK board.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Acked-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: 05601683a2a95c881cbc9f22651a044d969bd0ae.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:31 +01:00
Jean-Christophe Dubois
65f57c4363 i.MX: Add the i.MX25 PDK platform
Tested by booting a minimal Linux system on the emulated platform
Tested by booting the Xvisor hypervisor on the emulated platform

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: d27347300d253509d921bc27a6d0a14db877478b.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:31 +01:00
Jean-Christophe Dubois
ee708c999d i.MX: Add SOC support for i.MX25
For now we support the following devices:
      * CPU: ARM926
      * Interrupt Controller: AVIC
      * CCM
      * UART x 5
      * EPIT x 2
      * GPT x 4
      * FEC
      * I2C x 3

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: 62218bfa90f9101f79098e768c3d58bd92dcb7f3.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:30 +01:00
Jean-Christophe Dubois
fcbd8018e6 i.MX: Add FEC Ethernet Emulator
This is based on mcf_fec.c FEC implementation for Coldfire

  * A generic PHY was added (borrowwed from LAN9118)
  * The buffer management is also modified as buffers are
    slightly different between Coldfire and i.MX

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: fb314f8a120aa49f8f6ad886f312c649b484fb5a.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:30 +01:00
Jean-Christophe Dubois
20d0f9cf6a i.MX: Add I2C controller emulator
The slave mode is not implemented.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 508dbf2ebe26ec383d3a12a1db5a7890ac8acf20.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:30 +01:00
Jean-Christophe Dubois
f044ac4980 i.MX: KZM: use standalone i.MX31 SOC support
Convert the KZM board to use the i.MX31 SoC defintition instead of
redefining the entire SoC on the machine level. Major rewrite of the
machine init code.

While touching the memory map comment de-indent to the correct level
of indentation.

This obsoletes the legacy i.MX device device creation helpers which are removed.

Tested by booting a minimal Linux system on the emulated platform

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: 5e783561f092e1c939562fdff001f1ab1194b07f.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:30 +01:00
Jean-Christophe Dubois
558df83db7 i.MX: Add SOC support for i.MX31
For now we support the following devices:
  * CPU: ARM1136
  * Interrupt Controller: AVIC
  * CCM
  * UART x 2
  * EPIT x 2
  * GPT

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: f146d819594e41568daec42a1d0f440cdfe3df76.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:30 +01:00
Sergey Sorokin
771842585f target-arm: Fix arm_excp_unmasked() function
There is an error in arm_excp_unmasked() function:
bitwise operator & is used with integer and bool operands
causing an incorrect zeroed result.
The patch fixes it.

Signed-off-by: Sergey Sorokin <afarallax@yandex.ru>
Message-id: 1441209238-16881-1-git-send-email-afarallax@yandex.ru
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:30 +01:00
Pavel Fedin
5125f9cd25 hw/arm/virt: Add high MMIO PCI region, 512G in size
This large region is necessary for some devices like ivshmem and video cards
32-bit kernels can be built without LPAE support. In this case such a kernel
will not be able to use PCI controller which has windows in high addresses.
In order to work around the problem, "highmem" option is introduced. It
defaults to on on, but can be manually set to off in order to be able to run
those old 32-bit guests.

Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
[PMM: Added missing ULL suffixes and a comment to the a15memmap[] entry]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:29 +01:00
Sergey Sorokin
3a9148d0bd target-arm: Fix AArch32:AArch64 general-purpose register mapping
There is an error in functions aarch64_sync_32_to_64() and
aarch64_sync_64_to_32() with mapping of registers between AArch32 and
AArch64.  This commit fixes the mapping to match the v8 ARM ARM
section D1.20.1 (table D1-77).

Signed-off-by: Sergey Sorokin <afarallax@yandex.ru>
Message-id: 1440796451-15276-1-git-send-email-afarallax@yandex.ru
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tidied commit message a bit]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:29 +01:00
Peter Crosthwaite
8f6fd322f6 arm: Remove hw_error() usages.
All of these hw_errors are fatal and indicate something wrong with
QEMU implementation.

Convert to g_assert_not_reached.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: 169194d09017e5725535d31a1507d454c0043706.1440842587.git.crosthwaite.peter@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:29 +01:00
Peter Crosthwaite
f128bf297b arm: cpu: assert() on no-EL2 virt IRQ error condition.
Replace the hw_error() for no-EL2 VIRQ with an assert.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: 93b6acdee6cafe8ff0422a294a5640c3d35f0e17.1440842587.git.crosthwaite.peter@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:29 +01:00
Wei Huang
c30e15658b smbios: implement smbios support for mach-virt
This patch generates smbios tables for ARM mach-virt. Also add
CONFIG_SMBIOS=y for ARM default config.

Acked-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Wei Huang <wei@redhat.com>
Message-id: 1440615870-9518-3-git-send-email-wei@redhat.com
[PMM: Added missing braces around an if().]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:29 +01:00
Wei Huang
8629912006 smbios: add smbios 3.0 support
This patch adds support for SMBIOS 3.0 entry point. When caller invokes
smbios_set_defaults(), it can specify entry point as 2.1 or 3.0. Then
smbios_get_tables() will return the entry point table in right format.

Acked-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Wei Huang <wei@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-id: 1440615870-9518-2-git-send-email-wei@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:28 +01:00
Peter Maydell
8012c84ff9 target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
For the A64 instruction set, the semihosting call instruction
is 'HLT 0xf000'. Wire this up to call do_arm_semihosting()
if semihosting is enabled.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christopher Covington <christopher.covington@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-10-git-send-email-peter.maydell@linaro.org
2015-09-07 10:39:28 +01:00
Peter Maydell
7446d35e1d target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block
The A64 semihosting API changes the interface for SYS_EXIT so
that instead of taking a single exception type in a register,
it takes a parameter block containing the exception type and
a sub-code. Implement this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-9-git-send-email-peter.maydell@linaro.org
2015-09-07 10:39:28 +01:00
Peter Maydell
e9ebfbfcf3 target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call
The A64 semihosting ABI defines a new call SyncCacheRange
for doing a 'clean D-cache and invalidate I-cache' sequence.
Since QEMU doesn't implement caches, we can implement this as a nop.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christopher Covington <christopher.covington@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-8-git-send-email-peter.maydell@linaro.org
2015-09-07 10:39:28 +01:00
Peter Maydell
faacc04161 target-arm/arm-semi.c: Support widening APIs to 64 bits
The 64-bit A64 semihosting API has some pervasive changes from
the 32-bit version:
 * all parameter blocks are arrays of 64-bit values, not 32-bit
 * the semihosting call number is passed in W0
 * the return value is a 64-bit value in X0

Implement the necessary handling for this widening.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christopher Covington <christopher.covington@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-7-git-send-email-peter.maydell@linaro.org
2015-09-07 10:39:28 +01:00
Peter Maydell
44d4a499b7 include/exec/softmmu-semi.h: Add support for 64-bit values
Add support for getting and setting 64-bit values in the
softmmu semihosting support functions. This will be needed
for 64-bit ARM semihosting.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-6-git-send-email-peter.maydell@linaro.org
2015-09-07 10:39:27 +01:00
Peter Maydell
bb19cbc95a target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]'
Factor out a repeated pattern in the semihosting code:

    gdb_do_syscall(arm_semi_cb, "system,%s", arg0, (int)arg1+1);
    /* arm_semi_cb sets env->regs[0] to the syscall return value */
    return env->regs[0];

For A64 the return value will go in a different register; pull
the sequence out into its own function that passes the return
value in a static variable rather than overloading regs[0]
for the purpose, so the code will work on both A32/T32 and A64.

Note that the lack-of-synchronization bug noted in the FIXME
comment is not introduced by this commit, but was already present.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christopher Covington <christopher.covington@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-5-git-send-email-peter.maydell@linaro.org
2015-09-07 10:39:27 +01:00
Peter Maydell
19239b39e7 gdbstub: Implement gdb_do_syscallv()
Implement a variant of the existing gdb_do_syscall() which
takes a va_list.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-4-git-send-email-peter.maydell@linaro.org
2015-09-07 10:39:27 +01:00
Christopher Covington
205ace55ff target-arm: Improve semihosting debug prints
Print semihosting debugging information before the
do_arm_semihosting() call so that angel_SWIreason_ReportException,
which causes the function to not return, gets the same debug prints as
other semihosting calls. Also print out the semihosting call number.

Signed-off-by: Christopher Covington <christopher.covington@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-3-git-send-email-peter.maydell@linaro.org
2015-09-07 10:39:27 +01:00
Peter Maydell
857b55adb7 target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb
A spurious trailing "\n" in the gdb syscall format string used
for SYS_WRITE0 meant that gdb would reject the remote syscall,
with the effect that the output from the guest was silently dropped.
Remove the newline so that gdb accepts the packet.

Cc: qemu-stable@nongnu.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:27 +01:00
Markus Armbruster
b45c03f585 arm: Use g_new() & friends where that makes obvious sense
g_new(T, n) is neater than g_malloc(sizeof(T) * n).  It's also safer,
for two reasons.  One, it catches multiplication overflowing size_t.
Two, it returns T * rather than void *, which lets the compiler catch
more type errors.

This commit only touches allocations with size arguments of the form
sizeof(T).

Coccinelle semantic patch:

    @@
    type T;
    @@
    -g_malloc(sizeof(T))
    +g_new(T, 1)
    @@
    type T;
    @@
    -g_try_malloc(sizeof(T))
    +g_try_new(T, 1)
    @@
    type T;
    @@
    -g_malloc0(sizeof(T))
    +g_new0(T, 1)
    @@
    type T;
    @@
    -g_try_malloc0(sizeof(T))
    +g_try_new0(T, 1)
    @@
    type T;
    expression n;
    @@
    -g_malloc(sizeof(T) * (n))
    +g_new(T, n)
    @@
    type T;
    expression n;
    @@
    -g_try_malloc(sizeof(T) * (n))
    +g_try_new(T, n)
    @@
    type T;
    expression n;
    @@
    -g_malloc0(sizeof(T) * (n))
    +g_new0(T, n)
    @@
    type T;
    expression n;
    @@
    -g_try_malloc0(sizeof(T) * (n))
    +g_try_new0(T, n)
    @@
    type T;
    expression p, n;
    @@
    -g_realloc(p, sizeof(T) * (n))
    +g_renew(T, p, n)
    @@
    type T;
    expression p, n;
    @@
    -g_try_realloc(p, sizeof(T) * (n))
    +g_try_renew(T, p, n)
    @@
    type T;
    expression n;
    @@
    -(T *)g_new(T, n)
    +g_new(T, n)
    @@
    type T;
    expression n;
    @@
    -(T *)g_new0(T, n)
    +g_new0(T, n)
    @@
    type T;
    expression p, n;
    @@
    -(T *)g_renew(T, p, n)
    +g_renew(T, p, n)

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-id: 1440524394-15640-1-git-send-email-armbru@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 10:39:27 +01:00
Kevin Wolf
c804b5791d Block patches from 2015-08-24 until 2015-09-04.
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQEcBAABCAAGBQJV6eqyAAoJEDuxQgLoOKytXJ0H/ifwEz1qvDpwtGRkfm7hI/Tq
 cChw8h5ECf+N4EqS9LGMYpsq/gMnd6iIzw6ERtYHR9HKxpjG/Jyc4tvLy5t20DF/
 Ri59i7Wl703/RDafxiCXwLDpPc+6BLk4reiI3IOzFUhdPkpYflj4FJDhHQS8NolG
 aGQHEK8WEKTI/8gZ4fgQAIDK6mdLQif7kLMHLFQTuY1oRq3Th4FM9UkJtYJS4t3f
 sfqpHytj/cs9JjnI5x7vETYZNfdX4Mlxn9/UJfiVbE6bJ35No1CxZugzzDn6iUh5
 JbNETU5z57OvUENS2R7VvApprTffBJfwJivCydc7hQ6hBb1Q0SaiXwdLruEqX4M=
 =yOUO
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'mreitz/tags/pull-block-for-kevin-2015-09-04' into queue-block

Block patches from 2015-08-24 until 2015-09-04.

# gpg: Signature made Fri Sep  4 21:02:10 2015 CEST using RSA key ID E838ACAD
# gpg: Good signature from "Max Reitz <mreitz@redhat.com>"

* mreitz/tags/pull-block-for-kevin-2015-09-04:
  quorum: validate vote threshold against num_children even if read-pattern is fifo
  qcow2: reorder fields in Qcow2CachedTable to reduce padding
  docs: document how to configure the qcow2 L2/refcount caches
  qcow2: add option to clean unused cache entries after some time
  qcow2: mark the memory as no longer needed after qcow2_cache_empty()

Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2015-09-04 21:43:55 +02:00
Wen Congyang
834cb2ada5 quorum: validate vote threshold against num_children even if read-pattern is fifo
We need to use threshold to check if too many write operation fails.
If threshold is larger than num children, we always get write error
event even if all write operations success.

Signed-off-by: Wen Congyang <wency@cn.fujitsu.com>
Message-id: 55962F72.3060003@cn.fujitsu.com
Reviewed-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2015-09-04 21:00:32 +02:00
Alberto Garcia
909c260c71 qcow2: reorder fields in Qcow2CachedTable to reduce padding
Changing the current ordering saves 8 bytes per cache entry in x86_64.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Message-id: 0bd55291211df3dfb514d0e7d2031dd5c4f9f807.1438690126.git.berto@igalia.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2015-09-04 21:00:32 +02:00
Alberto Garcia
7f65ce834a docs: document how to configure the qcow2 L2/refcount caches
QEMU has options to configure the size of the L2 and refcount
caches for the qcow2 format. However, choosing the right sizes for
a particular disk image is not a straightforward operation since
the ratio between the cache size and the allocated disk space is
not obvious and depends on the size of the cluster and the refcount
entries.

This document attempts to give an overview of both caches and how to
configure their sizes.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-id: 55de928e139b1ba3f3d40fe9c6c88f30b1f36410.1438690126.git.berto@igalia.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2015-09-04 21:00:32 +02:00
Alberto Garcia
279621c046 qcow2: add option to clean unused cache entries after some time
This adds a new 'cache-clean-interval' option that cleans all qcow2
cache entries that haven't been used in a certain interval, given in
seconds.

This allows setting a large L2 cache size so it can handle scenarios
with lots of I/O and at the same time use little memory during periods
of inactivity.

This feature currently relies on MADV_DONTNEED to free that memory, so
it is not useful in systems that don't follow that behavior.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-id: a70d12da60433df9360ada648b3f34b8f6f354ce.1438690126.git.berto@igalia.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2015-09-04 21:00:32 +02:00
Alberto Garcia
355ee2d0e8 qcow2: mark the memory as no longer needed after qcow2_cache_empty()
After having emptied the cache, the data in the cache tables is no
longer useful, so we can tell the kernel that we are done with it. In
Linux this frees the resources associated with it.

The effect of this can be seen in the HMP commit operation: it moves
data from the top to the base image (and fills both caches), then it
empties the top image. At this point the data in that cache is no
longer needed so it's just wasting memory.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-id: 08538b098e1faf6c92496477cf9b47a20e5aacea.1438690126.git.berto@igalia.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2015-09-04 21:00:32 +02:00
Max Reitz
2ef6093cd6 iotests: Warn if python subprocess is killed
Currently, if a subprocess of a python test (i.e. qemu-io, qemu-img, or
qemu) receives a signal and is subsequently aborted, this is not logged.

This patch makes python tests always check the exit code of these
subprocesses, and emit a message if they have been killed.

Signed-off-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2015-09-04 20:59:48 +02:00
Max Reitz
934659c460 iotests: Do not suppress segfaults in bash tests
Currently, if a qemu/qemu-io/qemu-img/qemu-nbd invocation receives a
segmentation fault, that message is invisible in most cases since the
output is generally filtered and bash suppresses the segmentation fault
notice for any but the last element of a pipe.

Most of the time, the test will then fail anyway because of missing
output, but not necessarily (as happened with test 82 recently).

Fix this by making the corresponding environment variables point to
wrapper functions which execute the respective command in a subshell.

Giving options to qemu/qemu-io/qemu-img and path names with spaces were
broken for the Python tests; this patch "accidentally" fixes that.

Signed-off-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2015-09-04 20:59:48 +02:00
Max Reitz
0ed82f7a09 iotests: Respect -nodefaults in tests 41 and 55
While -nodefaults is set in $QEMU_OPTIONS, this is currently (wrongly)
ignored for Python iotests. In order to be prepared for when this is
fixed, we should explicitly add an IDE CD-ROM drive instead of relying
on it being created automatically.

Signed-off-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2015-09-04 20:59:48 +02:00
Max Reitz
8e4922535b iotests: More options for VM.add_drive()
This patch allows specifying the interface to be used for the drive, and
makes specifying a path optional (if the path is None, the "file" option
will be omitted, thus creating an empty drive).

Signed-off-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2015-09-04 20:59:48 +02:00
Max Reitz
e814dffcc9 qemu-img: Fix crash in amend invocation
Example:
$ ./qemu-img create -f qcow2 /tmp/t.qcow2 64M
$ ./qemu-img amend -f qcow2 -o backing_file=/tmp/t.qcow2, -o help \
    /tmp/t.qcow2

This should not crash. This actually is tested by iotest 082, but not
caught due to the segmentation fault being silent (which is something
that needs to be fixed, too).

Reported-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2015-09-04 20:59:48 +02:00
Max Reitz
bdd03cdf5d block/raw-posix: Use raw_normalize_devicepath()
The filename given to qemu_open() in block/raw-posix.c should generally
have been processed by raw_normalize_devicepath(); unless we are only
probing (in which case the caller often checks whether the file is a
block device or not, and this property will be changed by
raw_normalize_devicepath() on NetBSD) or it is about a deprecated device
(i.e. floppy).

Signed-off-by: Max Reitz <mreitz@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2015-09-04 20:59:48 +02:00
Bo Tu
137a905fdf qemu-iotests: s390x: fix test 130
The default device id of hard disk on the s390 platform is "virtio0"
which differs to the "ide0-hd0" for the x86 platform. Setting id in
the drive definition, ie:"qemu -drive id=testdisk", will be the same
on all platforms.

Reviewed-by: Max Reitz <mreitz@redhat.com>
Signed-off-by: Bo Tu <tubo@linux.vnet.ibm.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2015-09-04 20:59:48 +02:00
Bo Tu
212789925e qemu-iotests: s390x: fix test 049, reject negative sizes in QemuOpts
when creating an image qemu-img enable us specifying the size of the
image using -o size=xx options. But when we specify an invalid size
such as a negtive size then different platform gives different result.

parse_option_size() function in util/qemu-option.c will be called to
parse the size, a cast was called in the function to cast the input
(saved as a double in the function) size to an unsigned int64 value,
when the input is a negtive value or exceeds the maximum of uint64, then
the result is undefined.

According to C99 6.3.1.4, the result of converting a floating point
number to an integer that cannot represent the (integer part of) number
is undefined.  And sure enough the results are different on x86 and
s390.

C99 Language spec 6.3.1.4 Real floating and integers:
the result of this assignment/cast is undefined if the float is not
in the open interval (-1, U<type>_MAX+1).

Reviewed-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Sascha Silbe <silbe@linux.vnet.ibm.com>
Signed-off-by: Bo Tu <tubo@linux.vnet.ibm.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2015-09-04 20:59:48 +02:00