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9f4576f08b
Commit Graph

326 Commits

Author SHA1 Message Date
blueswir1
9f4576f08b Fix array subscript above array bounds error 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5219 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-14 19:16:21 +00:00
blueswir1
72ccba795b Fix mulscc with high bits set in either src1 or src2 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5201 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-13 17:20:52 +00:00
blueswir1
5068cbd9e9 Write zeros to high bits of y, based on patch by Vince Weaver 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5196 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-11 16:01:02 +00:00
blueswir1
d84763bc17 Convert rest of ops using float32 to TCG, remove FT0 and FT1 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5193 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-10 20:09:22 +00:00
blueswir1
c5d04e99f3 Partially convert float128 conversion ops to TCG 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5192 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-10 20:00:18 +00:00
blueswir1
e2ea21b396 Convert basic 64 bit VIS ops to TCG 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5191 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-10 19:57:35 +00:00
blueswir1
1d01299d29 Convert basic 32 bit VIS ops to TCG 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5190 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-10 19:57:13 +00:00
blueswir1
714547bbc7 Convert basic float32 ops to TCG 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5189 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-10 19:54:51 +00:00
blueswir1
3a3b925d47 Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCG 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5185 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-09 19:02:49 +00:00
blueswir1
510aba20f0 Fix a typo in fpsub32 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5177 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-06 17:54:01 +00:00
blueswir1
255e1fcb5a Convert most env fields to TCG registers 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5176 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-06 17:51:43 +00:00
blueswir1
47ad35f16a Silence gcc warning about constant overflow 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5175 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-06 17:50:16 +00:00
blueswir1
e83ce55068 Implement no-fault loads 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5148 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-03 17:32:10 +00:00
blueswir1
b991c38519 Fix sign extension problems with smul and umul (Vince Weaver) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5138 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-02 16:33:23 +00:00
blueswir1
105a1f04b5 Fix y register loads and stores 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5123 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-01 19:35:29 +00:00
blueswir1
c8f9349ad9 Remove memcpy32() prototype leftover from r5109 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5114 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-30 09:22:10 +00:00
blueswir1
ba6a9d8cda Fix FCC handling for Sparc64 target, initial patch by Vince Weaver 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5110 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-29 21:03:31 +00:00
blueswir1
91736d378b Fix Sparc64 boot on i386 host: 
- move do_interrupt() back to op_helper.c
 - move non-helper prototypes from helper.h to exec.h
 - move some prototypes from cpu.h to exec.h
 - do not export either set_cwp() or cpu_set_cwp() from op_helper.c,
   but instead provide inline functions


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5109 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-29 20:50:21 +00:00
blueswir1
7621a90da8 Fix udiv and sdiv on Sparc64 (Vince Weaver) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5085 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-25 19:43:53 +00:00
blueswir1
c93e7817ee Fix wrwim masking (Luis Pureza) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5043 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-21 17:34:42 +00:00
blueswir1
5578ceab94 Use initial CPU definition structure for some CPU fields instead of copying 
them around, based on patch by Luis Pureza.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5042 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-21 17:33:42 +00:00
blueswir1
2ae72bce02 Correct 32bit carry flag for add instruction (Igor Kovalenko) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5017 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-17 08:33:47 +00:00
blueswir1
06057e6f6c Fix faligndata (Vince Weaver) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4992 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-06 19:50:16 +00:00
blueswir1
43e9e742b9 Fix I/D MMU tag reads 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4991 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-06 18:16:08 +00:00
blueswir1
01b1fa6d16 Fix Sparc64 shifts 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4990 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-06 18:13:54 +00:00
blueswir1
95f9397c75 Fix offset handling for ASI loads and stores (Vince Weaver) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4988 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-06 15:28:20 +00:00
blueswir1
a7a044f29e Handle wrapped registers correctly when saving 
Fix typo
Save and load interrupt_index and pil_in
Original patch by Luis Pureza


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4980 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-01 15:13:58 +00:00
blueswir1
dd5e6304aa Fix cmp/subcc/addcc op bugs reported by Vince Weaver 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4970 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-29 18:11:20 +00:00
blueswir1
c19148bd8f Make MAXTL dynamic, bounds check tl when indexing 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4942 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-25 07:42:14 +00:00
blueswir1
0b8f1b102b Sparc32: save/load all MMU registers, Sparc64: add CPU save/load 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4938 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-24 11:28:51 +00:00
blueswir1
c7ba218da1 Add T1 and T2 CPUs, add a Sun4v machine 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4923 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-22 07:07:34 +00:00
blueswir1
74b9decc47 Use MMU globals for some MMU traps 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4918 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-21 18:43:32 +00:00
blueswir1
8eba209e33 Fix reset vector 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4917 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-21 11:17:23 +00:00
blueswir1
f76981b113 Print default and available CPU features separately 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4912 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-20 18:23:50 +00:00
blueswir1
fb79ceb91a Make UA200x features selectable, add MMU types 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4911 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-20 18:22:16 +00:00
blueswir1
7f626233a0 Remove unused variable 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4908 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-19 18:35:29 +00:00
blueswir1
db166940e2 Implement nucleus quad ldda 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4902 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-19 13:25:28 +00:00
blueswir1
f617a9a6bb Update TLB miss addresses 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4897 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-19 10:04:48 +00:00
ths
2cfc5f17d3 Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-18 18:01:29 +00:00
blueswir1
8d7d8c4bb1 wrhpr hstick_cmpr is a store, not a load 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4887 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-18 10:26:07 +00:00
blueswir1
e6bf7d70b5 Fix saving and loading of trap state 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4883 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-17 19:17:19 +00:00
blueswir1
2cade6a3f6 Support for address masking 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4882 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-17 12:53:05 +00:00
blueswir1
a5a52cf246 Fix MMU registers, add more E-cache ASIs 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4881 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-16 16:58:49 +00:00
blueswir1
e19e4efeaa Fix MMU miss traps 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4880 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-16 16:55:52 +00:00
blueswir1
c5f2f66835 Flushw can generate exceptions, so save PC & NPC 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4876 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-16 11:51:15 +00:00
blueswir1
71817e4898 Really fix cas 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4869 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-15 14:52:09 +00:00
blueswir1
f7350b47da Implement some Ultrasparc cache ASIs used by SILO 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4858 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-08 15:51:32 +00:00
pbrook
9656f324d2 Move interrupt_request and user_mode_only to common cpu state. 
Save and restore env->interrupt_request and env->halted.



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-01 20:01:19 +00:00
pbrook
b3c7724cbc Move CPU save/load registration to common code. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-30 16:31:04 +00:00
pbrook
2e70f6efa8 Add instruction counter. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-29 01:03:05 +00:00