Commit Graph

64672 Commits

Author SHA1 Message Date
Stefan Markovic
5dd0db52e6 linux-user: Extract MIPS abiflags from ELF file
Read MIPS.abiflags section from ELF file into Mips_elf_abiflags_v0 struct.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-10-29 15:50:31 +01:00
Stefan Markovic
74cfc704e5 linux-user: Extend image_info struct with MIPS fp_abi and interp_fp_abi fields
Add MIPS specific image_info struct fields fp_abi and interp_fp_abi
to store executable and interpreter fp_abi values (based on kernel
struct arch_elf_state in mips/include/asm/elf.h).

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-10-29 15:50:23 +01:00
Stefan Markovic
3f8e8ac331 elf: Define MIPS_ABI_FP_UNKNOWN macro
Add MIPS_ABI_FP_UNKNOWN as QEMU internal value to represent
unknown fp_abi (based on kernel mips/include/asm/elf.h definition)

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-10-29 15:47:32 +01:00
Aleksandar Markovic
093ade1217 target/mips: Amend MXU ASE overview note
Add prefix, suffix, operation descriptions, and other corrections
and amendments to the comment that describes MXU ASE.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:59 +01:00
Aleksandar Markovic
e5bf8a0829 target/mips: Move MXU_EN check one level higher
Move MXU_EN check to the main MXU decoding function, to avoid code
repetition.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:53 +01:00
Craig Janeczek
4ca837218c target/mips: Add emulation of MXU instructions S32LDD and S32LDDR
Add support for emulating the S32LDD and S32LDDR MXU instructions.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:53 +01:00
Craig Janeczek
a9a4181bdb target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU
Adds support for emulating the Q8MUL and Q8MULSU MXU instructions.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:53 +01:00
Craig Janeczek
e67915b427 target/mips: Add emulation of MXU instruction D16MAC
Add support for emulating the D16MAC MXU instruction.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:53 +01:00
Craig Janeczek
72c9bcf89c target/mips: Add emulation of MXU instruction D16MUL
Add support for emulating the D16MUL MXU instruction.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:53 +01:00
Craig Janeczek
be57bcdb2e target/mips: Add emulation of MXU instruction S8LDD
Add support for emulating the S8LDD MXU instruction.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:53 +01:00
Aleksandar Markovic
87860df551 target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch
Move MUL, S32M2I, S32I2M handling out of switch. These are all
instructions that do not depend on MXU_EN flag of MXU_CR.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:53 +01:00
Craig Janeczek
96992d1aa1 target/mips: Add emulation of MXU instructions S32I2M and S32M2I
Add support for emulating the S32I2M and S32M2I MXU instructions.
This commit also contains utility functions for reading/writing
to MXU registers. This is required for overall MXU instruction
support.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:53 +01:00
Craig Janeczek
11d56f6103 target/mips: Add emulation of non-MXU MULL within MXU decoding engine
Add emulation of non-MXU MULL within MXU decoding engine.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:53 +01:00
Craig Janeczek
53f1131fde target/mips: Add bit encoding for MXU operand getting pattern 'optn3'
Add bit encoding for MXU operand getting pattern 'optn3'.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:53 +01:00
Craig Janeczek
a35723f4ce target/mips: Add bit encoding for MXU operand getting pattern 'optn2'
Add bit encoding for MXU operand getting pattern 'optn2'.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:47 +01:00
Aleksandar Markovic
5bb2999239 target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'
Add bit encoding for MXU execute 2-bit add/subtract pattern 'eptn2'.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:47 +01:00
Craig Janeczek
b70bb918e2 target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'
Add bit encoding for MXU accumulate add/subtract 2-bit pattern
'aptn2'.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:47 +01:00
Aleksandar Markovic
d67da33786 target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1'
Add bit encoding for MXU accumulate add/subtract 1-bit pattern
'aptn1'.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:47 +01:00
Aleksandar Markovic
03f400883a target/mips: Add MXU decoding engine
Add MXU decoding engine: add handlers for all instruction pools,
and main decode handler. The handlers, for now, for the purpose
of this patch, contain only sceleton in the form of a single
switch statement.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:47 +01:00
Aleksandar Markovic
0a348b9a4e target/mips: Add and integrate MXU decoding engine placeholder
Provide the placeholder and add the invocation logic for MXU
decoding engine.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:47 +01:00
Aleksandar Markovic
eab0bdb07c target/mips: Amend MXU instruction opcodes
Amend MXU instruction opcodes. Pool04 is actually only instruction
OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit
subfield 'aptn1'.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:47 +01:00
Craig Janeczek
a031ac6161 target/mips: Define a bit for MXU in insn_flags
Define a bit for MXU in insn_flags. This is the first non-MIPS
(third party) ASE supported in QEMU for MIPS, so it is placed in
the section "bits 56-63: vendor-specific ASEs".

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:47 +01:00
Craig Janeczek
eb5559f67d target/mips: Introduce MXU registers
Define and initialize the 16 MXU registers - 15 general computational
register, and 1 control register). There is also a zero register, but
it does not have any corresponding variable.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:47 +01:00
Aleksandar Markovic
2431a422d3 target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases
Coverity found two fallthroughs that miss break statement. Fix them.

Revieved-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29 14:13:30 +01:00
Peter Maydell
285278ca78 Testing patches
One fix for mingw build and some improvements in VM based testing, many thanks
 to Paolo and Phil.
 -----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEEUAN8t5cGD3bwIa1WyjViTGqRccYFAlvTIXEQHGZhbXpAcmVk
 aGF0LmNvbQAKCRDKNWJMapFxxlRqB/99FX5texTlvPy2yH8jC6eXWt1XzcqVc9Ei
 TPHJ3LLR7EqjTBD/NCgvRzed4D0U2uRm8rXssujJPUnqt9hmlpNPzIEqLeV650hB
 QBWWC8rrxzPMGKbQzBE0b/bbAaXW4KFsBXicmrTJz6MCN12S4yGwMJg3B7yAeXtp
 2cVjhmoXiynx7qsWjKl8+hvSmCSMYvsfNygHGbFaLdr/CB8+ug/5fRg2yrhWz68U
 emcjljgHRiZpKy8Kn0F0lKTPqKCYi0EVxoDk424c2Ag+oGZsxvhJMolPooOWVXCX
 8bfmzyRR2aPi9m8bfp42+yqYYopD/ncr2zF65+6OYtTA2GfxiywG
 =wIx1
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/famz/tags/testing-pull-request' into staging

Testing patches

One fix for mingw build and some improvements in VM based testing, many thanks
to Paolo and Phil.

# gpg: Signature made Fri 26 Oct 2018 15:15:13 BST
# gpg:                using RSA key CA35624C6A9171C6
# gpg: Good signature from "Fam Zheng <famz@redhat.com>"
# Primary key fingerprint: 5003 7CB7 9706 0F76 F021  AD56 CA35 624C 6A91 71C6

* remotes/famz/tags/testing-pull-request:
  tests/vm: Do not abuse parallelism when HOST != TARGET architecture
  tests/vm: Do not use -enable-kvm if HOST != TARGET architecture
  tests/vm: Let kvm_available() work in cross environments
  tests/vm: Add a BaseVM::arch property
  tests/vm: Display remaining seconds to wait for a VM to start
  tests/vm: Do not use the -smp option with a single cpu
  tests/vm: Do not abuse parallelism when KVM is not available
  tests/vm: Extract the kvm_available() handy function
  tests: docker: update test-mingw for GTK+ 2.0 removal

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-27 19:55:08 +01:00
Peter Maydell
179f9ac887 MIPS queue for October 2018 - part 3
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJb0iQKAAoJENSXKoln91plUngH/icGvr5sa6JbT/4bDP20Wv7y
 gwJ8Ax6kKDU4Z/JbBt+2diXVRrPXCF6xt/dvcaWCnxKyjIZN0i2azHv75jtMEA5t
 +khdqqREzTZ8RiEI+u0r+OkSNJ3837O+ahQFdRxjqSDIScC8mcwW8h1md9ThjzbQ
 yBhRvNo8QkXGGx9MCWZ7kUGkPnJDQnL0jGiFj0xhtyDSGXfnnOpUgpQKRWu5cQzl
 Q7JKFPQgt676kd6UyG7f+xYw/a6uERmMBWp30CfN6bP4bPcdFHdUlgIM60VRAfhA
 qYA4led5sWcuqmA96PoZIOc+05/8Q8NkgP+nYbXeMkW8/9QOCPa/30p7QayOpZA=
 =F4up
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-oct-2018-part-3' into staging

MIPS queue for October 2018 - part 3

# gpg: Signature made Thu 25 Oct 2018 21:14:02 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-oct-2018-part-3:
  target/mips: Add disassembler support for nanoMIPS
  target/mips: Implement emulation of nanoMIPS EVA instructions
  target/mips: Add nanoMIPS CRC32 instruction pool

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-26 20:16:38 +01:00
Philippe Mathieu-Daudé
63a24c5e23 tests/vm: Do not abuse parallelism when HOST != TARGET architecture
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20181013004034.6968-9-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26 22:03:21 +08:00
Philippe Mathieu-Daudé
71531bb591 tests/vm: Do not use -enable-kvm if HOST != TARGET architecture
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20181013004034.6968-8-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26 22:03:21 +08:00
Philippe Mathieu-Daudé
67a52f3456 tests/vm: Let kvm_available() work in cross environments
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20181013004034.6968-7-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26 22:03:21 +08:00
Philippe Mathieu-Daudé
31719c37f5 tests/vm: Add a BaseVM::arch property
The 'arch' property gives a hint on which architecture the guest image runs.

This can be use to select the correct QEMU binary path.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20181013004034.6968-6-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26 22:03:21 +08:00
Philippe Mathieu-Daudé
f5d3d21847 tests/vm: Display remaining seconds to wait for a VM to start
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20181013004034.6968-5-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26 22:03:21 +08:00
Philippe Mathieu-Daudé
071cf5a420 tests/vm: Do not use the -smp option with a single cpu
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20181013004034.6968-4-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26 22:03:21 +08:00
Philippe Mathieu-Daudé
8a6e007e78 tests/vm: Do not abuse parallelism when KVM is not available
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20181013004034.6968-3-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26 22:03:21 +08:00
Philippe Mathieu-Daudé
b59b82eded tests/vm: Extract the kvm_available() handy function
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20181013004034.6968-2-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26 22:03:21 +08:00
Paolo Bonzini
1578466c9a tests: docker: update test-mingw for GTK+ 2.0 removal
--with-gtkabi does not exist anymore; remove it from the configure invocation.

Fixes: 89d85cde75
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <1539886203-33670-1-git-send-email-pbonzini@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26 22:03:21 +08:00
Aleksandar Markovic
89a955e8df target/mips: Add disassembler support for nanoMIPS
Add disassembler support for nanoMIPS.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Matthew Fortune <matthew.fortune@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-25 22:13:33 +02:00
Dimitrije Nikolic
d046a9ea1b target/mips: Implement emulation of nanoMIPS EVA instructions
Implement emulation of nanoMIPS EVA instructions. They are all
part of P.LS.E0 instruction pool, or one of its subpools.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-25 22:13:33 +02:00
Aleksandar Markovic
ba1e81171f target/mips: Add nanoMIPS CRC32 instruction pool
Add nanoMIPS CRC32 instruction pool.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-25 22:13:33 +02:00
Peter Maydell
6e6ffc9ffa Machine queue, 2018-10-25
* sysbus init/realize cleanups
   (Cédric Le Goater, Philippe Mathieu-Daudé)
 * memory-device refactoring (David Hildenbrand)
 * -smp: deprecate incorrect CPUs topology (Igor Mammedov)
 * -numa parsing cleanups (Markus Armbruster)
 * Fix hostmem-file memory leak (Zhang Yi)
 * Typo fix (Li Qiang)
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJb0cXCAAoJECgHk2+YTcWm9zoP/ioCxlqmjBYTJ9mrH0Ws8Cu3
 oeC/GefLgVmc9CZbalt7JXa/eWsALHzwKJkEAmokayORFKewLmKWnlSd0YIjL5+e
 jdstSQetNtjHn8wwtL2tx8stA7PS678p5vjQcgx2MP0Ia+drsqBKSm2OPYqF0+Hm
 LmmfGCoV4ijzof7NQXL/IPlyxt/FdphiUKZjaWqbiG4mFmZwRUfREcFcgAyz16tr
 m5M3bUzVaGvxVTa0gxsxwnVUpcQmjuT/x5BlhrHJs38LfEbafCDV0HDHYZurJ7Wv
 vaQMLUSpHHl+qThihEOxDsWXISNxLmjniYSa3Aq9RXjas2JbL90QZa3z/AQ9UNXc
 j3+/nkvNbFL/TkCPalOC5KdsN+6auLqmOcvdmDZSMumezAL52c+ysO5jt4lNYH+h
 FaxDptVrVOSrcpVNsb1vgSZHxTLxDz0VkDG4/zZx+I0f8IZXmuRdHsdGjGdZDkjp
 G8PEPW9QBUUHxDagc4M7wrFFrUvRkD8Aa8Z0xNSiYsU1Hb7h1Ke3pD9oFrLwSNKR
 g++hAY3kHSoHKnw4fAcu7Np+xdohhUQd4FzllcfDZwFfIsN/8jAxGc3BCodqbyoL
 aPBS3sxYkC3kWAHLpOXnD3luBn/LR8bfWdkqU0lD0cP4+msZQIcFcfhpcxY7nGg7
 GPVm2iywNQncewpb7yiN
 =5LPN
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging

Machine queue, 2018-10-25

* sysbus init/realize cleanups
  (Cédric Le Goater, Philippe Mathieu-Daudé)
* memory-device refactoring (David Hildenbrand)
* -smp: deprecate incorrect CPUs topology (Igor Mammedov)
* -numa parsing cleanups (Markus Armbruster)
* Fix hostmem-file memory leak (Zhang Yi)
* Typo fix (Li Qiang)

# gpg: Signature made Thu 25 Oct 2018 14:31:46 BST
# gpg:                using RSA key 2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/machine-next-pull-request: (43 commits)
  net: xgmac: convert SysBus init method to a realize method
  net: stellaris_enet: add a reset method
  net: stellaris_enet: convert SysBus init method to a realize method
  net: smc91c111: convert SysBus init method to a realize method
  net: opencores_eth: convert SysBus init method to a realize method
  net: mipsnet: convert SysBus init method to a realize method
  net: milkymist_minimac2: convert SysBus init method to a realize method
  net: lance: convert SysBus init method to a realize method
  net: lan9118: convert SysBus init method to a realize method
  net: etraxfs_eth: add a reset method
  net: etraxfs_eth: convert SysBus init method to a realize method
  memory-device: trace when pre_plugging/plugging/unplugging
  memory-device: complete factoring out unplug handling
  memory-device: complete factoring out plug handling
  memory-device: complete factoring out pre_plug handling
  memory-device: add device class function set_addr()
  memory-device: drop get_region_size()
  memory-device: factor out get_memory_region() from pc-dimm
  memory-device: add and use memory_device_get_region_size()
  memory-device: document MemoryDeviceClass
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-25 20:17:12 +01:00
Peter Maydell
808ebd66e4 First RISC-V Patch Set for the 3.1 Soft Freeze
This pull request contains a handful of patches that have been floating
 around various trees for a while but haven't made it upstream.  These
 patches all appear quite safe.  They're all somewhat independent from
 each other:
 
 * One refactors our IRQ management function to allow multiple interrupts
   to be raised an once.  This patch has no functional difference.
 * Cleaning up the op_helper/cpu_helper split.  This patch has no
   functional difference.
 * Updates to various constants to keep them in sync with the latest ISA
   specification and to remove some non-standard bits that snuck in.
 * A fix for a memory leak in the PLIC driver.
 * A fix to our device tree handling to avoid provinging a NULL string.
 
 I've given this my standard test: building the port, booting a Fedora
 root filesytem on the latest Linux tag, and then shutting down that
 image.  Essentially I'm just following the QEMU RISC-V wiki page's
 instructions.  Everything looks fine here.
 
 We have a lot more outstanding patches so I'll definately be submitting
 another PR for the soft freeze.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEAM520YNJYN/OiG3470yhUCzLq0EFAlvHmPATHHBhbG1lckBk
 YWJiZWx0LmNvbQAKCRDvTKFQLMurQforD/47/fuqbXlH2YZw5kNIuc/s0ULLOQFy
 yqiBig350IzO5fHZuiPeWdLJjlB4HXgif5O7yFuePTppG+3dl8IOf+hreMopia7K
 HaOG368vS1vQBDRhdw9OSDqeHipb9PF3zLoj0WWzngxrazg5WTyqX24k7Z/hCtco
 dP1dY8rCCgWAgyNE3yJki1Y/+KnubX0L3kmpoFQYp0otXmMG/IA+5KRKal4Jml03
 Z1puymvQNYyk+vI9gRPyjGQfbLeDn2jKghY0COad1u3okbfef9irDilmwCoFxhAA
 qW6ThXKsyIbYF/uEhqjfcvh6SSIu/q3OtLKFmTGwzWI+Df6eumcdLDW07OLKUpY1
 Xj7/6LqmeGfKMbe6b6JUfGwdf/4EpQ0byhGWBOjhj7CRyhtOryHrhBs15I3Fc57I
 QlBKrQXmETOiW++CC+h2BqLwdnJ8nlelzSLb96FzFGrYcVRlnAlof+n+1sMQPWNy
 quVyIWe4dZteJjJuTC1fnju4+LTH6sQCmhrvz10Jk1Hed1BYneww4D/bWc/Gzzgx
 FiIQud+7WvUYilwhGmzWOcHxPa2NYJvmJErW8asLXOvERd33cfbcyxjj4GCVpe/F
 vfZiubP+Pm95qXN31ahXB4SziFEw3I6IPLvCndFcLQSV2GvvF639xgcQEZ6m4xiV
 LahYSgwjWSkPwQ==
 =+IgM
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf0' into staging

First RISC-V Patch Set for the 3.1 Soft Freeze

This pull request contains a handful of patches that have been floating
around various trees for a while but haven't made it upstream.  These
patches all appear quite safe.  They're all somewhat independent from
each other:

* One refactors our IRQ management function to allow multiple interrupts
  to be raised an once.  This patch has no functional difference.
* Cleaning up the op_helper/cpu_helper split.  This patch has no
  functional difference.
* Updates to various constants to keep them in sync with the latest ISA
  specification and to remove some non-standard bits that snuck in.
* A fix for a memory leak in the PLIC driver.
* A fix to our device tree handling to avoid provinging a NULL string.

I've given this my standard test: building the port, booting a Fedora
root filesytem on the latest Linux tag, and then shutting down that
image.  Essentially I'm just following the QEMU RISC-V wiki page's
instructions.  Everything looks fine here.

We have a lot more outstanding patches so I'll definately be submitting
another PR for the soft freeze.

# gpg: Signature made Wed 17 Oct 2018 21:17:52 BST
# gpg:                using RSA key EF4CA1502CCBAB41
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>"
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/riscv/tags/riscv-for-master-3.1-sf0:
  RISC-V: Don't add NULL bootargs to device-tree
  RISC-V: Add missing free for plic_hart_config
  RISC-V: Update CSR and interrupt definitions
  RISC-V: Move non-ops from op_helper to cpu_helper
  RISC-V: Allow setting and clearing multiple irqs

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-25 17:41:03 +01:00
Peter Maydell
a4d710251f Improve performance of XTS cipher mode impl
The XTS cipher mode performance is approximately doubled and test
 coverage is improved.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJb0LRUAAoJEL6G67QVEE/fW0kQAKztZpe9TxQMIzQNlBtYJiUF
 51Xit4GVj3jZ5An1HcxhfKxv3hbsKOdDifBw1I+F5c7Tfmid6M/8f9M+fZ0FmGiN
 VsnkVNcckMbMck03C0llxigz24n3vxd8LvEQBR3ZA1sGAnWTSJNHfEmKZwh+5mX4
 hT2WoFC2QGcwOyWUH5W9NtASbVgzr3/KWuCaluK/okmLHA+ENov3FetMWYPad848
 FCjAvMLbC+S/AlkXwKTkn3L4+yow95yliyZHZXDiDS2QRP2u6fv39Q+0fYOayns1
 cTgmggNNsRErsYMAGveX5+GoFfLtUdYDH9h6e4U77mxonZz9IL8iP8sFVZEUc3Md
 syS3EPDQor+KBJF/opg0gR9IfY5cMoYUrW0huujX2uyOqQTl4yb0SAxzhPEP/gC7
 BOW757WkRXMsNDZNdYAtHi+kp0PPA+zGl9QFTMFSQtRgnPHyO0gkLFgXFQartPcg
 b6wpe+g+IwVdOzXjeYCJeP5WPD99pcxPsOcmHRfqopJq2fihm71czCFOg0uYjxZn
 LwhLrAzge6/MrZFBHsCwpkkItJov0hKjUl5QJ0S4vEK4fRPawaBkcvR9QuTCo9Pb
 xXdedxTKQYaBaXimV6ZsK4OpSZ/QR8FmwVeM33RUWzAz+SjtegzuvkXAA1Ic5XgI
 nxnjod33d+jxrzPDrVMl
 =K2kp
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/berrange/tags/qcrypto-next-pull-request' into staging

Improve performance of XTS cipher mode impl

The XTS cipher mode performance is approximately doubled and test
coverage is improved.

# gpg: Signature made Wed 24 Oct 2018 19:05:08 BST
# gpg:                using RSA key BE86EBB415104FDF
# gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>"
# gpg:                 aka "Daniel P. Berrange <berrange@redhat.com>"
# Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E  8E3F BE86 EBB4 1510 4FDF

* remotes/berrange/tags/qcrypto-next-pull-request:
  crypto: add testing for unaligned buffers with XTS cipher mode
  crypto: refactor XTS cipher mode test suite
  crypto: annotate xts_tweak_encdec as inlineable
  crypto: convert xts_mult_x to use xts_uint128 type
  crypto: convert xts_tweak_encdec to use xts_uint128 type
  crypto: introduce a xts_uint128 data type
  crypto: remove code duplication in tweak encrypt/decrypt
  crypto: expand algorithm coverage for cipher benchmark

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-24 22:08:42 +01:00
Daniel P. Berrangé
1e0fa32c6c crypto: add testing for unaligned buffers with XTS cipher mode
Validate that the XTS cipher mode will correctly operate with plain
text, cipher text and IV buffers that are not 64-bit aligned.

Reviewed-by: Alberto Garcia <berto@igalia.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24 19:03:37 +01:00
Daniel P. Berrangé
a61f682fde crypto: refactor XTS cipher mode test suite
The current XTS test overloads two different tests in a single function
making the code a little hard to follow. Split it into distinct test
cases.

Reviewed-by: Alberto Garcia <berto@igalia.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24 19:03:37 +01:00
Daniel P. Berrangé
aa895bd439 crypto: annotate xts_tweak_encdec as inlineable
Encouraging the compiler to inline xts_tweak_encdec increases the
performance for xts-aes-128 when built with gcrypt:

  Encrypt: 545 MB/s -> 580 MB/s
  Decrypt: 568 MB/s -> 602 MB/s

Reviewed-by: Alberto Garcia <berto@igalia.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24 19:03:37 +01:00
Daniel P. Berrangé
7dac0dd674 crypto: convert xts_mult_x to use xts_uint128 type
Using 64-bit arithmetic increases the performance for xts-aes-128
when built with gcrypt:

  Encrypt: 355 MB/s -> 545 MB/s
  Decrypt: 362 MB/s -> 568 MB/s

Reviewed-by: Alberto Garcia <berto@igalia.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24 19:03:37 +01:00
Daniel P. Berrangé
db217c69f0 crypto: convert xts_tweak_encdec to use xts_uint128 type
Using 64-bit arithmetic increases the performance for xts-aes-128
when built with gcrypt:

  Encrypt: 272 MB/s -> 355 MB/s
  Decrypt: 275 MB/s -> 362 MB/s

Reviewed-by: Alberto Garcia <berto@igalia.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24 19:03:37 +01:00
Daniel P. Berrangé
cc36930e40 crypto: introduce a xts_uint128 data type
The new type is designed to allow use of 64-bit arithmetic instead
of operating 1-byte at a time. The following patches will use this to
improve performance.

Reviewed-by: Alberto Garcia <berto@igalia.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24 19:03:37 +01:00
Daniel P. Berrangé
299ec87838 crypto: remove code duplication in tweak encrypt/decrypt
The tweak encrypt/decrypt functions are identical except for the
comments, so can be merged. Profiling data shows that the compiler is
in fact already merging the two merges in the object files.

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Alberto Garcia <berto@igalia.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24 19:03:37 +01:00
Daniel P. Berrangé
a9e08155bd crypto: expand algorithm coverage for cipher benchmark
Add testing coverage for AES with XTS, ECB and CTR modes

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Alberto Garcia <berto@igalia.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24 19:03:37 +01:00
Peter Maydell
c96292036a MIPS queue for October 2018 - part 2 - v2
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJb0HIuAAoJENSXKoln91plGcUH/3Lje5KF8kkShQ5dIrH9e8Xz
 bvK6lXOLNnndEyrWqJNLaJs7eJKEV2N+E2sBmdIjKnWXVHW6gOW3QBMuVGPTT4rg
 C6cntrh2HpnxibgJqrR+3RmjQHAI1Ktixhker9LWimF3ZZhcy4H6mFHwW9z7eBK4
 +n/pbnk8fq4FlGHJ2teHhctVIma6slmd8lkMa9vdwVQwpAyzpP82XjrsoTeeYhmG
 uuTvX3TFnXKGa9mYGxybpwKd4i+397l9fTQ4egx1KlZMR8OHuQItCBDOFdiQpHOg
 yljCeG3jHEhNzVf+xW7JU692Lz097otWDbzWDJibYGJkdkhKfyHJ9PvCYaPiK6M=
 =Sg8J
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-oct-2018-part-2-v2' into staging

MIPS queue for October 2018 - part 2 - v2

# gpg: Signature made Wed 24 Oct 2018 14:22:54 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-oct-2018-part-2-v2: (33 commits)
  target/mips: Fix decoding of ALIGN and DALIGN instructions
  target/mips: Fix the title of translate.c
  linux-user/mips: Recognize the R5900 CPU model
  target/mips: Define the R5900 CPU
  tests/tcg/mips: Add tests for R5900 DIVU1
  tests/tcg/mips: Add tests for R5900 DIV1
  tests/tcg/mips: Add tests for R5900 MTLO1 and MTHI1
  tests/tcg/mips: Add tests for R5900 MFLO1 and MFHI1
  tests/tcg/mips: Add tests for R5900 three-operand MULTU1
  tests/tcg/mips: Add tests for R5900 three-operand MULT1
  tests/tcg/mips: Add tests for R5900 three-operand MULTU
  tests/tcg/mips: Add tests for R5900 three-operand MULT
  target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only
  target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV
  target/mips: Support R5900 DIV1 and DIVU1 instructions
  target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions
  target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions
  target/mips: Support R5900 three-operand MULT and MULTU instructions
  target/mips: Add a placeholder for R5900 MMI3 instruction subclass
  target/mips: Add a placeholder for R5900 MMI2 instruction subclass
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-24 16:31:40 +01:00