MIPS queue for October 2018 - part 3
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJb0iQKAAoJENSXKoln91plUngH/icGvr5sa6JbT/4bDP20Wv7y gwJ8Ax6kKDU4Z/JbBt+2diXVRrPXCF6xt/dvcaWCnxKyjIZN0i2azHv75jtMEA5t +khdqqREzTZ8RiEI+u0r+OkSNJ3837O+ahQFdRxjqSDIScC8mcwW8h1md9ThjzbQ yBhRvNo8QkXGGx9MCWZ7kUGkPnJDQnL0jGiFj0xhtyDSGXfnnOpUgpQKRWu5cQzl Q7JKFPQgt676kd6UyG7f+xYw/a6uERmMBWp30CfN6bP4bPcdFHdUlgIM60VRAfhA qYA4led5sWcuqmA96PoZIOc+05/8Q8NkgP+nYbXeMkW8/9QOCPa/30p7QayOpZA= =F4up -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-oct-2018-part-3' into staging MIPS queue for October 2018 - part 3 # gpg: Signature made Thu 25 Oct 2018 21:14:02 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-oct-2018-part-3: target/mips: Add disassembler support for nanoMIPS target/mips: Implement emulation of nanoMIPS EVA instructions target/mips: Add nanoMIPS CRC32 instruction pool Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
179f9ac887
@ -202,6 +202,8 @@ F: include/hw/intc/mips_gic.h
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F: include/hw/timer/mips_gictimer.h
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F: tests/tcg/mips/
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F: disas/mips.c
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F: disas/nanomips.h
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F: disas/nanomips.cpp
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Moxie
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M: Anthony Green <green@moxielogic.com>
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3
configure
vendored
3
configure
vendored
@ -7264,6 +7264,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
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;;
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mips*)
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disas_config "MIPS"
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if test -n "${cxx}"; then
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disas_config "NANOMIPS"
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fi
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;;
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moxie*)
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disas_config "MOXIE"
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@ -14,6 +14,7 @@ common-obj-$(CONFIG_I386_DIS) += i386.o
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common-obj-$(CONFIG_M68K_DIS) += m68k.o
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common-obj-$(CONFIG_MICROBLAZE_DIS) += microblaze.o
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common-obj-$(CONFIG_MIPS_DIS) += mips.o
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common-obj-$(CONFIG_NANOMIPS_DIS) += nanomips.o
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common-obj-$(CONFIG_NIOS2_DIS) += nios2.o
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common-obj-$(CONFIG_MOXIE_DIS) += moxie.o
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common-obj-$(CONFIG_PPC_DIS) += ppc.o
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22242
disas/nanomips.cpp
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22242
disas/nanomips.cpp
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File diff suppressed because it is too large
Load Diff
1099
disas/nanomips.h
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1099
disas/nanomips.h
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File diff suppressed because it is too large
Load Diff
@ -387,6 +387,7 @@ typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
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int print_insn_tci(bfd_vma, disassemble_info*);
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int print_insn_big_mips (bfd_vma, disassemble_info*);
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int print_insn_little_mips (bfd_vma, disassemble_info*);
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int print_insn_nanomips (bfd_vma, disassemble_info*);
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int print_insn_i386 (bfd_vma, disassemble_info*);
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int print_insn_m68k (bfd_vma, disassemble_info*);
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int print_insn_z8001 (bfd_vma, disassemble_info*);
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@ -75,6 +75,7 @@
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#pragma GCC poison CONFIG_M68K_DIS
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#pragma GCC poison CONFIG_MICROBLAZE_DIS
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#pragma GCC poison CONFIG_MIPS_DIS
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#pragma GCC poison CONFIG_NANOMIPS_DIS
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#pragma GCC poison CONFIG_MOXIE_DIS
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#pragma GCC poison CONFIG_NIOS2_DIS
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#pragma GCC poison CONFIG_PPC_DIS
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@ -113,11 +113,20 @@ static void mips_cpu_reset(CPUState *s)
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}
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static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) {
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MIPSCPU *cpu = MIPS_CPU(s);
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CPUMIPSState *env = &cpu->env;
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if (!(env->insn_flags & ISA_NANOMIPS32)) {
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#ifdef TARGET_WORDS_BIGENDIAN
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info->print_insn = print_insn_big_mips;
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info->print_insn = print_insn_big_mips;
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#else
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info->print_insn = print_insn_little_mips;
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info->print_insn = print_insn_little_mips;
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#endif
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} else {
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#if defined(CONFIG_NANOMIPS_DIS)
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info->print_insn = print_insn_nanomips;
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#endif
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}
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}
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static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
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@ -2989,6 +2989,35 @@ static inline void check_nms(DisasContext *ctx)
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}
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}
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/*
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* This code generates a "reserved instruction" exception if the
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* Config5 NMS bit is set, and Config1 DL, Config1 IL, Config2 SL,
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* Config2 TL, and Config5 L2C are unset.
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*/
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static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
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{
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if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS)) &&
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!(ctx->CP0_Config1 & (1 << CP0C1_DL)) &&
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!(ctx->CP0_Config1 & (1 << CP0C1_IL)) &&
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!(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&
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!(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&
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!(ctx->CP0_Config5 & (1 << CP0C5_L2C)))
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{
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generate_exception_end(ctx, EXCP_RI);
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}
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}
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/*
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* This code generates a "reserved instruction" exception if the
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* Config5 EVA bit is NOT set.
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*/
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static inline void check_eva(DisasContext *ctx)
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{
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if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) {
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generate_exception_end(ctx, EXCP_RI);
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}
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}
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/* Define small wrappers for gen_load_fpr* so that we have a uniform
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calling interface for 32 and 64-bit FPRs. No sense in changing
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@ -17475,6 +17504,16 @@ enum {
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NM_SOV = 0x7a,
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};
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/* CRC32 instruction pool */
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enum {
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NM_CRC32B = 0x00,
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NM_CRC32H = 0x01,
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NM_CRC32W = 0x02,
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NM_CRC32CB = 0x04,
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NM_CRC32CH = 0x05,
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NM_CRC32CW = 0x06,
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};
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/* POOL32A5 instruction pool */
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enum {
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NM_CMP_EQ_PH = 0x00,
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@ -21208,6 +21247,105 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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break;
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}
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break;
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case NM_P_LS_E0:
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switch (extract32(ctx->opcode, 11, 4)) {
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case NM_LBE:
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check_eva(ctx);
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check_cp0_enabled(ctx);
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gen_ld(ctx, OPC_LBE, rt, rs, s);
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break;
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case NM_SBE:
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check_eva(ctx);
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check_cp0_enabled(ctx);
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gen_st(ctx, OPC_SBE, rt, rs, s);
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break;
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case NM_LBUE:
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check_eva(ctx);
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check_cp0_enabled(ctx);
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gen_ld(ctx, OPC_LBUE, rt, rs, s);
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break;
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case NM_P_PREFE:
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if (rt == 31) {
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/* case NM_SYNCIE */
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check_eva(ctx);
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check_cp0_enabled(ctx);
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/* Break the TB to be able to sync copied instructions
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immediately */
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ctx->base.is_jmp = DISAS_STOP;
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} else {
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/* case NM_PREFE */
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check_eva(ctx);
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check_cp0_enabled(ctx);
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/* Treat as NOP. */
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}
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break;
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case NM_LHE:
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check_eva(ctx);
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check_cp0_enabled(ctx);
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gen_ld(ctx, OPC_LHE, rt, rs, s);
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break;
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case NM_SHE:
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check_eva(ctx);
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check_cp0_enabled(ctx);
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gen_st(ctx, OPC_SHE, rt, rs, s);
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break;
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case NM_LHUE:
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check_eva(ctx);
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check_cp0_enabled(ctx);
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gen_ld(ctx, OPC_LHUE, rt, rs, s);
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break;
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case NM_CACHEE:
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check_nms_dl_il_sl_tl_l2c(ctx);
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gen_cache_operation(ctx, rt, rs, s);
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break;
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case NM_LWE:
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check_eva(ctx);
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check_cp0_enabled(ctx);
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gen_ld(ctx, OPC_LWE, rt, rs, s);
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break;
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case NM_SWE:
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check_eva(ctx);
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check_cp0_enabled(ctx);
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gen_st(ctx, OPC_SWE, rt, rs, s);
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break;
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case NM_P_LLE:
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switch (extract32(ctx->opcode, 2, 2)) {
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case NM_LLE:
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check_xnp(ctx);
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check_eva(ctx);
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check_cp0_enabled(ctx);
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gen_ld(ctx, OPC_LLE, rt, rs, s);
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break;
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case NM_LLWPE:
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check_xnp(ctx);
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check_eva(ctx);
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check_cp0_enabled(ctx);
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gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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case NM_P_SCE:
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switch (extract32(ctx->opcode, 2, 2)) {
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case NM_SCE:
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check_xnp(ctx);
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check_eva(ctx);
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check_cp0_enabled(ctx);
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gen_st_cond(ctx, OPC_SCE, rt, rs, s);
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break;
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case NM_SCWPE:
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check_xnp(ctx);
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check_eva(ctx);
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check_cp0_enabled(ctx);
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gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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}
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break;
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case NM_P_LS_WM:
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case NM_P_LS_UAWM:
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check_nms(ctx);
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