Commit Graph

647 Commits

Author SHA1 Message Date
Richard Henderson
e77f083292 target-arm: Fix sbc_CC carry
While T0+~T1+CF = T0-T1+CF-1 is true for the low 32-bits,
it does not produce the correct carry-out to bit 33.  Do
exactly what the manual says.

Using the ~T1 makes the add and subtract code paths nearly
identical, so have sbc_CC use adc_CC.

Cc: Peter Maydell <peter.maydell@linaro.org>
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-02-25 14:32:36 -06:00
Peter Crosthwaite
8c3ac601bd arm/translate.c: Fix adc_CC/sbc_CC implementation
commits 49b4c31efc and
2de68a4900 reworked the implementation of adc_CC
and sub_CC. The new implementations (on the TCG_TARGET_HAS_add2_i32 code path)
are incorrect. The new logic is:

CF:NF = 0:A +/- 0:CF
CF:NF = CF:A +/- 0:B

The lower 32 bits of the intermediate result stored in NF needs to be passes
into the second addition in place of A (s/CF:A/CF:NF):

CF:NF = 0:A +/- 0:CF
CF:NF = CF:NF +/- 0:B

This patch fixes the issue.

Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-02-25 14:32:36 -06:00
Richard Henderson
2de68a4900 target-arm: Implement sbc_cc inline
Use sub2 if available, otherwise use 64-bit arithmetic.

Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23 17:25:29 +00:00
Richard Henderson
49b4c31efc target-arm: Implement adc_cc inline
Use add2 if available, otherwise use 64-bit arithmetic.

Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23 17:25:29 +00:00
Richard Henderson
e3482cb806 target-arm: Use add2 in gen_add_CC
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23 17:25:29 +00:00
Richard Henderson
c9f10124a2 target-arm: Use mul[us]2 and add2 in umlal et al
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23 17:25:29 +00:00
Richard Henderson
831d7fe800 target-arm: Use mul[us]2 in gen_mul[us]_i64_i32
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23 17:25:29 +00:00
Andreas Färber
c05efcb18e cpu: Add CPUArchState pointer to CPUState
The target-specific ENV_GET_CPU() macros have allowed us to navigate
from CPUArchState to CPUState. The reverse direction was not supported.
Avoid introducing CPU_GET_ENV() macros by initializing an untyped
pointer that is initialized in derived instance_init functions.

The field may not be called "env" due to it being poisoned.

Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-02-16 14:51:00 +01:00
Andreas Färber
79614b781d target-arm: Move TCG initialization to ARMCPU initfn
Ensures that a QOM-created ARMCPU is usable.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-02-16 14:50:58 +01:00
Andreas Färber
149692667f target-arm: Update ARMCPU to QOM realizefn
Turn arm_cpu_realize() into a QOM realize function, no longer called
via cpu.h prototype. To maintain the semantics of cpu_init(), set
realized = true explicitly in cpu_arm_init().

Move GDB coprocessor registration, CPU reset and vCPU initialization
into the realizefn.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-02-16 14:50:56 +01:00
Andreas Färber
51492fd1a9 target-arm: Rename CPU types
In the initial conversion of CPU models to QOM types, model names were
mapped 1:1 to type names. As a side effect this gained us a type "any",
which is now a device.

To avoid "-device any" silliness and to pave the way for compiling
multiple targets into one executable, adopt a <name>-<arch>-cpu scheme.
This leads to names like arm926-arm-cpu but is easiest to handle.

No functional changes for -cpu arguments or -cpu ? output.

Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-01-30 16:03:57 +00:00
Peter Maydell
e4c1cfa5cb target-arm: Fix TCG temp leaks for WI and UNDEF VFP sysreg writes
Fix a leak of a TCG temporary in code paths for VFP system register
writes for cases which UNDEF or are write-ignored.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-01-30 16:01:58 +00:00
Andreas Färber
245fb54db5 target-arm: Catch attempt to instantiate abstract type in cpu_init()
This fixes -cpu arm-cpu asserting.

Cc: qemu-stable@nongnu.org
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-27 23:33:34 +01:00
Andreas Färber
5900d6b2d5 target-arm: Detect attempt to instantiate non-CPU type in cpu_init()
Consolidate model checking into a new arm_cpu_class_by_name().

If the name matches an existing type, also check whether that type is
actually (a sub-type of) TYPE_ARM_CPU.

This fixes, e.g., -cpu tmp105 asserting.

Cc: qemu-stable <qemu-stable@nongnu.org>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-27 14:52:04 +01:00
Andreas Färber
55e5c28502 cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using a
negative offset. Therefore the field is placed last in CPUState.

Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.

Move common parts of mips cpu_state_reset() to mips_cpu_reset().

Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
[AF: Rebased onto ppc CPU subclasses and openpic changes]
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-15 04:09:13 +01:00
Alex_Rozenman@mentor.com
314e2296dc target-arm: Fix SWI (SVC) instruction in M profile.
When do_interrupt_v7m is called with EXCP_SWI, the PC already
points to the next instruction. Don't modify it here.

Signed-off-by: Alex Rozenman <Alex_Rozenman@mentor.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-01-11 15:21:22 +00:00
Eduardo Habkost
918fd0839e target-arm: use type_register() instead of type_register_static()
The type_register_static() interface is documented as:

  type_register_static:
  @info: The #TypeInfo of the new type.

  @info and all of the strings it points to should exist for the life
  time that the type is registered.

But cpu_register() uses a stack variable for the 'info' argument, so it
has to use type_register() instead of type_register_static().

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-01-11 15:21:22 +00:00
Andreas Färber
501a7ce727 Merge branch 'master' of git://git.qemu.org/qemu into qom-cpu
Adapt header include paths.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-12-23 00:40:49 +01:00
Andreas Färber
92a3136174 cpu: Introduce CPUListState struct
This generalizes {ARM,M68k,Alpha}CPUListState to avoid declaring it for
each target. Place it in cpu-common.h to avoid circular dependencies.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
2012-12-19 14:08:56 +01:00
Paolo Bonzini
6b4c305cbd fpu: move public header file to include/fpu
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19 08:32:46 +01:00
Paolo Bonzini
9c17d615a6 softmmu: move include files to include/sysemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19 08:32:45 +01:00
Paolo Bonzini
1de7afc984 misc: move include files to include/qemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19 08:32:39 +01:00
Paolo Bonzini
14cccb6185 qom: move include files to include/qom/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19 08:31:32 +01:00
Paolo Bonzini
022c62cbbc exec: move include files to include/exec/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19 08:31:31 +01:00
Paolo Bonzini
76cad71136 build: kill libdis, move disassemblers to disas/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19 08:29:06 +01:00
Blue Swirl
a8a826a3c3 exec: refactor cpu_restore_state
Refactor common code around calls to cpu_restore_state().

tb_find_pc() has now no external users, make it static.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-16 08:35:24 +00:00
Evgeny Voevodin
ab1103def4 TCG: Use gen_opc_instr_start from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08 14:24:43 +00:00
Evgeny Voevodin
c9c99c22d5 TCG: Use gen_opc_icount from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08 14:24:42 +00:00
Evgeny Voevodin
25983cad31 TCG: Use gen_opc_pc from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08 14:24:42 +00:00
Evgeny Voevodin
92414b31e7 TCG: Use gen_opc_buf from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-11-17 13:53:36 +00:00
Evgeny Voevodin
efd7f48600 TCG: Use gen_opc_ptr from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-11-17 13:53:27 +00:00
Blue Swirl
f4359b9ffe disas: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Acked-by: Richard Henderson <rth@twiddle.net>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
2012-11-10 13:49:20 +00:00
Andreas Färber
3993c6bddf cpus: Pass CPUState to [qemu_]cpu_has_work()
For target-mips also change the return type to bool.

Make include paths for cpu-qom.h consistent for alpha and unicore32.

Signed-off-by: Andreas Färber <afaerber@suse.de>
[AF: Updated new target-openrisc function accordingly]
Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
2012-10-31 04:11:37 +01:00
Aurelien Jarno
4b3d4829ab target-arm: rename helper flags
Rename helper flags to the new ones. This is purely a mechanical change,
it's possible to use better flags by looking at the helpers.

Cc: Paul Brook <paul@codesourcery.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-28 14:54:23 +01:00
Peter Maydell
8b279a60dc target-arm: Remove out of date FIXME regarding saturating arithmetic
Remove an out of date FIXME regarding the saturating arithmetic helpers:
we now do pass a pointer to CPUARMState to these helpers, and since
the AREG0 changes went in there is no difference between helper.c
and op_helper.c and therefore no point in moving the functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-24 13:33:29 +01:00
Peter Maydell
36c91fd115 target-arm: Implement abs_i32 inline rather than as a helper
Implement abs_i32 inline (with movcond) rather than using a helper
function.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-24 13:33:29 +01:00
Peter Maydell
ee6fa5593e target-arm: Use TCG operation for Neon 64 bit negation
Use the TCG operation to do Neon 64 bit negations rather than calling
a helper routine for it.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-24 13:33:29 +01:00
Peter Maydell
f296c0d172 arm-semi.c: Handle get/put_user() failure accessing arguments
Rework the handling of arguments to ARM semihosting calls so that we
handle a possible failure return from get_user_ual() or put_user_ual().
(This incidentally silences a lot of warnings from clang about
"expression result unused").

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-24 13:33:29 +01:00
Avi Kivity
a8170e5e97 Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific).  Replace it with a finger-friendly,
standards conformant hwaddr.

Outstanding patchsets can be fixed up with the command

  git rebase -i --exec 'find -name "*.[ch]"
                        | xargs s/target_phys_addr_t/hwaddr/g' origin

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-10-23 08:58:25 -05:00
Peter Maydell
02c7ac0c0f target-arm/neon_helper: Remove obsolete FIXME comment
Commit 33ebc29 fixed the bugs in the implementation of VQRSHL,
but forgot to remove the FIXME comment...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-10-19 10:32:24 +02:00
Peter Crosthwaite
b6348f29d0 target-arm/translate: Fix RRX operands
Instructions that both use the RRX second operand and update CS were
incorrect, as the Carry flag was updated too early. An example of such an
instruction would be:

ands r12,r13,RRX

Ands, because of the "s" flag will update the carry flag. But the RRX second
operand rotates through the C flag which should happen before the update.
Fixed the ordering of the two, the old carry is read by "r13,RRX" before being
updated.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reported-by: Vinesh Peringat <vineshp@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 19:56:46 +02:00
Peter Maydell
1273d9ca09 target-arm: Drop unused DECODE_CPREG_CRN macro
This macro snuck through code review despite being unused; drop it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05 15:04:45 +01:00
Aurelien Jarno
d593c48ef9 target-arm: use deposit instead of hardcoded version
Use the deposit op instead of and hardcoded bit field insertion. It
allows the host to emit the corresponding instruction if available.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05 15:04:45 +01:00
Aurelien Jarno
00e3ab2db0 target-arm: mark a few integer helpers const and pure
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05 15:04:45 +01:00
Aurelien Jarno
365af80e47 target-arm: convert sar, shl and shr helpers to TCG
Now that the movcond TCG op is available, it's possible to replace
shl and shr helpers by TCG code. The code generated by TCG is slightly
longer than the code generated by GCC for the helper but is still worth
it as this avoid all the consequences of using an helper: globals saved
back to memory, no possible optimization, call overhead, etc.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05 15:04:44 +01:00
Aurelien Jarno
72485ec4f6 target-arm: convert add_cc and sub_cc helpers to TCG
Now that the setcond TCG op is available, it's possible to replace
add_cc and sub_cc helpers by TCG code. The code generated by TCG is
actually very close to the one generated by GCC for the helper, and
this avoid all the consequences of using an helper: globals saved back
to memory, no possible optimization, call overhead, etc.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05 15:04:44 +01:00
Aurelien Jarno
66c374de8a target-arm: use globals for CC flags
Use globals for CC flags instead of loading/storing them each they are
accessed. This allows some optimizations to be performed by the TCG
optimization passes.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05 15:04:44 +01:00
Peter Maydell
f2617cfc23 target-arm: Reinstate display of VFP registers in cpu_dump_state
Reinstate the display of VFP registers in cpu_dump_state(), if
the CPU has them (this code had been #if 0'd out a for a long time).
We drop the attempt ot display the values as floating point, since
this makes assumptions about the host 'float' and 'double' formats
and is not done by eg the i386 cpu_dump_state().
This display is gated on the CPU_DUMP_FPU flag, as for x86.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05 15:04:44 +01:00
Richard Henderson
fdefe51c28 Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,
add CPU_LOG_TB_OP_OPT to the condition that gates it.

This is useful for comparing optimization dumps, when the
pre-optimization dump is merely noise.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-27 21:38:50 +02:00
Blue Swirl
d31dd73e48 target-arm: final conversion to AREG0 free mode
Convert code load functions and switch to AREG0 free mode.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2012-09-15 17:44:32 +00:00