Commit Graph

582 Commits

Author SHA1 Message Date
Peter Maydell
3cc0cd61f4 ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits
Make target_phys_addr_t 64 bits for ARM targets, and set
TARGET_PHYS_ADDR_SPACE_BITS to 40.  This should have no effect for ARM
boards where physical addresses really are 32 bits (except perhaps a
slight performance hit on 32 bit hosts for system emulation) but allows
us to implement the Large Physical Address Extensions for Cortex-A15,
which mean 40 bit physical addresses.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12 10:59:53 +00:00
Peter Maydell
ed336850e8 target-arm: Fix TCG temp handling in 64 bit cp writes
Fix errors in the TCG temp handling in the 64 bit coprocessor
write path: we were reusing a 32 bit temp after it had been
freed by store_reg(), and failing to free a 64 bit temp.

This bug has no visible effect at this point because there
aren't any non-NOP 64 bit registers yet; it needs to be fixed
as a prerequisite for the 64 bit registers in LPAE support.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12 10:59:53 +00:00
Peter Maydell
091fd17ce8 target-arm: Fix some copy-and-paste errors in cp register names
Fix a couple of cases where cp register names were copy-and-pasted.
These are harmless since we don't use the name for anything (except
debugging convenience) but could be confusing.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>
2012-07-12 10:58:36 +00:00
Peter Maydell
81a60ada7e target-arm: Fix typo that meant TTBR1 accesses went to TTBR0
Fix a copy-and-paste error in the register description for TTBR1
that meant it was a duplicate of TTBR0 rather than affecting the
correct bit of CPU state.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12 10:58:36 +00:00
Paul Brook
2bee510548 target-arm: Fix CP15 based WFI
The coprocessor register rework broke cp15 based WFI instructions.
We incorrectly fall through the normal register write case, which
incorrectly adds a forced block termination.  We've already done
a special version of this (DISAS_WFI), so return immediately.

Signed-off-by: Paul Brook <paul@codesourcery.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12 10:58:35 +00:00
Peter Maydell
b2d06f9607 target-arm: Remove ARM_CPUID_* macros
All the uses of ARM_CPUID() to vary behaviour have now been
removed, so we can delete the ARM_CPUID_* macros now.
The one exception is the TI915T/925T, because of its odd behaviour
where the MIDR value can be changed at runtime.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-06-20 12:13:28 +00:00
Peter Maydell
4a9a539ffb target-arm: Remove remaining old cp15 infrastructure
There are now no uses of the old cp15 infrastructure,
so it can be deleted.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:13:04 +00:00
Peter Maydell
30b05bba11 target-arm: Move block cache ops to new cp15 framework
Move the v6 optional block cache ops to the new cp15 framework.
This includes only providing them on the CPUs which implemented
them, rather than the previous blunderbuss approach of making
all MCRR instructions on all CPUs act as NOPs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:12:41 +00:00
Peter Maydell
b22af022b2 target-arm: Remove c0_cachetype CPUARMState field
Remove the no-longer-used CPUARMState c0_cachetype field.
Although this was a constant register we had it in our
migration state. Drop this (with resulting version bump)
because for ARM currently we prefer cleaner migration
code and have not stabilised migration format yet.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:11:49 +00:00
Peter Maydell
7884849cc5 target-arm: Convert final ID registers
Convert the final ID registers to the new cp15 scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:11:45 +00:00
Peter Maydell
81bdde9dcd target-arm: Convert MPIDR
Convert the MPIDR to the new cp15 register scheme.
This includes giving it its own feature bit rather
than doing a CPUID value check.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:10:54 +00:00
Peter Maydell
776d4e5c6c target-arm: Convert cp15 cache ID registers
Convert the cp15 cache ID registers to the new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:10:05 +00:00
Peter Maydell
8515a09294 target-arm: Convert cp15 crn=0 crm={1,2} feature registers
Convert the cp15 crn=0 crm={1,2} features registers to
the new cp reg framework.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:09:11 +00:00
Peter Maydell
2771db2741 target-arm: Convert cp15 crn=1 registers
Convert the cp15 crn=1 registers to the new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:08:22 +00:00
Peter Maydell
34f9052967 target-arm: Convert cp15 crn=9 registers
Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme.

Note that this change makes OMAPCP cores RAZ/WI the whole c9 space.  This is
a change from previous behaviour, but a return to the behaviour of commit
c3d2689d when OMAP1 support was first added -- subsequent commits have
clearly accidentally relegated the OMAPCP RAZ condition to only a subset of
the crn=9 space when adding support for other cores.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:08:16 +00:00
Peter Maydell
06d76f319f target-arm: Convert cp15 crn=6 registers
Convert the cp15 crn=6 registers to the new scheme.
Note that this includes some minor tidyup: drop an unnecessary
underdecoding of op2 on OMAPCP cores, and only implement the
pre-v6 c6,c0,0,1 IFAR on the 1026 and not on the other ARMv5
cores, which didn't have it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:08:11 +00:00
Peter Maydell
c480421426 target-arm: convert cp15 crn=7 registers
Convert the cp15 crn=7 registers to the new scheme.
Note that to do this we have to distinguish some registers
used on the ARM9 and ARM10 from some which are ARM1176
only. This is because the old code returned a value of 0
but always set the Z flag (by clearing env->ZF, since we
store the Z flag in CPUState inverted). This is inconsistent
with actual ARM CPU behaviour, which only sets flags for
reads to r15 and sets them based on the top bits of the result.
However it happened to work for the two common use cases for
cp15 crn=7 reads:
 * On ARM9 and ARM10 the cache clean-and-test operations are
typically done with a destination of r15 so that you can do
a "loop: mrc ... ; bne loop" to keep cleaning until the cache
is finally clean; always setting the Z flag means this loop
terminates immediately
 * on ARM1176 the Cache Dirty Status Register reads as zero
if the cache is dirty; returning 0 means this is correctly
implemented for QEMU

Since the new coprocessor register framework does the right
thing of always setting flags based on the returned result
for reads to r15, we need to split these up so that we can
return (1<<30) for the ARM9/ARM10 registers but 0 for the
ARM1176 one.

This allows us to remove the nasty hack which always sets Z.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:07:11 +00:00
Peter Maydell
4a50160666 target-arm: Convert cp15 VA-PA translation registers
Convert the cp15 VA-PA translation registers (a subset of
the crn=7 regs) to the new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:07:05 +00:00
Peter Maydell
d929823fa1 target-arm: Convert cp15 MMU TLB control
Convert cp15 MMU TLB control (crn=8) to new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:07:00 +00:00
Peter Maydell
1047b9d7bb target-arm: Convert cp15 crn=15 registers
Convert the cp15 crn=15 (implementation specific) registers
to the new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:06:09 +00:00
Peter Maydell
4fdd17dd35 target-arm: Convert cp15 crn=10 registers
We RAZ/WI the entire block of crn=10 registers. Note that this
actually covers not just the implementation-defined TLB
lockdown registers but also a number of v7 VMSA memory
attribute registers which we would need to implement to
support TEX remap. We retain the previous QEMU behaviour
in this conversion, though.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:06:05 +00:00
Peter Maydell
08de207bc5 target-arm: Convert cp15 crn=13 registers
Convert the cp15 crn=13 registers (FCSEIDR, CONTEXTIDR,
and the ARM946 Trace Process Identifier Register).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:06:01 +00:00
Peter Maydell
ecce5c3c90 target-arm: Convert cp15 crn=2 registers
Convert the cp15 crn=2 registers (MMU page table control,
MPU cache control) to the new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:05:56 +00:00
Peter Maydell
18032bec5c target-arm: Convert MMU fault status cp15 registers
Convert the MMU fault status and MPU access permission cp15
registers to the new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:05:50 +00:00
Peter Maydell
c983fe6cf1 target-arm: Convert cp15 c3 register
Convert the cp15 c3 register (MMU domain access control
or MPU write buffer control). NB that this is horribly
underdecoded for modern cores (should be crn=3,crm=0,
opc1=0,opc2=0) but this change preserves the existing
QEMU behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:05:44 +00:00
Peter Maydell
6cc7a3aee6 target-arm: Convert generic timer cp15 regs
Convert the (dummy) generic timer cp15 implementation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:05:40 +00:00
Peter Maydell
200ac0ef87 target-arm: Convert performance monitor registers
Convert the v7 performance monitor cp15 registers to
the new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:05:17 +00:00
Peter Maydell
4d31c59679 target-arm: Convert TLS registers
Convert TLS registers to the new cp15 framework

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:04:54 +00:00
Peter Maydell
7d57f40877 target-arm: Convert WFI/barriers special cases to cp_reginfo
Convert the various WFI and barrier instruction special cases to use
cp_reginfo infrastructure.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:04:32 +00:00
Peter Maydell
c326b9796f target-arm: Convert TEECR, TEEHBR to new scheme
Convert the THUMB2EE cp14 registers TEECR and TEEHBR to
use arm_cp_reginfo.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:04:08 +00:00
Peter Maydell
e9aa6c2148 target-arm: Convert debug registers to cp_reginfo
Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the
cp_reginfo scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:03:44 +00:00
Peter Maydell
2ceb98c007 target-arm: Add register_cp_regs_for_features()
Add new function register_cp_regs_for_features() as a place to
register coprocessor registers dependent on feature flags.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:02:54 +00:00
Peter Maydell
e8070a23a8 target-arm: Remove old cpu_arm_set_cp_io infrastructure
All the users of cpu_arm_set_cp_io have been converted, so we
can remove it and the infrastructure it used.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:02:01 +00:00
Peter Maydell
4b6a83fb0c target-arm: initial coprocessor register framework
Initial infrastructure for data-driven registration of
coprocessor register implementations.

We still fall back to the old-style switch statements pending
complete conversion of all existing registers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:01:02 +00:00
Peter Maydell
200bf596b9 target-arm: Fix 11MPCore cache type register value
Make the 11MPCore report a valid value in its cache type register
(the previous value appears to have been incorrectly copied from
the 1136/1176). In particular, do not report that we have an
aliasing VIPT cache, because this causes Linux to attempt to use
the v6 block cache ops which the 11MPCore doesn't actually have.
(This causes no problems currently because we over-broadly provide
those ops on all cores, but prevents us correctly narrowing the
block ops down to those cores which actually implement them.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20 12:00:58 +00:00
Paolo Bonzini
fbe37ef3e1 build: move other target-*/ objects to nested Makefile.objs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-07 09:21:11 +02:00
Paolo Bonzini
9cdc8df314 build: move libobj-y variable to nested Makefile.objs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-07 07:19:23 +02:00
Paolo Bonzini
5e8861a036 build: move obj-TARGET-y variables to nested Makefile.objs
Also drop duplicate occurrence of device-hotplug.o.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-07 07:17:36 +02:00
Andreas Färber
b7e516ce04 Kill off cpu_state_reset()
In commit 1bba0dc932 cpu_reset()
was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()
that would operate on QOM objects.

All callers have been updated except for one in target-mips, so drop all
implementations except for the one in target-mips and move the
declaration there until MIPSCPU reset can be fully QOM'ified.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> (for mb + cris)
Acked-by: Alexander Graf <agraf@suse.de> (for ppc)
Acked-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-04 23:00:45 +02:00
Andreas Färber
df90dadb45 target-arm: Use cpu_reset() in cpu_arm_init()
Commit 3c30dd5a68 (target-arm: Move reset
handling to arm_cpu_reset) QOM'ified CPU reset. Complete it by replacing
cpu_state_reset() with cpu_reset().

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-04 23:00:40 +02:00
Peter Maydell
ad37ad5b25 target-arm/cpu.h: Make cpu_init("nonexistent cpu") return NULL
The macro definition of cpu_init meant that if cpu_arm_init()
returned NULL this wouldn't result in cpu_init() itself returning
NULL. This had the effect that "-cpu foo" for some unknown CPU
name 'foo' would cause ARM targets to segfault rather than
generating a useful error message. Fix this by making cpu_init
a simple inline function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-05-10 12:56:09 +00:00
Matt Craighead
7e598de023 target-arm: When setting FPSCR.QC, don't clear other FPSCR bits
This patch fixes a bug affecting a variety of Neon instructions, such as
VQADD.

Signed-off-by: Matt Craighead <mjcraighead@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-05-10 12:56:08 +00:00
Peter Maydell
10962fd510 target-arm: Make SETEND respect bswap_code (BE8) setting
Make the SETEND instruction respect the setting of bswap_code,
so that in BE8 mode we UNDEF for attempts to switch into
little-endian mode and nop for attempts to stay in big-endian
mode. (This is the inverse of the existing handling of SETEND
in the more common little-endian setup, which we use since
we don't implement the architecturally-mandated dynamic
endianness switching.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-27 11:07:52 +00:00
Peter Maydell
c5fad12fa0 target-arm: Move A9 config_base_address reset value to ARMCPU
Move the A9 config_base_address cp15 register reset value to
ARMCPU. This should become a QOM property so that the Highbank
board can set it without having to pull in cpu-qom.h, but at
least this avoids the implicit dependency on reset ordering
that the previous workaround had.

Cc: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-27 11:06:18 +00:00
Andreas Färber
778c3a0619 target-arm: Change cpu_arm_init() return type to ARMCPU
Make cpu_arm_init() return a QOM ARMCPU, so that we don't need to
obtain an ARMCPU through arm_env_get_cpu() in machine init code.
This requires to adjust the inclusion site of cpu-qom.h and in turn,
forward-looking, to homogenize its include order.

cpu_init() must still return a CPUARMState for backwards and
cross-target compatibility, so adjust the cpu_init macro.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-27 11:04:44 +00:00
Peter Maydell
3c30dd5a68 target-arm: Move reset handling to arm_cpu_reset
Now that cpu_reset_model_id() has gone we can move the
reset code over to the class reset function and have cpu_state_reset
simply do a reset on the CPU QOM object.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:13:22 +00:00
Peter Maydell
caa1d0779e target-arm: Drop cpu_reset_model_id()
cpu_reset_model_id() is now empty and we can remove it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:13:19 +00:00
Peter Maydell
85df3786b2 target-arm: Move cache ID register setup to cpu specific init fns
Move cache ID register reset out of cpu_reset_model_id() by
creating a field for the reset value in ARMCPU and setting it
up in the cpu specific init functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:12:29 +00:00
Peter Maydell
8092d2f031 target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_reset
Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset;
since these registers are only accessible on CPUs with the
OMAPCP feature set there's no need to guard this reset with
either a CPUID or feature bit check.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:12:27 +00:00
Peter Maydell
2e4d7e3e3e target-arm: Move feature register setup to per-CPU init fns
Move feature register value setup to per-CPU init functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:11:38 +00:00