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target-arm: Move A9 config_base_address reset value to ARMCPU

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Move the A9 config_base_address cp15 register reset value to
ARMCPU. This should become a QOM property so that the Highbank
board can set it without having to pull in cpu-qom.h, but at
least this avoids the implicit dependency on reset ordering
that the previous workaround had.

Cc: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Peter Maydell 2012-04-20 07:39:15 +00:00
parent 778c3a0619
commit c5fad12fa0
3 changed files with 8 additions and 12 deletions
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15
hw/highbank.c
View File

@ -35,12 +35,6 @@
#define NIRQ_GIC 160
/* Board init. */
static void highbank_cpu_reset(void *opaque)
{
CPUARMState *env = opaque;
env->cp15.c15_config_base_address = GIC_BASE_ADDR;
}
static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)
{
@ -213,14 +207,17 @@ static void highbank_init(ram_addr_t ram_size,
}
for (n = 0; n < smp_cpus; n++) {
env = cpu_init(cpu_model);
if (!env) {
ARMCPU *cpu;
cpu = cpu_arm_init(cpu_model);
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
env = &cpu->env;
/* This will become a QOM property eventually */
cpu->reset_cbar = GIC_BASE_ADDR;
irqp = arm_pic_init_cpu(env);
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
qemu_register_reset(highbank_cpu_reset, env);
}
sysmem = get_system_memory();

1
target-arm/cpu-qom.h
View File

@ -93,6 +93,7 @@ typedef struct ARMCPU {
* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
*/
uint32_t ccsidr[16];
uint32_t reset_cbar;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)

4
target-arm/cpu.c
View File

@ -30,7 +30,6 @@ static void arm_cpu_reset(CPUState *s)
ARMCPU *cpu = ARM_CPU(s);
ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
CPUARMState *env = &cpu->env;
uint32_t tmp = 0;
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@ -39,9 +38,8 @@ static void arm_cpu_reset(CPUState *s)
acc->parent_reset(s);
tmp = env->cp15.c15_config_base_address;
memset(env, 0, offsetof(CPUARMState, breakpoints));
env->cp15.c15_config_base_address = tmp;
env->cp15.c15_config_base_address = cpu->reset_cbar;
env->cp15.c0_cpuid = cpu->midr;
env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;