Commit Graph

363 Commits

Author SHA1 Message Date
Stefan Hajnoczi
195801d700 system/cpus: rename qemu_mutex_lock_iothread() to bql_lock()
The Big QEMU Lock (BQL) has many names and they are confusing. The
actual QemuMutex variable is called qemu_global_mutex but it's commonly
referred to as the BQL in discussions and some code comments. The
locking APIs, however, are called qemu_mutex_lock_iothread() and
qemu_mutex_unlock_iothread().

The "iothread" name is historic and comes from when the main thread was
split into into KVM vcpu threads and the "iothread" (now called the main
loop thread). I have contributed to the confusion myself by introducing
a separate --object iothread, a separate concept unrelated to the BQL.

The "iothread" name is no longer appropriate for the BQL. Rename the
locking APIs to:
- void bql_lock(void)
- void bql_unlock(void)
- bool bql_locked(void)

There are more APIs with "iothread" in their names. Subsequent patches
will rename them. There are also comments and documentation that will be
updated in later patches.

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Paul Durrant <paul@xen.org>
Acked-by: Fabiano Rosas <farosas@suse.de>
Acked-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Peter Xu <peterx@redhat.com>
Acked-by: Eric Farman <farman@linux.ibm.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Acked-by: Hyman Huang <yong.huang@smartx.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-id: 20240102153529.486531-2-stefanha@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-01-08 10:45:43 -05:00
Gavin Shan
d33fc716dc target/hppa: Use generic cpu_list()
No changes in the output from the following command.

[gshan@gshan q]$ ./build/qemu-system-hppa -cpu ?
Available CPUs:
  hppa
  hppa64

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231114235628.534334-13-gshan@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-01-05 16:20:14 +01:00
Philippe Mathieu-Daudé
d5be19f514 cpu: Call object_class_dynamic_cast() once in cpu_class_by_name()
For all targets, the CPU class returned from CPUClass::class_by_name()
and object_class_dynamic_cast(oc, CPU_RESOLVING_TYPE) need to be
compatible. Lets apply the check in cpu_class_by_name() for once,
instead of having the check in CPUClass::class_by_name() for individual
target.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Gavin Shan <gshan@redhat.com>
Message-ID: <20231114235628.534334-4-gshan@redhat.com>
2024-01-05 16:20:14 +01:00
Gavin Shan
b0b8fa1814 target/hppa: Remove object_class_is_abstract()
Since commit 3a9d0d7b64 ("hw/cpu: Call object_class_is_abstract()
once in cpu_class_by_name()"), there is no need to check if @oc is
abstract because it has been covered by cpu_class_by_name().

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231114235628.534334-3-gshan@redhat.com>
[PMD: Mention commit 3a9d0d7b64]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-01-05 16:20:14 +01:00
Richard Henderson
218eee7047 target/hppa: Constify VMState in machine.c
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231221031652.119827-8-richard.henderson@linaro.org>
2023-12-29 11:17:30 +11:00
Stefan Hajnoczi
1817af991c HPPA64-PATCHES-for-8.2
Two patches for 8.2.
 
 The SHRPD patch fixes a real translation bug which then allows to boot
 the 64-bit Linux kernels of the Debian-11 and Debian-12 installation CDs.
 
 The second patch adds the instruction byte sequence to the
 assembly log. This is not an actual bug fix, but it's important since
 it helps a lot when trying to fix qemu translation bugs on hppa.
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZVfHPwAKCRD3ErUQojoP
 X3TrAQD2SfFsTWIYqTamh1ZHmydaJRL1xhXmPMqXgXFkDmiyhQD/VeyIyWEGj5Oe
 x70WR8HrtkadsUddgSGzFRChaVb0/wI=
 =Sapq
 -----END PGP SIGNATURE-----

Merge tag 'hppa64-fixes-pull-request' of https://github.com/hdeller/qemu-hppa into staging

HPPA64-PATCHES-for-8.2

Two patches for 8.2.

The SHRPD patch fixes a real translation bug which then allows to boot
the 64-bit Linux kernels of the Debian-11 and Debian-12 installation CDs.

The second patch adds the instruction byte sequence to the
assembly log. This is not an actual bug fix, but it's important since
it helps a lot when trying to fix qemu translation bugs on hppa.

# -----BEGIN PGP SIGNATURE-----
#
# iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZVfHPwAKCRD3ErUQojoP
# X3TrAQD2SfFsTWIYqTamh1ZHmydaJRL1xhXmPMqXgXFkDmiyhQD/VeyIyWEGj5Oe
# x70WR8HrtkadsUddgSGzFRChaVb0/wI=
# =Sapq
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 17 Nov 2023 15:04:15 EST
# gpg:                using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F
# gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown]
# gpg:                 aka "Helge Deller <deller@kernel.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4544 8228 2CD9 10DB EF3D  25F8 3E5F 3D04 A7A2 4603
#      Subkey fingerprint: BCE9 123E 1AD2 9F07 C049  BBDE F712 B510 A23A 0F5F

* tag 'hppa64-fixes-pull-request' of https://github.com/hdeller/qemu-hppa:
  disas/hppa: Show hexcode of instruction along with disassembly
  target/hppa: Fix 64-bit SHRPD instruction

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-20 05:24:08 -05:00
Helge Deller
a01491a238 target/hppa: Fix 64-bit SHRPD instruction
When shifting the two joined 64-bit registers right, shift the upper
64-bit register to the left and the lower 64-bit register to the right
before merging them with OR.

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-17 18:36:36 +01:00
Michael Tokarev
385b3280ce target/hppa: spelling fixes: Indicies, Truely
Fixes: bb67ec32a0 "target/hppa: Include PSW_P in tb flags and mmu index"
Fixes: d7553f3591 "target/hppa: Populate an interval tree with valid tlb entries"
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-11-15 11:59:54 +03:00
Richard Henderson
fa71b4f84f target/hppa: Reduce TARGET_PHYS_ADDR_SPACE_BITS to 40
This is the value that is supported by both PA-8500 and Astro.
If we support a larger address space than expected, we trip up
software that did not fill in all of the page table bits,
expecting them to be ignored.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13 09:21:32 -08:00
Richard Henderson
451d993d58 target/hppa: Replace MMU_PHYS_IDX with MMU_ABS_IDX, MMU_ABS_W_IDX
Align the language with pa2.0, separating absolute and physical.
The translation from absolute to physical depends on PSW.W, and
we prefer not to flush between changes, therefore use 2 mmu_idx.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13 09:20:43 -08:00
Richard Henderson
17fe594c59 target/hppa: Introduce MMU_IDX_MMU_DISABLED
Reduce the number of direct checks against MMU_PHYS_IDX.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13 09:17:21 -08:00
Helge Deller
2a23f0f118 target/hppa: Fix possible overflow in TLB size calculation
Coverty found that the shift of TARGET_PAGE_SIZE (32-bit type) might
overflow.  Fix it by casting TARGET_PAGE_SIZE to a 64-bit type before
doing the shift (CID 1523902 and CID 1523908).

Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Helge Deller <deller@gmx.de>
Message-Id: <ZU6F/H8CZr3q4pP/@p100>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13 09:17:07 -08:00
Helge Deller
e722e5a112 target/hppa: Fix calculation of CR_IIASQ back register
Need to use iasq_b and iaoq_b to determine back register of CR_IIASQ.
This fixes random faults when booting up Linux user space.

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13 09:17:07 -08:00
Richard Henderson
576fc9376d target/hppa: Use PRIV_P_TO_MMU_IDX in helper_probe
Direct privilege level to mmu_idx mapping has been
false for some time.  Provide the correct value to
hppa_get_physical_address.

Fixes: fa824d99f9 ("target/hppa: Switch to use MMU indices 11-15")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13 09:17:07 -08:00
Richard Henderson
e5d487c972 target/hppa: Use only low 2 immediate bits for PROBEI
During the conversion to decodetree, the 2-bit mask was lost.

Fixes: deee69a19f ("target/hppa: Convert memory management insns")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13 09:16:36 -08:00
Helge Deller
881d1073d0 target/hppa: Mask reserved PSW bits in expand_sm_imm
The system mask is a restricted subset of the psw, with only
a couple of reserved bits.  It is better to handle this up
front in the translator than require helper_swap_system_mask
to use cpu_hppa_get_psw and cpu_hppa_put_psw.

Signed-off-by: Helge Deller <deller@gmx.de>
[rth: Handle this in expand_sm_imm not helper_swap_system_mask.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-12 09:01:22 -08:00
Philippe Mathieu-Daudé
9348028e7e target: Move ArchCPUClass definition to 'cpu.h'
The OBJECT_DECLARE_CPU_TYPE() macro forward-declares each
ArchCPUClass type. These forward declarations are sufficient
for code in hw/ to use the QOM definitions. No need to expose
these structure definitions. Keep each local to their target/
by moving them to the corresponding "cpu.h" header.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013140116.255-13-philmd@linaro.org>
2023-11-07 13:08:48 +01:00
Philippe Mathieu-Daudé
336588a29d target: Mention 'cpu-qom.h' is target agnostic
"target/foo/cpu-qom.h" is supposed to be target agnostic
(include-able by any target). Add such mention in the
header.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013140116.255-3-philmd@linaro.org>
2023-11-07 12:13:27 +01:00
Philippe Mathieu-Daudé
6ee45fac56 target: Unify QOM style
Enforce the style described by commit 067109a11c ("docs/devel:
mention the spacing requirement for QOM"):

  The first declaration of a storage or class structure should
  always be the parent and leave a visual space between that
  declaration and the new code. It is also useful to separate
  backing for properties (options driven by the user) and internal
  state to make navigation easier.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231013140116.255-2-philmd@linaro.org>
2023-11-07 12:13:27 +01:00
Richard Henderson
5dd5c00366 target/hppa: Improve interrupt logging
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
b10700d826 target/hppa: Update IIAOQ, IIASQ for pa2.0
These registers have a different format for pa2.0.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
8a02b9a68e target/hppa: Create raise_exception_with_ior
Handle pa2.0 logic for filling in ISR+IOR.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
f5b5c85760 target/hppa: Add unwind_breg to CPUHPPAState
Fill in the insn_start value during form_gva, and copy
it out to the env field in hppa_restore_state_to_opc.
The value is not yet consumed.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Helge Deller
4c34bab0d3 target/hppa: Clear upper bits in mtctl for pa1.x
Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
34a0d9eefe target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Helge Deller
eb25d10f4d target/hppa: Add pa2.0 cpu local tlb flushes
The previous decoding misnamed the bit it called "local".
Other than the name, the implementation was correct for pa1.x.
Rename this field to "tlbe".

PA2.0 adds (a real) local bit to PxTLB, and also adds a range
of pages to flush in GR[b].

Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
b5caa17cda target/hppa: Implement pa2.0 data prefetch instructions
These are aliased onto the normal integer loads to %g0.
Since we don't emulate caches, prefetch is a nop.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
bc3da3cf62 target/hppa: Return zero for r0 from load_gpr
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
a4db4a7811 target/hppa: Precompute zero into DisasContext
Reduce the number of times we look for the constant 0.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Helge Deller
ab9af359c1 target/hppa: Fix interruption based on default PSW
The default PSW is set by the operating system with the PDC_PSW
firmware call.  Use that setting to decide if wide mode is to be
enabled for interruptions and EIRR usage.

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
4e7abdb120 target/hppa: Implement PERMH
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
c2a7ee3f9d target/hppa: Implement MIXH, MIXW
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
3bbb8e4832 target/hppa: Implement HSHLADD, HSHRADD
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
151f309b98 target/hppa: Implement HSHL, HSHR
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
1b3cb7c874 target/hppa: Implement HAVG
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
10c9e58d5c target/hppa: Implement HSUB
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
0843563f3e target/hppa: Implement HADD
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
d265360f07 target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
aac0f603de target/hppa: Use tcg_temp_new_i64 not tcg_temp_new
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
ea6c40b0f1 target/hppa: Adjust vmstate_env for pa2.0 tlb
Split out the tlb to a subsection so that it can be separately
versioned -- the format is only partially following the architecture
and is partially guided by the qemu implementation.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
967662cd5a target/hppa: Remove remaining TARGET_REGISTER_BITS redirections
The conversions to/from i64 can be eliminated entirely,
folding computation into adjacent operations.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
6fd0c7bc91 target/hppa: Remove most of the TARGET_REGISTER_BITS redirections
Remove all but those intended to change type to or from i64.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
c53e401ed9 target/hppa: Remove TARGET_REGISTER_BITS
Rely only on TARGET_LONG_BITS, fixed at 64, and hppa_is_pa20.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
8577f35479 target/hppa: Implement IDTLBT, IITLBT
Rename the existing insert tlb helpers to emphasize that they
are for pa1.1 cpus.  Implement a combined i/d tlb for pa2.0.
Still missing is the new 'P' tlb bit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
25460fc5a7 target/hppa: Implement STDBY
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
a8966ba70a target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
f7b775a9c0 target/hppa: Implement SHRPD
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
bd792da354 target/hppa: Implement EXTRD
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
72ae4f2b82 target/hppa: Implement DEPD, DEPDI
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
51416c4e41 target/hppa: Implement LDD, LDCD, LDDA, STD, STDA
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00