target/hppa: Convert memory management insns
Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
7aee8189ad
commit
deee69a19f
@ -22,9 +22,17 @@
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####
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%assemble_sr3 13:1 14:2
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%assemble_sr3x 13:1 14:2 !function=expand_sr3x
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%sm_imm 16:10 !function=expand_sm_imm
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####
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# Argument set definitions
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####
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# All insns that need to form a virtual address should use this set.
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&ldst t b x disp sp m scale size
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####
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# System
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####
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@ -49,3 +57,33 @@ ssm 000000 .......... 000 01101011 t:5 i=%sm_imm
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rfi 000000 ----- ----- --- 01100000 00000
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rfi_r 000000 ----- ----- --- 01100101 00000
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####
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# Memory Management
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####
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@addrx ...... b:5 x:5 .. ........ m:1 ..... \
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&ldst disp=0 scale=0 t=0 sp=0 size=0
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nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp
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nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index
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nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce
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nop_addrx 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a
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nop_addrx 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f
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nop_addrx 000001 ..... ..... --- 0001011 . ----- @addrx # fice
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nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc
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probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5
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ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1
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ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \
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sp=%assemble_sr3x data=0
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pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1
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pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \
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sp=%assemble_sr3x data=0
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lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \
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&ldst disp=0 scale=0 size=0
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lci 000001 ----- ----- -- 01001100 0 t:5
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@ -290,6 +290,12 @@ static int expand_sm_imm(int val)
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return val;
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}
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/* Inverted space register indicates 0 means sr0 not inferred from base. */
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static int expand_sr3x(int val)
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{
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return ~val;
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}
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/* Include the auto-generated decoder. */
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#include "decode.inc.c"
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@ -1997,7 +2003,7 @@ static void do_page_zero(DisasContext *ctx)
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}
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#endif
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static bool trans_nop(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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static bool trans_nop(DisasContext *ctx, arg_nop *a)
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{
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cond_free(&ctx->null_cond);
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return true;
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@ -2317,81 +2323,62 @@ static bool gen_hlt(DisasContext *ctx, int reset)
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}
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#endif /* !CONFIG_USER_ONLY */
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static bool trans_base_idx_mod(DisasContext *ctx, uint32_t insn,
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const DisasInsn *di)
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static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a)
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{
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unsigned rb = extract32(insn, 21, 5);
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unsigned rx = extract32(insn, 16, 5);
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TCGv_reg dest = dest_gpr(ctx, rb);
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TCGv_reg src1 = load_gpr(ctx, rb);
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TCGv_reg src2 = load_gpr(ctx, rx);
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/* The only thing we need to do is the base register modification. */
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tcg_gen_add_reg(dest, src1, src2);
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save_gpr(ctx, rb, dest);
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if (a->m) {
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TCGv_reg dest = dest_gpr(ctx, a->b);
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TCGv_reg src1 = load_gpr(ctx, a->b);
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TCGv_reg src2 = load_gpr(ctx, a->x);
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/* The only thing we need to do is the base register modification. */
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tcg_gen_add_reg(dest, src1, src2);
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save_gpr(ctx, a->b, dest);
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}
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cond_free(&ctx->null_cond);
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return true;
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}
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static bool trans_probe(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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static bool trans_probe(DisasContext *ctx, arg_probe *a)
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{
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unsigned rt = extract32(insn, 0, 5);
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unsigned sp = extract32(insn, 14, 2);
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unsigned rr = extract32(insn, 16, 5);
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unsigned rb = extract32(insn, 21, 5);
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unsigned is_write = extract32(insn, 6, 1);
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unsigned is_imm = extract32(insn, 13, 1);
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TCGv_reg dest, ofs;
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TCGv_i32 level, want;
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TCGv_tl addr;
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nullify_over(ctx);
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dest = dest_gpr(ctx, rt);
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form_gva(ctx, &addr, &ofs, rb, 0, 0, 0, sp, 0, false);
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dest = dest_gpr(ctx, a->t);
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form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false);
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if (is_imm) {
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level = tcg_const_i32(extract32(insn, 16, 2));
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if (a->imm) {
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level = tcg_const_i32(a->ri);
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} else {
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level = tcg_temp_new_i32();
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tcg_gen_trunc_reg_i32(level, load_gpr(ctx, rr));
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tcg_gen_trunc_reg_i32(level, load_gpr(ctx, a->ri));
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tcg_gen_andi_i32(level, level, 3);
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}
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want = tcg_const_i32(is_write ? PAGE_WRITE : PAGE_READ);
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want = tcg_const_i32(a->write ? PAGE_WRITE : PAGE_READ);
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gen_helper_probe(dest, cpu_env, addr, level, want);
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tcg_temp_free_i32(want);
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tcg_temp_free_i32(level);
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save_gpr(ctx, rt, dest);
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save_gpr(ctx, a->t, dest);
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return nullify_end(ctx);
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}
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#ifndef CONFIG_USER_ONLY
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static bool trans_ixtlbx(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a)
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{
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unsigned sp;
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unsigned rr = extract32(insn, 16, 5);
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unsigned rb = extract32(insn, 21, 5);
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unsigned is_data = insn & 0x1000;
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unsigned is_addr = insn & 0x40;
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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#ifndef CONFIG_USER_ONLY
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TCGv_tl addr;
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TCGv_reg ofs, reg;
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if (is_data) {
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sp = extract32(insn, 14, 2);
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} else {
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sp = ~assemble_sr3(insn);
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}
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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nullify_over(ctx);
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form_gva(ctx, &addr, &ofs, rb, 0, 0, 0, sp, 0, false);
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reg = load_gpr(ctx, rr);
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if (is_addr) {
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form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false);
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reg = load_gpr(ctx, a->r);
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if (a->addr) {
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gen_helper_itlba(cpu_env, addr, reg);
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} else {
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gen_helper_itlbp(cpu_env, addr, reg);
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@ -2399,80 +2386,67 @@ static bool trans_ixtlbx(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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/* Exit TB for ITLB change if mmu is enabled. This *should* not be
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the case, since the OS TLB fill handler runs with mmu disabled. */
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if (!is_data && (ctx->tb_flags & PSW_C)) {
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if (!a->data && (ctx->tb_flags & PSW_C)) {
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ctx->base.is_jmp = DISAS_IAQ_N_STALE;
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}
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return nullify_end(ctx);
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#endif
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}
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static bool trans_pxtlbx(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a)
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{
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unsigned m = extract32(insn, 5, 1);
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unsigned sp;
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unsigned rx = extract32(insn, 16, 5);
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unsigned rb = extract32(insn, 21, 5);
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unsigned is_data = insn & 0x1000;
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unsigned is_local = insn & 0x40;
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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#ifndef CONFIG_USER_ONLY
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TCGv_tl addr;
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TCGv_reg ofs;
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if (is_data) {
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sp = extract32(insn, 14, 2);
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} else {
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sp = ~assemble_sr3(insn);
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}
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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nullify_over(ctx);
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form_gva(ctx, &addr, &ofs, rb, rx, 0, 0, sp, m, false);
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if (m) {
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save_gpr(ctx, rb, ofs);
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form_gva(ctx, &addr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false);
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if (a->m) {
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save_gpr(ctx, a->b, ofs);
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}
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if (is_local) {
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if (a->local) {
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gen_helper_ptlbe(cpu_env);
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} else {
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gen_helper_ptlb(cpu_env, addr);
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}
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/* Exit TB for TLB change if mmu is enabled. */
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if (!is_data && (ctx->tb_flags & PSW_C)) {
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if (!a->data && (ctx->tb_flags & PSW_C)) {
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ctx->base.is_jmp = DISAS_IAQ_N_STALE;
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}
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return nullify_end(ctx);
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#endif
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}
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static bool trans_lpa(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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static bool trans_lpa(DisasContext *ctx, arg_ldst *a)
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{
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unsigned rt = extract32(insn, 0, 5);
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unsigned m = extract32(insn, 5, 1);
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unsigned sp = extract32(insn, 14, 2);
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unsigned rx = extract32(insn, 16, 5);
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unsigned rb = extract32(insn, 21, 5);
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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#ifndef CONFIG_USER_ONLY
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TCGv_tl vaddr;
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TCGv_reg ofs, paddr;
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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nullify_over(ctx);
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form_gva(ctx, &vaddr, &ofs, rb, rx, 0, 0, sp, m, false);
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form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false);
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paddr = tcg_temp_new();
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gen_helper_lpa(paddr, cpu_env, vaddr);
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/* Note that physical address result overrides base modification. */
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if (m) {
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save_gpr(ctx, rb, ofs);
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if (a->m) {
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save_gpr(ctx, a->b, ofs);
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}
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save_gpr(ctx, rt, paddr);
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save_gpr(ctx, a->t, paddr);
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tcg_temp_free(paddr);
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return nullify_end(ctx);
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#endif
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}
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static bool trans_lci(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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static bool trans_lci(DisasContext *ctx, arg_lci *a)
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{
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unsigned rt = extract32(insn, 0, 5);
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TCGv_reg ci;
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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@ -2482,43 +2456,12 @@ static bool trans_lci(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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view of the cache. Our implementation is to return 0 for all,
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since the entire address space is coherent. */
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ci = tcg_const_reg(0);
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save_gpr(ctx, rt, ci);
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save_gpr(ctx, a->t, ci);
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tcg_temp_free(ci);
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cond_free(&ctx->null_cond);
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return true;
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}
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#endif /* !CONFIG_USER_ONLY */
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static const DisasInsn table_mem_mgmt[] = {
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{ 0x04003280u, 0xfc003fffu, trans_nop }, /* fdc, disp */
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{ 0x04001280u, 0xfc003fffu, trans_nop }, /* fdc, index */
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{ 0x040012a0u, 0xfc003fffu, trans_base_idx_mod }, /* fdc, index, base mod */
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{ 0x040012c0u, 0xfc003fffu, trans_nop }, /* fdce */
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{ 0x040012e0u, 0xfc003fffu, trans_base_idx_mod }, /* fdce, base mod */
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{ 0x04000280u, 0xfc001fffu, trans_nop }, /* fic 0a */
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{ 0x040002a0u, 0xfc001fffu, trans_base_idx_mod }, /* fic 0a, base mod */
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{ 0x040013c0u, 0xfc003fffu, trans_nop }, /* fic 4f */
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{ 0x040013e0u, 0xfc003fffu, trans_base_idx_mod }, /* fic 4f, base mod */
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{ 0x040002c0u, 0xfc001fffu, trans_nop }, /* fice */
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{ 0x040002e0u, 0xfc001fffu, trans_base_idx_mod }, /* fice, base mod */
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{ 0x04002700u, 0xfc003fffu, trans_nop }, /* pdc */
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{ 0x04002720u, 0xfc003fffu, trans_base_idx_mod }, /* pdc, base mod */
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{ 0x04001180u, 0xfc003fa0u, trans_probe }, /* probe */
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{ 0x04003180u, 0xfc003fa0u, trans_probe }, /* probei */
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#ifndef CONFIG_USER_ONLY
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{ 0x04000000u, 0xfc001fffu, trans_ixtlbx }, /* iitlbp */
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{ 0x04000040u, 0xfc001fffu, trans_ixtlbx }, /* iitlba */
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{ 0x04001000u, 0xfc001fffu, trans_ixtlbx }, /* idtlbp */
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{ 0x04001040u, 0xfc001fffu, trans_ixtlbx }, /* idtlba */
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{ 0x04000200u, 0xfc001fdfu, trans_pxtlbx }, /* pitlb */
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{ 0x04000240u, 0xfc001fdfu, trans_pxtlbx }, /* pitlbe */
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{ 0x04001200u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlb */
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{ 0x04001240u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlbe */
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{ 0x04001340u, 0xfc003fc0u, trans_lpa },
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{ 0x04001300u, 0xfc003fe0u, trans_lci },
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#endif
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};
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static bool trans_add(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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{
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@ -4544,9 +4487,6 @@ static void translate_one(DisasContext *ctx, uint32_t insn)
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opc = extract32(insn, 26, 6);
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switch (opc) {
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case 0x01:
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translate_table(ctx, insn, table_mem_mgmt);
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return;
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case 0x02:
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translate_table(ctx, insn, table_arith_log);
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return;
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