target/hppa: Use tcg_temp_new_i64 not tcg_temp_new
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
ea6c40b0f1
commit
aac0f603de
@ -32,6 +32,8 @@
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#include "exec/helper-info.c.inc"
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#undef HELPER_H
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/* Choose to use explicit sizes within this file. */
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#undef tcg_temp_new
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typedef struct DisasCond {
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TCGCond c;
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@ -269,15 +271,15 @@ static DisasCond cond_make_0_tmp(TCGCond c, TCGv_i64 a0)
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static DisasCond cond_make_0(TCGCond c, TCGv_i64 a0)
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{
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TCGv_i64 tmp = tcg_temp_new();
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_mov_i64(tmp, a0);
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return cond_make_0_tmp(c, tmp);
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}
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static DisasCond cond_make(TCGCond c, TCGv_i64 a0, TCGv_i64 a1)
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{
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TCGv_i64 t0 = tcg_temp_new();
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TCGv_i64 t1 = tcg_temp_new();
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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tcg_gen_mov_i64(t0, a0);
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tcg_gen_mov_i64(t1, a1);
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@ -302,7 +304,7 @@ static void cond_free(DisasCond *cond)
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static TCGv_i64 load_gpr(DisasContext *ctx, unsigned reg)
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{
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if (reg == 0) {
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TCGv_i64 t = tcg_temp_new();
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TCGv_i64 t = tcg_temp_new_i64();
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tcg_gen_movi_i64(t, 0);
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return t;
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} else {
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@ -313,7 +315,7 @@ static TCGv_i64 load_gpr(DisasContext *ctx, unsigned reg)
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static TCGv_i64 dest_gpr(DisasContext *ctx, unsigned reg)
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{
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if (reg == 0 || ctx->null_cond.c != TCG_COND_NEVER) {
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return tcg_temp_new();
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return tcg_temp_new_i64();
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} else {
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return cpu_gr[reg];
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}
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@ -437,7 +439,7 @@ static void nullify_over(DisasContext *ctx)
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/* If we're using PSW[N], copy it to a temp because... */
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if (ctx->null_cond.a0 == cpu_psw_n) {
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ctx->null_cond.a0 = tcg_temp_new();
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ctx->null_cond.a0 = tcg_temp_new_i64();
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tcg_gen_mov_i64(ctx->null_cond.a0, cpu_psw_n);
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}
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/* ... we clear it before branching over the implementation,
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@ -657,14 +659,14 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
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break;
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case 1: /* = / <> (Z / !Z) */
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if (cond_need_ext(ctx, d)) {
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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tcg_gen_ext32u_i64(tmp, res);
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res = tmp;
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}
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cond = cond_make_0(TCG_COND_EQ, res);
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break;
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case 2: /* < / >= (N ^ V / !(N ^ V) */
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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tcg_gen_xor_i64(tmp, res, sv);
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if (cond_need_ext(ctx, d)) {
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tcg_gen_ext32s_i64(tmp, tmp);
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@ -681,7 +683,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
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* !(~(res ^ sv) >> 31) | !res
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* !(~(res ^ sv) >> 31 & res)
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*/
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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tcg_gen_eqv_i64(tmp, res, sv);
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if (cond_need_ext(ctx, d)) {
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tcg_gen_sextract_i64(tmp, tmp, 31, 1);
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@ -698,7 +700,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
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cond = cond_make_0(TCG_COND_EQ, cb_msb);
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break;
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case 5: /* ZNV / VNZ (!C | Z / C & !Z) */
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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tcg_gen_neg_i64(tmp, cb_msb);
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tcg_gen_and_i64(tmp, tmp, res);
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if (cond_need_ext(ctx, d)) {
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@ -708,14 +710,14 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
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break;
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case 6: /* SV / NSV (V / !V) */
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if (cond_need_ext(ctx, d)) {
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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tcg_gen_ext32s_i64(tmp, sv);
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sv = tmp;
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}
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cond = cond_make_0(TCG_COND_LT, sv);
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break;
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case 7: /* OD / EV */
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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tcg_gen_andi_i64(tmp, res, 1);
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cond = cond_make_0_tmp(TCG_COND_NE, tmp);
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break;
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@ -769,8 +771,8 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d,
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tc = tcg_invert_cond(tc);
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}
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if (cond_need_ext(ctx, d)) {
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TCGv_i64 t1 = tcg_temp_new();
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TCGv_i64 t2 = tcg_temp_new();
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TCGv_i64 t1 = tcg_temp_new_i64();
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TCGv_i64 t2 = tcg_temp_new_i64();
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if (ext_uns) {
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tcg_gen_ext32u_i64(t1, in1);
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@ -846,7 +848,7 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d,
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}
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if (cond_need_ext(ctx, d)) {
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TCGv_i64 tmp = tcg_temp_new();
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TCGv_i64 tmp = tcg_temp_new_i64();
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if (ext_uns) {
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tcg_gen_ext32u_i64(tmp, res);
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@ -891,8 +893,8 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_i64 res,
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* do our normal thing and compute carry-in of bit B+1 since that
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* leaves us with carry bits spread across two words.
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*/
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cb = tcg_temp_new();
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tmp = tcg_temp_new();
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cb = tcg_temp_new_i64();
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tmp = tcg_temp_new_i64();
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tcg_gen_or_i64(cb, in1, in2);
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tcg_gen_and_i64(tmp, in1, in2);
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tcg_gen_andc_i64(cb, cb, res);
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@ -910,7 +912,7 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_i64 res,
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/* See hasless(v,1) from
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* https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
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*/
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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tcg_gen_subi_i64(tmp, res, d_repl * 0x01010101u);
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tcg_gen_andc_i64(tmp, tmp, res);
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tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80808080u);
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@ -918,7 +920,7 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_i64 res,
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break;
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case 3: /* SHZ / NHZ */
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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tcg_gen_subi_i64(tmp, res, d_repl * 0x00010001u);
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tcg_gen_andc_i64(tmp, tmp, res);
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tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80008000u);
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@ -954,7 +956,7 @@ static TCGv_i64 get_carry(DisasContext *ctx, bool d,
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TCGv_i64 cb, TCGv_i64 cb_msb)
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{
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if (cond_need_ext(ctx, d)) {
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TCGv_i64 t = tcg_temp_new();
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TCGv_i64 t = tcg_temp_new_i64();
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tcg_gen_extract_i64(t, cb, 32, 1);
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return t;
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}
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@ -970,8 +972,8 @@ static TCGv_i64 get_psw_carry(DisasContext *ctx, bool d)
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static TCGv_i64 do_add_sv(DisasContext *ctx, TCGv_i64 res,
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TCGv_i64 in1, TCGv_i64 in2)
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{
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TCGv_i64 sv = tcg_temp_new();
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TCGv_i64 tmp = tcg_temp_new();
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TCGv_i64 sv = tcg_temp_new_i64();
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_xor_i64(sv, res, in1);
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tcg_gen_xor_i64(tmp, in1, in2);
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@ -984,8 +986,8 @@ static TCGv_i64 do_add_sv(DisasContext *ctx, TCGv_i64 res,
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static TCGv_i64 do_sub_sv(DisasContext *ctx, TCGv_i64 res,
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TCGv_i64 in1, TCGv_i64 in2)
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{
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TCGv_i64 sv = tcg_temp_new();
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TCGv_i64 tmp = tcg_temp_new();
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TCGv_i64 sv = tcg_temp_new_i64();
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_xor_i64(sv, res, in1);
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tcg_gen_xor_i64(tmp, in1, in2);
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@ -1002,21 +1004,21 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
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unsigned c = cf >> 1;
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DisasCond cond;
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dest = tcg_temp_new();
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dest = tcg_temp_new_i64();
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cb = NULL;
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cb_msb = NULL;
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cb_cond = NULL;
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if (shift) {
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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tcg_gen_shli_i64(tmp, in1, shift);
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in1 = tmp;
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}
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if (!is_l || cond_need_cb(c)) {
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TCGv_i64 zero = tcg_constant_i64(0);
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cb_msb = tcg_temp_new();
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cb = tcg_temp_new();
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cb_msb = tcg_temp_new_i64();
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cb = tcg_temp_new_i64();
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tcg_gen_add2_i64(dest, cb_msb, in1, zero, in2, zero);
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if (is_c) {
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@ -1048,7 +1050,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
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/* Emit any conditional trap before any writeback. */
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cond = do_cond(ctx, cf, d, dest, cb_cond, sv);
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if (is_tc) {
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1);
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gen_helper_tcond(tcg_env, tmp);
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}
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@ -1103,9 +1105,9 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
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unsigned c = cf >> 1;
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DisasCond cond;
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dest = tcg_temp_new();
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cb = tcg_temp_new();
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cb_msb = tcg_temp_new();
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dest = tcg_temp_new_i64();
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cb = tcg_temp_new_i64();
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cb_msb = tcg_temp_new_i64();
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zero = tcg_constant_i64(0);
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if (is_b) {
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@ -1144,7 +1146,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
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/* Emit any conditional trap before any writeback. */
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if (is_tc) {
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1);
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gen_helper_tcond(tcg_env, tmp);
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}
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@ -1193,7 +1195,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
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TCGv_i64 dest, sv;
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DisasCond cond;
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dest = tcg_temp_new();
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dest = tcg_temp_new_i64();
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tcg_gen_sub_i64(dest, in1, in2);
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/* Compute signed overflow if required. */
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@ -1258,13 +1260,13 @@ static void do_unit(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
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save_gpr(ctx, rt, dest);
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cond_free(&ctx->null_cond);
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} else {
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dest = tcg_temp_new();
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dest = tcg_temp_new_i64();
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fn(dest, in1, in2);
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cond = do_unit_cond(cf, d, dest, in1, in2);
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if (is_tc) {
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TCGv_i64 tmp = tcg_temp_new();
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1);
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gen_helper_tcond(tcg_env, tmp);
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}
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@ -1299,7 +1301,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_i64 base)
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}
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ptr = tcg_temp_new_ptr();
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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spc = tcg_temp_new_i64();
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/* Extract top 2 bits of the address, shift left 3 for uint64_t index. */
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@ -1324,11 +1326,11 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs,
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/* Note that RX is mutually exclusive with DISP. */
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if (rx) {
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ofs = tcg_temp_new();
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ofs = tcg_temp_new_i64();
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tcg_gen_shli_i64(ofs, cpu_gr[rx], scale);
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tcg_gen_add_i64(ofs, ofs, base);
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} else if (disp || modify) {
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ofs = tcg_temp_new();
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ofs = tcg_temp_new_i64();
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tcg_gen_addi_i64(ofs, base, disp);
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} else {
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ofs = base;
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@ -1434,7 +1436,7 @@ static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb,
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dest = dest_gpr(ctx, rt);
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} else {
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/* Make sure if RT == RB, we see the result of the load. */
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dest = tcg_temp_new();
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dest = tcg_temp_new_i64();
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}
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do_load_64(ctx, dest, rb, rx, scale, disp, sp, modify, mop);
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save_gpr(ctx, rt, dest);
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@ -1750,7 +1752,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest,
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if (link != 0) {
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copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
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}
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next = tcg_temp_new();
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next = tcg_temp_new_i64();
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tcg_gen_mov_i64(next, dest);
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if (is_n) {
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if (use_nullify_skip(ctx)) {
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@ -1779,7 +1781,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest,
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branching. Since IOAQ_F is not really live at this point, we
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can simply store DEST optimistically. Similarly with IAOQ_B. */
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copy_iaoq_entry(ctx, cpu_iaoq_f, -1, dest);
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next = tcg_temp_new();
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next = tcg_temp_new_i64();
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tcg_gen_addi_i64(next, dest, 4);
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copy_iaoq_entry(ctx, cpu_iaoq_b, -1, next);
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@ -1794,8 +1796,8 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest,
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a0 = ctx->null_cond.a0;
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a1 = ctx->null_cond.a1;
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tmp = tcg_temp_new();
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next = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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next = tcg_temp_new_i64();
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copy_iaoq_entry(ctx, tmp, ctx->iaoq_n, ctx->iaoq_n_var);
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tcg_gen_movcond_i64(c, next, a0, a1, tmp, dest);
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@ -1837,11 +1839,11 @@ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset)
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return offset;
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case 3:
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/* Privilege 3 is minimum and is never allowed to increase. */
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dest = tcg_temp_new();
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dest = tcg_temp_new_i64();
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tcg_gen_ori_i64(dest, offset, 3);
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break;
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default:
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dest = tcg_temp_new();
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dest = tcg_temp_new_i64();
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tcg_gen_andi_i64(dest, offset, -4);
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tcg_gen_ori_i64(dest, dest, ctx->privilege);
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tcg_gen_movcond_i64(TCG_COND_GTU, dest, dest, offset, dest, offset);
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@ -1898,7 +1900,7 @@ static void do_page_zero(DisasContext *ctx)
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case 0xe0: /* SET_THREAD_POINTER */
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tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27]));
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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tcg_gen_ori_i64(tmp, cpu_gr[31], 3);
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copy_iaoq_entry(ctx, cpu_iaoq_f, -1, tmp);
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tcg_gen_addi_i64(tmp, tmp, 4);
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@ -2004,7 +2006,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a)
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break;
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}
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
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save_gpr(ctx, rt, tmp);
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@ -2045,7 +2047,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
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if (ctl == CR_SAR) {
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reg = load_gpr(ctx, a->r);
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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tcg_gen_andi_i64(tmp, reg, ctx->is_pa20 ? 63 : 31);
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save_or_nullify(ctx, cpu_sar, tmp);
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@ -2076,7 +2078,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
|
||||
case CR_IIAOQ:
|
||||
/* FIXME: Respect PSW_Q bit */
|
||||
/* The write advances the queue and stores to the back element. */
|
||||
tmp = tcg_temp_new();
|
||||
tmp = tcg_temp_new_i64();
|
||||
tcg_gen_ld_i64(tmp, tcg_env,
|
||||
offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ]));
|
||||
tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
|
||||
@ -2104,7 +2106,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
|
||||
|
||||
static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a)
|
||||
{
|
||||
TCGv_i64 tmp = tcg_temp_new();
|
||||
TCGv_i64 tmp = tcg_temp_new_i64();
|
||||
|
||||
tcg_gen_not_i64(tmp, load_gpr(ctx, a->r));
|
||||
tcg_gen_andi_i64(tmp, tmp, ctx->is_pa20 ? 63 : 31);
|
||||
@ -2139,7 +2141,7 @@ static bool trans_rsm(DisasContext *ctx, arg_rsm *a)
|
||||
|
||||
nullify_over(ctx);
|
||||
|
||||
tmp = tcg_temp_new();
|
||||
tmp = tcg_temp_new_i64();
|
||||
tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw));
|
||||
tcg_gen_andi_i64(tmp, tmp, ~a->i);
|
||||
gen_helper_swap_system_mask(tmp, tcg_env, tmp);
|
||||
@ -2159,7 +2161,7 @@ static bool trans_ssm(DisasContext *ctx, arg_ssm *a)
|
||||
|
||||
nullify_over(ctx);
|
||||
|
||||
tmp = tcg_temp_new();
|
||||
tmp = tcg_temp_new_i64();
|
||||
tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw));
|
||||
tcg_gen_ori_i64(tmp, tmp, a->i);
|
||||
gen_helper_swap_system_mask(tmp, tcg_env, tmp);
|
||||
@ -2179,7 +2181,7 @@ static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a)
|
||||
nullify_over(ctx);
|
||||
|
||||
reg = load_gpr(ctx, a->r);
|
||||
tmp = tcg_temp_new();
|
||||
tmp = tcg_temp_new_i64();
|
||||
gen_helper_swap_system_mask(tmp, tcg_env, reg);
|
||||
|
||||
/* Exit the TB to recognize new interrupts. */
|
||||
@ -2434,7 +2436,7 @@ static bool trans_lpa(DisasContext *ctx, arg_ldst *a)
|
||||
|
||||
form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false);
|
||||
|
||||
paddr = tcg_temp_new();
|
||||
paddr = tcg_temp_new_i64();
|
||||
gen_helper_lpa(paddr, tcg_env, vaddr);
|
||||
|
||||
/* Note that physical address result overrides base modification. */
|
||||
@ -2618,7 +2620,7 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc)
|
||||
}
|
||||
tcg_r1 = load_gpr(ctx, a->r1);
|
||||
tcg_r2 = load_gpr(ctx, a->r2);
|
||||
tmp = tcg_temp_new();
|
||||
tmp = tcg_temp_new_i64();
|
||||
tcg_gen_not_i64(tmp, tcg_r2);
|
||||
do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_i64);
|
||||
return nullify_end(ctx);
|
||||
@ -2640,7 +2642,7 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i)
|
||||
|
||||
nullify_over(ctx);
|
||||
|
||||
tmp = tcg_temp_new();
|
||||
tmp = tcg_temp_new_i64();
|
||||
tcg_gen_shri_i64(tmp, cpu_psw_cb, 3);
|
||||
if (!is_i) {
|
||||
tcg_gen_not_i64(tmp, tmp);
|
||||
@ -2672,10 +2674,10 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
|
||||
in1 = load_gpr(ctx, a->r1);
|
||||
in2 = load_gpr(ctx, a->r2);
|
||||
|
||||
add1 = tcg_temp_new();
|
||||
add2 = tcg_temp_new();
|
||||
addc = tcg_temp_new();
|
||||
dest = tcg_temp_new();
|
||||
add1 = tcg_temp_new_i64();
|
||||
add2 = tcg_temp_new_i64();
|
||||
addc = tcg_temp_new_i64();
|
||||
dest = tcg_temp_new_i64();
|
||||
zero = tcg_constant_i64(0);
|
||||
|
||||
/* Form R1 << 1 | PSW[CB]{8}. */
|
||||
@ -2798,7 +2800,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
|
||||
if (a->m) {
|
||||
/* Base register modification. Make sure if RT == RB,
|
||||
we see the result of the load. */
|
||||
dest = tcg_temp_new();
|
||||
dest = tcg_temp_new_i64();
|
||||
} else {
|
||||
dest = dest_gpr(ctx, a->t);
|
||||
}
|
||||
@ -2958,7 +2960,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_i64 in1,
|
||||
DisasCond cond;
|
||||
|
||||
in2 = load_gpr(ctx, r);
|
||||
dest = tcg_temp_new();
|
||||
dest = tcg_temp_new_i64();
|
||||
|
||||
tcg_gen_sub_i64(dest, in1, in2);
|
||||
|
||||
@ -3010,13 +3012,13 @@ static bool do_addb(DisasContext *ctx, unsigned r, TCGv_i64 in1,
|
||||
}
|
||||
|
||||
in2 = load_gpr(ctx, r);
|
||||
dest = tcg_temp_new();
|
||||
dest = tcg_temp_new_i64();
|
||||
sv = NULL;
|
||||
cb_cond = NULL;
|
||||
|
||||
if (cond_need_cb(c)) {
|
||||
TCGv_i64 cb = tcg_temp_new();
|
||||
TCGv_i64 cb_msb = tcg_temp_new();
|
||||
TCGv_i64 cb = tcg_temp_new_i64();
|
||||
TCGv_i64 cb_msb = tcg_temp_new_i64();
|
||||
|
||||
tcg_gen_movi_i64(cb_msb, 0);
|
||||
tcg_gen_add2_i64(dest, cb_msb, in1, cb_msb, in2, cb_msb);
|
||||
@ -3054,7 +3056,7 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
|
||||
|
||||
nullify_over(ctx);
|
||||
|
||||
tmp = tcg_temp_new();
|
||||
tmp = tcg_temp_new_i64();
|
||||
tcg_r = load_gpr(ctx, a->r);
|
||||
if (cond_need_ext(ctx, a->d)) {
|
||||
/* Force shift into [32,63] */
|
||||
@ -3076,7 +3078,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a)
|
||||
|
||||
nullify_over(ctx);
|
||||
|
||||
tmp = tcg_temp_new();
|
||||
tmp = tcg_temp_new_i64();
|
||||
tcg_r = load_gpr(ctx, a->r);
|
||||
p = a->p | (cond_need_ext(ctx, a->d) ? 32 : 0);
|
||||
tcg_gen_shli_i64(tmp, tcg_r, p);
|
||||
@ -3136,7 +3138,7 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a)
|
||||
if (a->d) {
|
||||
tcg_gen_shr_i64(dest, src2, cpu_sar);
|
||||
} else {
|
||||
TCGv_i64 tmp = tcg_temp_new();
|
||||
TCGv_i64 tmp = tcg_temp_new_i64();
|
||||
|
||||
tcg_gen_ext32u_i64(dest, src2);
|
||||
tcg_gen_andi_i64(tmp, cpu_sar, 31);
|
||||
@ -3159,8 +3161,8 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a)
|
||||
TCGv_i64 src1 = load_gpr(ctx, a->r1);
|
||||
|
||||
if (a->d) {
|
||||
TCGv_i64 t = tcg_temp_new();
|
||||
TCGv_i64 n = tcg_temp_new();
|
||||
TCGv_i64 t = tcg_temp_new_i64();
|
||||
TCGv_i64 n = tcg_temp_new_i64();
|
||||
|
||||
tcg_gen_xori_i64(n, cpu_sar, 63);
|
||||
tcg_gen_shl_i64(t, src2, n);
|
||||
@ -3243,7 +3245,7 @@ static bool trans_extr_sar(DisasContext *ctx, arg_extr_sar *a)
|
||||
|
||||
dest = dest_gpr(ctx, a->t);
|
||||
src = load_gpr(ctx, a->r);
|
||||
tmp = tcg_temp_new();
|
||||
tmp = tcg_temp_new_i64();
|
||||
|
||||
/* Recall that SAR is using big-endian bit numbering. */
|
||||
tcg_gen_andi_i64(tmp, cpu_sar, widthm1);
|
||||
@ -3395,14 +3397,14 @@ static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c,
|
||||
uint64_t msb = 1ULL << (len - 1);
|
||||
|
||||
dest = dest_gpr(ctx, rt);
|
||||
shift = tcg_temp_new();
|
||||
tmp = tcg_temp_new();
|
||||
shift = tcg_temp_new_i64();
|
||||
tmp = tcg_temp_new_i64();
|
||||
|
||||
/* Convert big-endian bit numbering in SAR to left-shift. */
|
||||
tcg_gen_andi_i64(shift, cpu_sar, widthm1);
|
||||
tcg_gen_xori_i64(shift, shift, widthm1);
|
||||
|
||||
mask = tcg_temp_new();
|
||||
mask = tcg_temp_new_i64();
|
||||
tcg_gen_movi_i64(mask, msb + (msb - 1));
|
||||
tcg_gen_and_i64(tmp, val, mask);
|
||||
if (rs) {
|
||||
@ -3467,7 +3469,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a)
|
||||
nullify_over(ctx);
|
||||
#endif
|
||||
|
||||
tmp = tcg_temp_new();
|
||||
tmp = tcg_temp_new_i64();
|
||||
tcg_gen_addi_i64(tmp, load_gpr(ctx, a->b), a->disp);
|
||||
tmp = do_ibranch_priv(ctx, tmp);
|
||||
|
||||
@ -3565,7 +3567,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a)
|
||||
static bool trans_blr(DisasContext *ctx, arg_blr *a)
|
||||
{
|
||||
if (a->x) {
|
||||
TCGv_i64 tmp = tcg_temp_new();
|
||||
TCGv_i64 tmp = tcg_temp_new_i64();
|
||||
tcg_gen_shli_i64(tmp, load_gpr(ctx, a->x), 3);
|
||||
tcg_gen_addi_i64(tmp, tmp, ctx->iaoq_f + 8);
|
||||
/* The computation here never changes privilege level. */
|
||||
@ -3583,7 +3585,7 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a)
|
||||
if (a->x == 0) {
|
||||
dest = load_gpr(ctx, a->b);
|
||||
} else {
|
||||
dest = tcg_temp_new();
|
||||
dest = tcg_temp_new_i64();
|
||||
tcg_gen_shli_i64(dest, load_gpr(ctx, a->x), 3);
|
||||
tcg_gen_add_i64(dest, dest, load_gpr(ctx, a->b));
|
||||
}
|
||||
@ -3920,7 +3922,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a)
|
||||
|
||||
nullify_over(ctx);
|
||||
|
||||
t = tcg_temp_new();
|
||||
t = tcg_temp_new_i64();
|
||||
tcg_gen_ld32u_i64(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow));
|
||||
|
||||
if (a->y == 1) {
|
||||
@ -4222,7 +4224,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
|
||||
This will be overwritten by a branch. */
|
||||
if (ctx->iaoq_b == -1) {
|
||||
ctx->iaoq_n = -1;
|
||||
ctx->iaoq_n_var = tcg_temp_new();
|
||||
ctx->iaoq_n_var = tcg_temp_new_i64();
|
||||
tcg_gen_addi_i64(ctx->iaoq_n_var, cpu_iaoq_b, 4);
|
||||
} else {
|
||||
ctx->iaoq_n = ctx->iaoq_b + 4;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user