PReP machine and devices
* Raven PCI host bridge memory fixes (remainder) -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJTKimsAAoJEPou0S0+fgE/E2gP/Ro/xu+tbL41q5Y1rWH+umxy 1UZRYr9pV8MtFGMFC41KeZhKa9l6SjA8R47n8F9dDi/ocwIvg0kmD7LJKmt6MXQE WnjtCByJF9mEJXO0Dx2xmjNYWWTQakaRMhATj/AAuwHVn5mTGki/iKvFgrDTaaA5 GpBIzlNAroaxPGTslrsWnpLg0XuWBHlwUIvDzlNWkYZC+NzYCZH2rN8dX3Cr45V1 kIc3gmVxknrv1/xDEBLOtTuf+1dFWR8Pjhvrv96k0Tp2Wi48K5s6TYJBdLCof4Qy B+4wQbYsFa21rwB1spT41DSU+MKcB2FbjEk5sOSRxQ7yLVq5eSw+/nwVVLi9Ebaa o4/65EF9SZ9KyKIXmmX3vjD742rVqSc5ezgdNegwpcyYa0K0Pli3DHVf77ElPin7 V0yBIMOcGWmwq+V/5PKxvIQ/UsUrV91s93eZAF2uswhKwzLN75gutToXlCO9T4lI cMq781xV6lU1aFggCZ1JelllJTvPSIdadBYVYISLcFmByXbdYoACxlqu/pCfAZJx XDzMJsbc9fLcgoOSgpAlHa2DTFZImuMKc0exXWiV68Dn+wr7Ecs81iIW9uZW2kPO FF7qS3L3F2ivxMwzLA+nBOpiE0Vl7yCmN6Ekxeaw/9GEkyPuFFAvG0My4X0/XnaY 9dulVM6rIhRwP8iLzfBI =BQRy -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/afaerber/tags/prep-for-2.0' into staging PReP machine and devices * Raven PCI host bridge memory fixes (remainder) # gpg: Signature made Wed 19 Mar 2014 23:35:08 GMT using RSA key ID 3E7E013F # gpg: Good signature from "Andreas Färber <afaerber@suse.de>" # gpg: aka "Andreas Färber <afaerber@suse.com>" * remotes/afaerber/tags/prep-for-2.0: raven: Use raven_ for all function prefixes raven: Fix PCI bus accesses with size > 1 raven: Add PCI bus mastering address space raven: Set a correct PCI memory region raven: Set a correct PCI I/O memory region raven: Implement non-contiguous I/O region raven: Rename intack region to pci_intack Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
06c1bee85a
@ -52,15 +52,25 @@ typedef struct RavenPCIState {
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typedef struct PRePPCIState {
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PCIHostState parent_obj;
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MemoryRegion intack;
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qemu_irq irq[PCI_NUM_PINS];
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PCIBus pci_bus;
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AddressSpace pci_io_as;
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MemoryRegion pci_io;
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MemoryRegion pci_io_non_contiguous;
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MemoryRegion pci_memory;
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MemoryRegion pci_intack;
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MemoryRegion bm;
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MemoryRegion bm_ram_alias;
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MemoryRegion bm_pci_memory_alias;
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AddressSpace bm_as;
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RavenPCIState pci_dev;
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int contiguous_map;
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} PREPPCIState;
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#define BIOS_SIZE (1024 * 1024)
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static inline uint32_t PPC_PCIIO_config(hwaddr addr)
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static inline uint32_t raven_pci_io_config(hwaddr addr)
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{
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int i;
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@ -72,53 +82,133 @@ static inline uint32_t PPC_PCIIO_config(hwaddr addr)
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return (addr & 0x7ff) | (i << 11);
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}
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static void ppc_pci_io_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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static void raven_pci_io_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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PREPPCIState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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pci_data_write(phb->bus, PPC_PCIIO_config(addr), val, size);
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pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);
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}
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static uint64_t ppc_pci_io_read(void *opaque, hwaddr addr,
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unsigned int size)
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static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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PREPPCIState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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return pci_data_read(phb->bus, PPC_PCIIO_config(addr), size);
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return pci_data_read(phb->bus, raven_pci_io_config(addr), size);
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}
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static const MemoryRegionOps PPC_PCIIO_ops = {
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.read = ppc_pci_io_read,
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.write = ppc_pci_io_write,
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static const MemoryRegionOps raven_pci_io_ops = {
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.read = raven_pci_io_read,
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.write = raven_pci_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static uint64_t ppc_intack_read(void *opaque, hwaddr addr,
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unsigned int size)
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static uint64_t raven_intack_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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return pic_read_irq(isa_pic);
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}
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static const MemoryRegionOps PPC_intack_ops = {
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.read = ppc_intack_read,
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static const MemoryRegionOps raven_intack_ops = {
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.read = raven_intack_read,
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.valid = {
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.max_access_size = 1,
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},
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};
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static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
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static inline hwaddr raven_io_address(PREPPCIState *s,
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hwaddr addr)
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{
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if (s->contiguous_map == 0) {
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/* 64 KB contiguous space for IOs */
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addr &= 0xFFFF;
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} else {
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/* 8 MB non-contiguous space for IOs */
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addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
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}
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/* FIXME: handle endianness switch */
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return addr;
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}
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static uint64_t raven_io_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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PREPPCIState *s = opaque;
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uint8_t buf[4];
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addr = raven_io_address(s, addr);
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address_space_read(&s->pci_io_as, addr + 0x80000000, buf, size);
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if (size == 1) {
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return buf[0];
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} else if (size == 2) {
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return lduw_p(buf);
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} else if (size == 4) {
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return ldl_p(buf);
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} else {
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g_assert_not_reached();
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}
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}
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static void raven_io_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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PREPPCIState *s = opaque;
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uint8_t buf[4];
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addr = raven_io_address(s, addr);
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if (size == 1) {
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buf[0] = val;
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} else if (size == 2) {
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stw_p(buf, val);
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} else if (size == 4) {
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stl_p(buf, val);
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} else {
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g_assert_not_reached();
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}
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address_space_write(&s->pci_io_as, addr + 0x80000000, buf, size);
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}
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static const MemoryRegionOps raven_io_ops = {
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.read = raven_io_read,
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.write = raven_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl.max_access_size = 4,
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.valid.unaligned = true,
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};
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static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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return (irq_num + (pci_dev->devfn >> 3)) & 1;
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}
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static void prep_set_irq(void *opaque, int irq_num, int level)
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static void raven_set_irq(void *opaque, int irq_num, int level)
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{
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qemu_irq *pic = opaque;
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qemu_set_irq(pic[irq_num] , level);
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}
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static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
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int devfn)
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{
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PREPPCIState *s = opaque;
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return &s->bm_as;
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}
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static void raven_change_gpio(void *opaque, int n, int level)
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{
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PREPPCIState *s = opaque;
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s->contiguous_map = level;
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}
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static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
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{
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SysBusDevice *dev = SYS_BUS_DEVICE(d);
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@ -127,29 +217,30 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
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MemoryRegion *address_space_mem = get_system_memory();
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int i;
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isa_mem_base = 0xc0000000;
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for (i = 0; i < PCI_NUM_PINS; i++) {
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sysbus_init_irq(dev, &s->irq[i]);
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}
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pci_bus_irqs(&s->pci_bus, prep_set_irq, prep_map_irq, s->irq, PCI_NUM_PINS);
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qdev_init_gpio_in(d, raven_change_gpio, 1);
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, s,
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"pci-conf-idx", 1);
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sysbus_add_io(dev, 0xcf8, &h->conf_mem);
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sysbus_init_ioports(&h->busdev, 0xcf8, 1);
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pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s->irq,
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PCI_NUM_PINS);
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memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_be_ops, s,
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"pci-conf-data", 1);
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sysbus_add_io(dev, 0xcfc, &h->data_mem);
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sysbus_init_ioports(&h->busdev, 0xcfc, 1);
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
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"pci-conf-idx", 4);
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memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
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memory_region_init_io(&h->mmcfg, OBJECT(s), &PPC_PCIIO_ops, s, "pciio", 0x00400000);
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memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
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"pci-conf-data", 4);
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memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
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memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
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"pciio", 0x00400000);
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memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
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memory_region_init_io(&s->intack, OBJECT(s), &PPC_intack_ops, s, "pci-intack", 1);
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memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->intack);
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memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,
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"pci-intack", 1);
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memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
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/* TODO Remove once realize propagates to child devices. */
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object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
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@ -160,11 +251,36 @@ static void raven_pcihost_initfn(Object *obj)
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *address_space_io = get_system_io();
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DeviceState *pci_dev;
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memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
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memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
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"pci-io-non-contiguous", 0x00800000);
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/* Open Hack'Ware hack: real size should be only 0x3f000000 bytes */
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memory_region_init(&s->pci_memory, obj, "pci-memory",
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0x3f000000 + 0xc0000000ULL);
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address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
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/* CPU address space */
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memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
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memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
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&s->pci_io_non_contiguous, 1);
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memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
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pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
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address_space_mem, address_space_io, 0, TYPE_PCI_BUS);
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&s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
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/* Bus master address space */
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memory_region_init(&s->bm, obj, "bm-raven", UINT32_MAX);
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memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
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&s->pci_memory, 0,
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memory_region_size(&s->pci_memory));
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memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
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get_system_memory(), 0, 0x80000000);
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memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias);
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memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
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address_space_init(&s->bm_as, &s->bm, "raven-bm");
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pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s);
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h->bus = &s->pci_bus;
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object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
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103
hw/ppc/prep.c
103
hw/ppc/prep.c
@ -185,6 +185,7 @@ typedef struct sysctrl_t {
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uint8_t state;
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uint8_t syscontrol;
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int contiguous_map;
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qemu_irq contiguous_map_irq;
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int endian;
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} sysctrl_t;
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@ -253,6 +254,7 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
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case 0x0850:
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/* I/O map type register */
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sysctrl->contiguous_map = val & 0x01;
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qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
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break;
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default:
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printf("ERROR: unaffected IO port write: %04" PRIx32
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@ -327,91 +329,6 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
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return retval;
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}
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static inline hwaddr prep_IO_address(sysctrl_t *sysctrl,
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hwaddr addr)
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{
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if (sysctrl->contiguous_map == 0) {
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/* 64 KB contiguous space for IOs */
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addr &= 0xFFFF;
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} else {
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/* 8 MB non-contiguous space for IOs */
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addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
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}
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return addr;
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}
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static void PPC_prep_io_writeb (void *opaque, hwaddr addr,
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uint32_t value)
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{
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sysctrl_t *sysctrl = opaque;
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addr = prep_IO_address(sysctrl, addr);
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cpu_outb(addr, value);
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}
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static uint32_t PPC_prep_io_readb (void *opaque, hwaddr addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t ret;
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addr = prep_IO_address(sysctrl, addr);
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ret = cpu_inb(addr);
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return ret;
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}
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static void PPC_prep_io_writew (void *opaque, hwaddr addr,
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uint32_t value)
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{
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sysctrl_t *sysctrl = opaque;
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addr = prep_IO_address(sysctrl, addr);
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PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
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cpu_outw(addr, value);
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}
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static uint32_t PPC_prep_io_readw (void *opaque, hwaddr addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t ret;
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addr = prep_IO_address(sysctrl, addr);
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ret = cpu_inw(addr);
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PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
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return ret;
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}
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static void PPC_prep_io_writel (void *opaque, hwaddr addr,
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uint32_t value)
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{
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sysctrl_t *sysctrl = opaque;
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addr = prep_IO_address(sysctrl, addr);
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PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
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cpu_outl(addr, value);
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}
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static uint32_t PPC_prep_io_readl (void *opaque, hwaddr addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t ret;
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addr = prep_IO_address(sysctrl, addr);
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ret = cpu_inl(addr);
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PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
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return ret;
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}
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static const MemoryRegionOps PPC_prep_io_ops = {
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.old_mmio = {
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.read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl },
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.write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel },
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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#define NVRAM_SIZE 0x2000
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@ -458,13 +375,13 @@ static void ppc_prep_init(QEMUMachineInitArgs *args)
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CPUPPCState *env = NULL;
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nvram_t nvram;
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M48t59State *m48t59;
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MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1);
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PortioList *port_list = g_new(PortioList, 1);
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#if 0
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MemoryRegion *xcsr = g_new(MemoryRegion, 1);
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#endif
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int linux_boot, i, nb_nics1;
|
||||
MemoryRegion *ram = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *vga = g_new(MemoryRegion, 1);
|
||||
uint32_t kernel_base, initrd_base;
|
||||
long kernel_size, initrd_size;
|
||||
DeviceState *dev;
|
||||
@ -567,6 +484,7 @@ static void ppc_prep_init(QEMUMachineInitArgs *args)
|
||||
fprintf(stderr, "Couldn't create PCI host controller.\n");
|
||||
exit(1);
|
||||
}
|
||||
sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
|
||||
|
||||
/* PCI -> ISA bridge */
|
||||
pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
|
||||
@ -587,13 +505,16 @@ static void ppc_prep_init(QEMUMachineInitArgs *args)
|
||||
qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */
|
||||
qdev_init_nofail(dev);
|
||||
|
||||
/* Register 8 MB of ISA IO space (needed for non-contiguous map) */
|
||||
memory_region_init_io(PPC_io_memory, NULL, &PPC_prep_io_ops, sysctrl,
|
||||
"ppc-io", 0x00800000);
|
||||
memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory);
|
||||
|
||||
/* init basic PC hardware */
|
||||
pci_vga_init(pci_bus);
|
||||
/* Open Hack'Ware hack: PCI BAR#0 is programmed to 0xf0000000.
|
||||
* While bios will access framebuffer at 0xf0000000, real physical
|
||||
* address is 0xf0000000 + 0xc0000000 (PCI memory base).
|
||||
* Alias the wrong memory accesses to the right place.
|
||||
*/
|
||||
memory_region_init_alias(vga, NULL, "vga-alias", pci_address_space(pci),
|
||||
0xf0000000, 0x1000000);
|
||||
memory_region_add_subregion_overlap(sysmem, 0xf0000000, vga, 10);
|
||||
|
||||
nb_nics1 = nb_nics;
|
||||
if (nb_nics1 > NE2000_NB_MAX)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user