From 49a4e21251d89cdf9db8662a0d7138831f85d427 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Mon, 17 Mar 2014 23:00:19 +0100 Subject: [PATCH 1/7] raven: Rename intack region to pci_intack MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Regions added subsequently will also have the pci_ prefix. Signed-off-by: Hervé Poussineau Signed-off-by: Andreas Färber --- hw/pci-host/prep.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index 94fdffa777..84d50ca22a 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -52,9 +52,9 @@ typedef struct RavenPCIState { typedef struct PRePPCIState { PCIHostState parent_obj; - MemoryRegion intack; qemu_irq irq[PCI_NUM_PINS]; PCIBus pci_bus; + MemoryRegion pci_intack; RavenPCIState pci_dev; } PREPPCIState; @@ -148,8 +148,9 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp) memory_region_init_io(&h->mmcfg, OBJECT(s), &PPC_PCIIO_ops, s, "pciio", 0x00400000); memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg); - memory_region_init_io(&s->intack, OBJECT(s), &PPC_intack_ops, s, "pci-intack", 1); - memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->intack); + memory_region_init_io(&s->pci_intack, OBJECT(s), &PPC_intack_ops, s, + "pci-intack", 1); + memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack); /* TODO Remove once realize propagates to child devices. */ object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp); From 9a1839164c9c8f06f4645e8207d7faee771ec78e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Mon, 17 Mar 2014 23:00:20 +0100 Subject: [PATCH 2/7] raven: Implement non-contiguous I/O region MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove now duplicated code from prep board. Signed-off-by: Hervé Poussineau Signed-off-by: Andreas Färber --- hw/pci-host/prep.c | 85 +++++++++++++++++++++++++++++++++++++++++ hw/ppc/prep.c | 94 ++-------------------------------------------- 2 files changed, 88 insertions(+), 91 deletions(-) diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index 84d50ca22a..629735eeda 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -54,8 +54,12 @@ typedef struct PRePPCIState { qemu_irq irq[PCI_NUM_PINS]; PCIBus pci_bus; + AddressSpace pci_io_as; + MemoryRegion pci_io_non_contiguous; MemoryRegion pci_intack; RavenPCIState pci_dev; + + int contiguous_map; } PREPPCIState; #define BIOS_SIZE (1024 * 1024) @@ -107,6 +111,71 @@ static const MemoryRegionOps PPC_intack_ops = { }, }; +static inline hwaddr raven_io_address(PREPPCIState *s, + hwaddr addr) +{ + if (s->contiguous_map == 0) { + /* 64 KB contiguous space for IOs */ + addr &= 0xFFFF; + } else { + /* 8 MB non-contiguous space for IOs */ + addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); + } + + /* FIXME: handle endianness switch */ + + return addr; +} + +static uint64_t raven_io_read(void *opaque, hwaddr addr, + unsigned int size) +{ + PREPPCIState *s = opaque; + uint8_t buf[4]; + + addr = raven_io_address(s, addr); + address_space_read(&s->pci_io_as, addr, buf, size); + + if (size == 1) { + return buf[0]; + } else if (size == 2) { + return lduw_p(buf); + } else if (size == 4) { + return ldl_p(buf); + } else { + g_assert_not_reached(); + } +} + +static void raven_io_write(void *opaque, hwaddr addr, + uint64_t val, unsigned int size) +{ + PREPPCIState *s = opaque; + uint8_t buf[4]; + + addr = raven_io_address(s, addr); + + if (size == 1) { + buf[0] = val; + } else if (size == 2) { + stw_p(buf, val); + } else if (size == 4) { + stl_p(buf, val); + } else { + g_assert_not_reached(); + } + + address_space_write(&s->pci_io_as, addr, buf, size); +} + +static const MemoryRegionOps raven_io_ops = { + .read = raven_io_read, + .write = raven_io_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl.max_access_size = 4, + .valid.unaligned = true, +}; + static int prep_map_irq(PCIDevice *pci_dev, int irq_num) { return (irq_num + (pci_dev->devfn >> 3)) & 1; @@ -119,6 +188,13 @@ static void prep_set_irq(void *opaque, int irq_num, int level) qemu_set_irq(pic[irq_num] , level); } +static void raven_change_gpio(void *opaque, int n, int level) +{ + PREPPCIState *s = opaque; + + s->contiguous_map = level; +} + static void raven_pcihost_realizefn(DeviceState *d, Error **errp) { SysBusDevice *dev = SYS_BUS_DEVICE(d); @@ -133,6 +209,8 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp) sysbus_init_irq(dev, &s->irq[i]); } + qdev_init_gpio_in(d, raven_change_gpio, 1); + pci_bus_irqs(&s->pci_bus, prep_set_irq, prep_map_irq, s->irq, PCI_NUM_PINS); memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, s, @@ -164,6 +242,13 @@ static void raven_pcihost_initfn(Object *obj) MemoryRegion *address_space_io = get_system_io(); DeviceState *pci_dev; + memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s, + "pci-io-non-contiguous", 0x00800000); + address_space_init(&s->pci_io_as, get_system_io(), "raven-io"); + + /* CPU address space */ + memory_region_add_subregion_overlap(address_space_mem, 0x80000000, + &s->pci_io_non_contiguous, 1); pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL, address_space_mem, address_space_io, 0, TYPE_PCI_BUS); h->bus = &s->pci_bus; diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index 81e13cb4ac..035b5b2f86 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -185,6 +185,7 @@ typedef struct sysctrl_t { uint8_t state; uint8_t syscontrol; int contiguous_map; + qemu_irq contiguous_map_irq; int endian; } sysctrl_t; @@ -253,6 +254,7 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) case 0x0850: /* I/O map type register */ sysctrl->contiguous_map = val & 0x01; + qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map); break; default: printf("ERROR: unaffected IO port write: %04" PRIx32 @@ -327,91 +329,6 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) return retval; } -static inline hwaddr prep_IO_address(sysctrl_t *sysctrl, - hwaddr addr) -{ - if (sysctrl->contiguous_map == 0) { - /* 64 KB contiguous space for IOs */ - addr &= 0xFFFF; - } else { - /* 8 MB non-contiguous space for IOs */ - addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); - } - - return addr; -} - -static void PPC_prep_io_writeb (void *opaque, hwaddr addr, - uint32_t value) -{ - sysctrl_t *sysctrl = opaque; - - addr = prep_IO_address(sysctrl, addr); - cpu_outb(addr, value); -} - -static uint32_t PPC_prep_io_readb (void *opaque, hwaddr addr) -{ - sysctrl_t *sysctrl = opaque; - uint32_t ret; - - addr = prep_IO_address(sysctrl, addr); - ret = cpu_inb(addr); - - return ret; -} - -static void PPC_prep_io_writew (void *opaque, hwaddr addr, - uint32_t value) -{ - sysctrl_t *sysctrl = opaque; - - addr = prep_IO_address(sysctrl, addr); - PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); - cpu_outw(addr, value); -} - -static uint32_t PPC_prep_io_readw (void *opaque, hwaddr addr) -{ - sysctrl_t *sysctrl = opaque; - uint32_t ret; - - addr = prep_IO_address(sysctrl, addr); - ret = cpu_inw(addr); - PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); - - return ret; -} - -static void PPC_prep_io_writel (void *opaque, hwaddr addr, - uint32_t value) -{ - sysctrl_t *sysctrl = opaque; - - addr = prep_IO_address(sysctrl, addr); - PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); - cpu_outl(addr, value); -} - -static uint32_t PPC_prep_io_readl (void *opaque, hwaddr addr) -{ - sysctrl_t *sysctrl = opaque; - uint32_t ret; - - addr = prep_IO_address(sysctrl, addr); - ret = cpu_inl(addr); - PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); - - return ret; -} - -static const MemoryRegionOps PPC_prep_io_ops = { - .old_mmio = { - .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl }, - .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel }, - }, - .endianness = DEVICE_NATIVE_ENDIAN, -}; #define NVRAM_SIZE 0x2000 @@ -458,7 +375,6 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) CPUPPCState *env = NULL; nvram_t nvram; M48t59State *m48t59; - MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1); PortioList *port_list = g_new(PortioList, 1); #if 0 MemoryRegion *xcsr = g_new(MemoryRegion, 1); @@ -567,6 +483,7 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) fprintf(stderr, "Couldn't create PCI host controller.\n"); exit(1); } + sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0); /* PCI -> ISA bridge */ pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); @@ -587,11 +504,6 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */ qdev_init_nofail(dev); - /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ - memory_region_init_io(PPC_io_memory, NULL, &PPC_prep_io_ops, sysctrl, - "ppc-io", 0x00800000); - memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory); - /* init basic PC hardware */ pci_vga_init(pci_bus); From 1ae1dc5ba241a6dd22b7359ec1b2d21dd8e66f5b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Mon, 17 Mar 2014 23:00:21 +0100 Subject: [PATCH 3/7] raven: Set a correct PCI I/O memory region MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI I/O region is 0x3f800000 bytes starting at 0x80000000. Do not use global QEMU I/O region, which is only 64KB. Signed-off-by: Hervé Poussineau Signed-off-by: Andreas Färber --- hw/pci-host/prep.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index 629735eeda..6463b6d424 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -55,6 +55,7 @@ typedef struct PRePPCIState { qemu_irq irq[PCI_NUM_PINS]; PCIBus pci_bus; AddressSpace pci_io_as; + MemoryRegion pci_io; MemoryRegion pci_io_non_contiguous; MemoryRegion pci_intack; RavenPCIState pci_dev; @@ -134,7 +135,7 @@ static uint64_t raven_io_read(void *opaque, hwaddr addr, uint8_t buf[4]; addr = raven_io_address(s, addr); - address_space_read(&s->pci_io_as, addr, buf, size); + address_space_read(&s->pci_io_as, addr + 0x80000000, buf, size); if (size == 1) { return buf[0]; @@ -165,7 +166,7 @@ static void raven_io_write(void *opaque, hwaddr addr, g_assert_not_reached(); } - address_space_write(&s->pci_io_as, addr, buf, size); + address_space_write(&s->pci_io_as, addr + 0x80000000, buf, size); } static const MemoryRegionOps raven_io_ops = { @@ -215,13 +216,11 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp) memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, s, "pci-conf-idx", 1); - sysbus_add_io(dev, 0xcf8, &h->conf_mem); - sysbus_init_ioports(&h->busdev, 0xcf8, 1); + memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem); memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_be_ops, s, "pci-conf-data", 1); - sysbus_add_io(dev, 0xcfc, &h->data_mem); - sysbus_init_ioports(&h->busdev, 0xcfc, 1); + memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem); memory_region_init_io(&h->mmcfg, OBJECT(s), &PPC_PCIIO_ops, s, "pciio", 0x00400000); memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg); @@ -239,18 +238,20 @@ static void raven_pcihost_initfn(Object *obj) PCIHostState *h = PCI_HOST_BRIDGE(obj); PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj); MemoryRegion *address_space_mem = get_system_memory(); - MemoryRegion *address_space_io = get_system_io(); DeviceState *pci_dev; + memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000); memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s, "pci-io-non-contiguous", 0x00800000); - address_space_init(&s->pci_io_as, get_system_io(), "raven-io"); + address_space_init(&s->pci_io_as, &s->pci_io, "raven-io"); /* CPU address space */ + memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io); memory_region_add_subregion_overlap(address_space_mem, 0x80000000, &s->pci_io_non_contiguous, 1); pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL, - address_space_mem, address_space_io, 0, TYPE_PCI_BUS); + address_space_mem, &s->pci_io, 0, TYPE_PCI_BUS); + h->bus = &s->pci_bus; object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE); From 1fe9e2626f00b237a7e79d3eba4891da1bff6671 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Mon, 17 Mar 2014 23:00:22 +0100 Subject: [PATCH 4/7] raven: Set a correct PCI memory region MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI memory region is 0x3f000000 bytes starting at 0xc0000000. However, keep compatibility with Open Hack'Ware expectations by adding a hack for Open Hack'Ware display. Signed-off-by: Hervé Poussineau Signed-off-by: Andreas Färber --- hw/pci-host/prep.c | 9 ++++++--- hw/ppc/prep.c | 9 +++++++++ 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index 6463b6d424..7f23a11881 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -57,6 +57,7 @@ typedef struct PRePPCIState { AddressSpace pci_io_as; MemoryRegion pci_io; MemoryRegion pci_io_non_contiguous; + MemoryRegion pci_memory; MemoryRegion pci_intack; RavenPCIState pci_dev; @@ -204,8 +205,6 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp) MemoryRegion *address_space_mem = get_system_memory(); int i; - isa_mem_base = 0xc0000000; - for (i = 0; i < PCI_NUM_PINS; i++) { sysbus_init_irq(dev, &s->irq[i]); } @@ -243,14 +242,18 @@ static void raven_pcihost_initfn(Object *obj) memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000); memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s, "pci-io-non-contiguous", 0x00800000); + /* Open Hack'Ware hack: real size should be only 0x3f000000 bytes */ + memory_region_init(&s->pci_memory, obj, "pci-memory", + 0x3f000000 + 0xc0000000ULL); address_space_init(&s->pci_io_as, &s->pci_io, "raven-io"); /* CPU address space */ memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io); memory_region_add_subregion_overlap(address_space_mem, 0x80000000, &s->pci_io_non_contiguous, 1); + memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory); pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL, - address_space_mem, &s->pci_io, 0, TYPE_PCI_BUS); + &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS); h->bus = &s->pci_bus; diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index 035b5b2f86..e2436512f7 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -381,6 +381,7 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) #endif int linux_boot, i, nb_nics1; MemoryRegion *ram = g_new(MemoryRegion, 1); + MemoryRegion *vga = g_new(MemoryRegion, 1); uint32_t kernel_base, initrd_base; long kernel_size, initrd_size; DeviceState *dev; @@ -506,6 +507,14 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) /* init basic PC hardware */ pci_vga_init(pci_bus); + /* Open Hack'Ware hack: PCI BAR#0 is programmed to 0xf0000000. + * While bios will access framebuffer at 0xf0000000, real physical + * address is 0xf0000000 + 0xc0000000 (PCI memory base). + * Alias the wrong memory accesses to the right place. + */ + memory_region_init_alias(vga, NULL, "vga-alias", pci_address_space(pci), + 0xf0000000, 0x1000000); + memory_region_add_subregion_overlap(sysmem, 0xf0000000, vga, 10); nb_nics1 = nb_nics; if (nb_nics1 > NE2000_NB_MAX) From d16644ec4ce1da5db24dd0a1618d814feaaf8ccb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Mon, 17 Mar 2014 23:00:23 +0100 Subject: [PATCH 5/7] raven: Add PCI bus mastering address space MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This has been tested on Linux 2.4/PPC with the lsi53c895a SCSI adapter. Signed-off-by: Hervé Poussineau Signed-off-by: Andreas Färber --- hw/pci-host/prep.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index 7f23a11881..8109625324 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -59,6 +59,10 @@ typedef struct PRePPCIState { MemoryRegion pci_io_non_contiguous; MemoryRegion pci_memory; MemoryRegion pci_intack; + MemoryRegion bm; + MemoryRegion bm_ram_alias; + MemoryRegion bm_pci_memory_alias; + AddressSpace bm_as; RavenPCIState pci_dev; int contiguous_map; @@ -190,6 +194,14 @@ static void prep_set_irq(void *opaque, int irq_num, int level) qemu_set_irq(pic[irq_num] , level); } +static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque, + int devfn) +{ + PREPPCIState *s = opaque; + + return &s->bm_as; +} + static void raven_change_gpio(void *opaque, int n, int level) { PREPPCIState *s = opaque; @@ -255,6 +267,18 @@ static void raven_pcihost_initfn(Object *obj) pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL, &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS); + /* Bus master address space */ + memory_region_init(&s->bm, obj, "bm-raven", UINT32_MAX); + memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory", + &s->pci_memory, 0, + memory_region_size(&s->pci_memory)); + memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system", + get_system_memory(), 0, 0x80000000); + memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias); + memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias); + address_space_init(&s->bm_as, &s->bm, "raven-bm"); + pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s); + h->bus = &s->pci_bus; object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE); From 2403837e67eca7eb5dfdadda25cdd38ef2dc9ad0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Mon, 17 Mar 2014 23:00:24 +0100 Subject: [PATCH 6/7] raven: Fix PCI bus accesses with size > 1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Hervé Poussineau Reviewed-by: Artyom Tarasenko Signed-off-by: Andreas Färber --- hw/pci-host/prep.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index 8109625324..e452a91cb1 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -225,12 +225,12 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp) pci_bus_irqs(&s->pci_bus, prep_set_irq, prep_map_irq, s->irq, PCI_NUM_PINS); - memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, s, - "pci-conf-idx", 1); + memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s, + "pci-conf-idx", 4); memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem); - memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_be_ops, s, - "pci-conf-data", 1); + memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s, + "pci-conf-data", 4); memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem); memory_region_init_io(&h->mmcfg, OBJECT(s), &PPC_PCIIO_ops, s, "pciio", 0x00400000); From f205da688b3dc8f6f54220b6997ed5b910afcc54 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Mon, 17 Mar 2014 23:00:25 +0100 Subject: [PATCH 7/7] raven: Use raven_ for all function prefixes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Hervé Poussineau Signed-off-by: Andreas Färber --- hw/pci-host/prep.c | 40 +++++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index e452a91cb1..d3e746c0f8 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -70,7 +70,7 @@ typedef struct PRePPCIState { #define BIOS_SIZE (1024 * 1024) -static inline uint32_t PPC_PCIIO_config(hwaddr addr) +static inline uint32_t raven_pci_io_config(hwaddr addr) { int i; @@ -82,36 +82,36 @@ static inline uint32_t PPC_PCIIO_config(hwaddr addr) return (addr & 0x7ff) | (i << 11); } -static void ppc_pci_io_write(void *opaque, hwaddr addr, - uint64_t val, unsigned int size) +static void raven_pci_io_write(void *opaque, hwaddr addr, + uint64_t val, unsigned int size) { PREPPCIState *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); - pci_data_write(phb->bus, PPC_PCIIO_config(addr), val, size); + pci_data_write(phb->bus, raven_pci_io_config(addr), val, size); } -static uint64_t ppc_pci_io_read(void *opaque, hwaddr addr, - unsigned int size) +static uint64_t raven_pci_io_read(void *opaque, hwaddr addr, + unsigned int size) { PREPPCIState *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); - return pci_data_read(phb->bus, PPC_PCIIO_config(addr), size); + return pci_data_read(phb->bus, raven_pci_io_config(addr), size); } -static const MemoryRegionOps PPC_PCIIO_ops = { - .read = ppc_pci_io_read, - .write = ppc_pci_io_write, +static const MemoryRegionOps raven_pci_io_ops = { + .read = raven_pci_io_read, + .write = raven_pci_io_write, .endianness = DEVICE_LITTLE_ENDIAN, }; -static uint64_t ppc_intack_read(void *opaque, hwaddr addr, - unsigned int size) +static uint64_t raven_intack_read(void *opaque, hwaddr addr, + unsigned int size) { return pic_read_irq(isa_pic); } -static const MemoryRegionOps PPC_intack_ops = { - .read = ppc_intack_read, +static const MemoryRegionOps raven_intack_ops = { + .read = raven_intack_read, .valid = { .max_access_size = 1, }, @@ -182,12 +182,12 @@ static const MemoryRegionOps raven_io_ops = { .valid.unaligned = true, }; -static int prep_map_irq(PCIDevice *pci_dev, int irq_num) +static int raven_map_irq(PCIDevice *pci_dev, int irq_num) { return (irq_num + (pci_dev->devfn >> 3)) & 1; } -static void prep_set_irq(void *opaque, int irq_num, int level) +static void raven_set_irq(void *opaque, int irq_num, int level) { qemu_irq *pic = opaque; @@ -223,7 +223,8 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp) qdev_init_gpio_in(d, raven_change_gpio, 1); - pci_bus_irqs(&s->pci_bus, prep_set_irq, prep_map_irq, s->irq, PCI_NUM_PINS); + pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s->irq, + PCI_NUM_PINS); memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s, "pci-conf-idx", 4); @@ -233,10 +234,11 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp) "pci-conf-data", 4); memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem); - memory_region_init_io(&h->mmcfg, OBJECT(s), &PPC_PCIIO_ops, s, "pciio", 0x00400000); + memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s, + "pciio", 0x00400000); memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg); - memory_region_init_io(&s->pci_intack, OBJECT(s), &PPC_intack_ops, s, + memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s, "pci-intack", 1); memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);