2004-05-27 02:55:16 +04:00
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/*
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2007-10-29 02:42:18 +03:00
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* QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
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2007-09-17 01:08:06 +04:00
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*
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2007-03-30 13:38:04 +04:00
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* Copyright (c) 2004-2007 Fabrice Bellard
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2007-10-29 02:42:18 +03:00
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* Copyright (c) 2007 Jocelyn Mayer
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2007-09-17 01:08:06 +04:00
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*
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2004-05-27 02:55:16 +04:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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2010-02-09 19:37:03 +03:00
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*
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* PCI bus layout on a real G5 (U3 based):
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*
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* 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
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* 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
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* 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
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* 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
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* 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
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* 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
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* 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
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* 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
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* 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
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* 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
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* 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
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* 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
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* 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
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* 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
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* 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
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* 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
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* 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
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* 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
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* 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
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* 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
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*
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2004-05-27 02:55:16 +04:00
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*/
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2007-11-17 20:14:51 +03:00
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#include "hw.h"
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#include "ppc.h"
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2007-10-29 02:42:18 +03:00
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#include "ppc_mac.h"
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2011-09-04 12:41:15 +04:00
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#include "adb.h"
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2009-01-30 23:39:32 +03:00
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#include "mac_dbdma.h"
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2007-11-17 20:14:51 +03:00
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#include "nvram.h"
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2012-12-12 16:24:50 +04:00
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#include "pci/pci.h"
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2012-10-24 10:43:34 +04:00
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#include "net/net.h"
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2012-12-17 21:20:04 +04:00
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#include "sysemu/sysemu.h"
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2007-11-17 20:14:51 +03:00
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#include "boards.h"
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2009-02-08 18:59:36 +03:00
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#include "fw_cfg.h"
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2009-01-12 20:40:23 +03:00
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#include "escc.h"
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2009-03-02 19:42:04 +03:00
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#include "openpic.h"
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2009-08-20 17:22:20 +04:00
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#include "ide.h"
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2009-09-20 18:58:02 +04:00
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#include "loader.h"
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#include "elf.h"
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2012-12-17 21:20:04 +04:00
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#include "sysemu/kvm.h"
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2010-02-09 19:37:05 +03:00
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#include "kvm_ppc.h"
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2010-02-09 19:37:08 +03:00
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#include "hw/usb.h"
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2012-12-17 21:20:04 +04:00
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#include "sysemu/blockdev.h"
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2012-12-17 21:19:49 +04:00
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#include "exec/address-spaces.h"
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2012-12-08 08:17:14 +04:00
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#include "sysbus.h"
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2004-06-03 22:46:20 +04:00
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2007-12-02 07:51:10 +03:00
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#define MAX_IDE_BUS 2
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2009-02-08 18:59:36 +03:00
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#define CFG_ADDR 0xf0000510
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2007-12-02 07:51:10 +03:00
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2009-02-05 23:22:07 +03:00
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/* debug UniNorth */
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//#define DEBUG_UNIN
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#ifdef DEBUG_UNIN
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2009-05-13 21:53:17 +04:00
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#define UNIN_DPRINTF(fmt, ...) \
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do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
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2009-02-05 23:22:07 +03:00
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#else
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2009-05-13 21:53:17 +04:00
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#define UNIN_DPRINTF(fmt, ...)
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2009-02-05 23:22:07 +03:00
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#endif
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2005-06-05 19:11:17 +04:00
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/* UniN device */
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2012-10-23 14:30:10 +04:00
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static void unin_write(void *opaque, hwaddr addr, uint64_t value,
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2011-09-13 17:30:29 +04:00
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unsigned size)
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2005-06-05 19:11:17 +04:00
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{
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2011-09-13 17:30:29 +04:00
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UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value);
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2005-06-05 19:11:17 +04:00
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}
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2012-10-23 14:30:10 +04:00
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static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size)
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2005-06-05 19:11:17 +04:00
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{
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2009-02-05 23:22:07 +03:00
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uint32_t value;
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value = 0;
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UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value);
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return value;
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2005-06-05 19:11:17 +04:00
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}
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2011-09-13 17:30:29 +04:00
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static const MemoryRegionOps unin_ops = {
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.read = unin_read,
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.write = unin_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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2005-06-05 19:11:17 +04:00
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};
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2009-03-08 12:51:29 +03:00
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static int fw_cfg_boot_set(void *opaque, const char *boot_device)
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{
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fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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return 0;
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}
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2010-03-14 23:20:59 +03:00
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static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
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{
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return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
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}
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2012-10-23 14:30:10 +04:00
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static hwaddr round_page(hwaddr addr)
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2011-06-16 01:27:19 +04:00
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{
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return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
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}
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2012-02-08 06:03:33 +04:00
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static void ppc_core99_reset(void *opaque)
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{
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2012-05-04 19:30:25 +04:00
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PowerPCCPU *cpu = opaque;
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2012-02-08 06:03:33 +04:00
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2012-05-04 19:30:25 +04:00
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cpu_reset(CPU(cpu));
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2012-02-08 06:03:33 +04:00
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}
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2007-10-29 02:42:18 +03:00
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/* PowerPC Mac99 hardware initialisation */
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2012-10-16 00:22:02 +04:00
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static void ppc_core99_init(QEMUMachineInitArgs *args)
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2004-05-27 02:55:16 +04:00
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{
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2012-10-16 00:22:02 +04:00
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ram_addr_t ram_size = args->ram_size;
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const char *cpu_model = args->cpu_model;
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const char *kernel_filename = args->kernel_filename;
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const char *kernel_cmdline = args->kernel_cmdline;
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const char *initrd_filename = args->initrd_filename;
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const char *boot_device = args->boot_device;
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2012-05-04 19:29:07 +04:00
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PowerPCCPU *cpu = NULL;
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2012-03-14 04:38:23 +04:00
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CPUPPCState *env = NULL;
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2009-05-30 03:52:44 +04:00
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char *filename;
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2007-04-10 02:45:36 +04:00
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qemu_irq *pic, **openpic_irqs;
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2011-09-13 17:30:29 +04:00
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MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
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2012-12-08 08:17:14 +04:00
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int linux_boot, i, j, k;
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2011-09-13 17:30:29 +04:00
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MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
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2012-10-23 14:30:10 +04:00
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hwaddr kernel_base, initrd_base, cmdline_base = 0;
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2010-09-18 09:53:14 +04:00
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long kernel_size, initrd_size;
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2004-06-21 23:43:00 +04:00
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PCIBus *pci_bus;
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2007-10-29 02:42:18 +03:00
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MacIONVRAMState *nvr;
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2010-10-13 22:38:07 +04:00
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int bios_size;
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2011-08-08 17:09:17 +04:00
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MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem, *escc_mem;
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2011-08-24 22:37:05 +04:00
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MemoryRegion *escc_bar = g_new(MemoryRegion, 1);
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2011-08-08 17:09:17 +04:00
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MemoryRegion *ide_mem[3];
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2007-11-11 04:50:45 +03:00
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int ppc_boot_device;
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2009-08-28 17:47:03 +04:00
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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2009-02-08 18:59:36 +03:00
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void *fw_cfg;
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2009-01-30 23:39:32 +03:00
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void *dbdma;
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2010-02-09 19:37:02 +03:00
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int machine_arch;
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2012-12-08 08:17:14 +04:00
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SysBusDevice *s;
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DeviceState *dev;
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2004-06-21 23:43:00 +04:00
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2004-05-27 02:55:16 +04:00
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linux_boot = (kernel_filename != NULL);
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2005-11-22 02:33:12 +03:00
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/* init CPUs */
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2007-03-05 22:44:02 +03:00
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if (cpu_model == NULL)
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2009-12-20 02:22:26 +03:00
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#ifdef TARGET_PPC64
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cpu_model = "970fx";
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#else
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2009-02-09 22:03:02 +03:00
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cpu_model = "G4";
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2009-12-20 02:22:26 +03:00
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#endif
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2007-04-10 02:45:36 +04:00
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for (i = 0; i < smp_cpus; i++) {
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2012-05-04 19:29:07 +04:00
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cpu = cpu_ppc_init(cpu_model);
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if (cpu == NULL) {
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2007-11-10 18:15:54 +03:00
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fprintf(stderr, "Unable to find PowerPC CPU definition\n");
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exit(1);
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}
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2012-05-04 19:29:07 +04:00
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env = &cpu->env;
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2007-04-10 02:45:36 +04:00
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/* Set time-base frequency to 100 Mhz */
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cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
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2012-05-04 19:30:25 +04:00
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qemu_register_reset(ppc_core99_reset, cpu);
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2007-04-10 02:45:36 +04:00
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}
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2005-11-22 02:33:12 +03:00
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2004-05-27 02:55:16 +04:00
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/* allocate RAM */
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2011-12-20 17:59:12 +04:00
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memory_region_init_ram(ram, "ppc_core99.ram", ram_size);
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vmstate_register_ram_global(ram);
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2011-09-13 17:30:29 +04:00
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memory_region_add_subregion(get_system_memory(), 0, ram);
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2009-02-05 23:20:29 +03:00
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2004-05-27 02:55:16 +04:00
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/* allocate and load BIOS */
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2011-12-20 17:59:12 +04:00
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memory_region_init_ram(bios, "ppc_core99.bios", BIOS_SIZE);
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vmstate_register_ram_global(bios);
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2007-10-05 17:08:35 +04:00
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if (bios_name == NULL)
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2009-02-08 18:59:36 +03:00
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bios_name = PROM_FILENAME;
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2009-05-30 03:52:44 +04:00
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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2011-09-13 17:30:29 +04:00
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memory_region_set_readonly(bios, true);
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memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios);
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2009-02-08 18:59:36 +03:00
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/* Load OpenBIOS (ELF) */
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2009-05-30 03:52:44 +04:00
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if (filename) {
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2010-03-14 23:20:59 +03:00
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bios_size = load_elf(filename, NULL, NULL, NULL,
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NULL, NULL, 1, ELF_MACHINE, 0);
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2009-09-20 18:58:02 +04:00
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2011-08-21 07:09:37 +04:00
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g_free(filename);
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2009-05-30 03:52:44 +04:00
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} else {
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bios_size = -1;
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}
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2005-07-03 18:00:51 +04:00
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if (bios_size < 0 || bios_size > BIOS_SIZE) {
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2009-05-30 03:52:44 +04:00
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hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
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2004-05-27 02:55:16 +04:00
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exit(1);
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}
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2007-09-17 12:09:54 +04:00
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2004-06-21 20:55:53 +04:00
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if (linux_boot) {
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2009-03-08 12:51:29 +03:00
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uint64_t lowaddr = 0;
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2009-09-20 18:58:02 +04:00
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int bswap_needed;
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#ifdef BSWAP_NEEDED
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bswap_needed = 1;
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#else
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bswap_needed = 0;
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#endif
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2004-06-21 20:55:53 +04:00
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kernel_base = KERNEL_LOAD_ADDR;
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2009-03-08 12:51:29 +03:00
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2010-03-14 23:20:59 +03:00
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kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
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NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
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2009-03-08 12:51:29 +03:00
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if (kernel_size < 0)
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kernel_size = load_aout(kernel_filename, kernel_base,
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2009-09-20 18:58:02 +04:00
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ram_size - kernel_base, bswap_needed,
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TARGET_PAGE_SIZE);
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2009-03-08 12:51:29 +03:00
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if (kernel_size < 0)
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kernel_size = load_image_targphys(kernel_filename,
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kernel_base,
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ram_size - kernel_base);
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2004-06-21 20:55:53 +04:00
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if (kernel_size < 0) {
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2009-05-08 05:35:15 +04:00
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hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
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2004-06-21 20:55:53 +04:00
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exit(1);
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}
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/* load initrd */
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if (initrd_filename) {
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2011-06-16 01:27:19 +04:00
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initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
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2009-04-10 04:26:15 +04:00
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initrd_size = load_image_targphys(initrd_filename, initrd_base,
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ram_size - initrd_base);
|
2004-06-21 20:55:53 +04:00
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if (initrd_size < 0) {
|
2009-05-08 05:35:15 +04:00
|
|
|
hw_error("qemu: could not load initial ram disk '%s'\n",
|
|
|
|
initrd_filename);
|
2004-06-21 20:55:53 +04:00
|
|
|
exit(1);
|
|
|
|
}
|
2011-06-16 01:27:19 +04:00
|
|
|
cmdline_base = round_page(initrd_base + initrd_size);
|
2004-06-21 20:55:53 +04:00
|
|
|
} else {
|
|
|
|
initrd_base = 0;
|
|
|
|
initrd_size = 0;
|
2011-06-16 01:27:19 +04:00
|
|
|
cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
|
2004-06-21 20:55:53 +04:00
|
|
|
}
|
2007-10-31 04:54:04 +03:00
|
|
|
ppc_boot_device = 'm';
|
2004-06-21 20:55:53 +04:00
|
|
|
} else {
|
|
|
|
kernel_base = 0;
|
|
|
|
kernel_size = 0;
|
|
|
|
initrd_base = 0;
|
|
|
|
initrd_size = 0;
|
2007-11-11 04:50:45 +03:00
|
|
|
ppc_boot_device = '\0';
|
|
|
|
/* We consider that NewWorld PowerMac never have any floppy drive
|
|
|
|
* For now, OHW cannot boot from the network.
|
|
|
|
*/
|
2007-11-11 17:44:28 +03:00
|
|
|
for (i = 0; boot_device[i] != '\0'; i++) {
|
|
|
|
if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
|
|
|
|
ppc_boot_device = boot_device[i];
|
2007-11-11 04:50:45 +03:00
|
|
|
break;
|
2007-11-11 17:44:28 +03:00
|
|
|
}
|
2007-11-11 04:50:45 +03:00
|
|
|
}
|
|
|
|
if (ppc_boot_device == '\0') {
|
|
|
|
fprintf(stderr, "No valid boot device for Mac99 machine\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
2004-06-21 20:55:53 +04:00
|
|
|
}
|
2005-06-05 19:11:17 +04:00
|
|
|
|
2007-10-29 02:42:18 +03:00
|
|
|
/* Register 8 MB of ISA IO space */
|
2010-12-08 14:05:49 +03:00
|
|
|
isa_mmio_init(0xf2000000, 0x00800000);
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2007-10-29 02:42:18 +03:00
|
|
|
/* UniN init */
|
2011-09-13 17:30:29 +04:00
|
|
|
memory_region_init_io(unin_memory, &unin_ops, NULL, "unin", 0x1000);
|
|
|
|
memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory);
|
2007-03-30 13:38:04 +04:00
|
|
|
|
2011-08-21 07:09:37 +04:00
|
|
|
openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
|
2007-10-29 02:42:18 +03:00
|
|
|
openpic_irqs[0] =
|
2011-08-21 07:09:37 +04:00
|
|
|
g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
|
2007-10-29 02:42:18 +03:00
|
|
|
for (i = 0; i < smp_cpus; i++) {
|
|
|
|
/* Mac99 IRQ connection between OpenPIC outputs pins
|
|
|
|
* and PowerPC input pins
|
|
|
|
*/
|
|
|
|
switch (PPC_INPUT(env)) {
|
|
|
|
case PPC_FLAGS_INPUT_6xx:
|
|
|
|
openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
|
|
|
|
openpic_irqs[i][OPENPIC_OUTPUT_INT] =
|
|
|
|
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
|
|
|
|
openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
|
|
|
|
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
|
|
|
|
openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
|
|
|
|
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
|
|
|
|
/* Not connected ? */
|
|
|
|
openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
|
|
|
|
/* Check this */
|
|
|
|
openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
|
|
|
|
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
|
|
|
|
break;
|
2007-10-03 05:05:39 +04:00
|
|
|
#if defined(TARGET_PPC64)
|
2007-10-29 02:42:18 +03:00
|
|
|
case PPC_FLAGS_INPUT_970:
|
|
|
|
openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
|
|
|
|
openpic_irqs[i][OPENPIC_OUTPUT_INT] =
|
|
|
|
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
|
|
|
|
openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
|
|
|
|
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
|
|
|
|
openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
|
|
|
|
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
|
|
|
|
/* Not connected ? */
|
|
|
|
openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
|
|
|
|
/* Check this */
|
|
|
|
openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
|
|
|
|
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
|
|
|
|
break;
|
2007-10-03 05:05:39 +04:00
|
|
|
#endif /* defined(TARGET_PPC64) */
|
2007-10-29 02:42:18 +03:00
|
|
|
default:
|
2009-05-08 05:35:15 +04:00
|
|
|
hw_error("Bus model not supported on mac99 machine\n");
|
2007-10-29 02:42:18 +03:00
|
|
|
exit(1);
|
2005-06-05 19:11:17 +04:00
|
|
|
}
|
2007-10-29 02:42:18 +03:00
|
|
|
}
|
2012-12-08 08:17:14 +04:00
|
|
|
|
|
|
|
pic = g_new(qemu_irq, 64);
|
|
|
|
|
|
|
|
dev = qdev_create(NULL, "openpic");
|
|
|
|
qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN);
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 05:47:33 +04:00
|
|
|
s = SYS_BUS_DEVICE(dev);
|
2012-12-08 08:17:14 +04:00
|
|
|
pic_mem = s->mmio[0].memory;
|
|
|
|
k = 0;
|
|
|
|
for (i = 0; i < smp_cpus; i++) {
|
|
|
|
for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
|
|
|
|
sysbus_connect_irq(s, k++, openpic_irqs[i][j]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < 64; i++) {
|
|
|
|
pic[i] = qdev_get_gpio_in(dev, i);
|
|
|
|
}
|
|
|
|
|
2010-02-09 19:37:02 +03:00
|
|
|
if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
|
|
|
|
/* 970 gets a U3 bus */
|
2011-08-08 17:09:04 +04:00
|
|
|
pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
|
2010-02-09 19:37:02 +03:00
|
|
|
machine_arch = ARCH_MAC99_U3;
|
|
|
|
} else {
|
2011-08-08 17:09:04 +04:00
|
|
|
pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io());
|
2010-02-09 19:37:02 +03:00
|
|
|
machine_arch = ARCH_MAC99;
|
|
|
|
}
|
2007-10-29 02:42:18 +03:00
|
|
|
/* init basic PC hardware */
|
2012-09-08 14:19:38 +04:00
|
|
|
pci_vga_init(pci_bus);
|
2007-11-24 05:56:36 +03:00
|
|
|
|
2011-09-30 17:29:12 +04:00
|
|
|
escc_mem = escc_init(0, pic[0x25], pic[0x24],
|
2011-08-08 17:09:17 +04:00
|
|
|
serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
|
2011-08-24 22:37:05 +04:00
|
|
|
memory_region_init_alias(escc_bar, "escc-bar",
|
|
|
|
escc_mem, 0, memory_region_size(escc_mem));
|
2009-01-13 22:47:10 +03:00
|
|
|
|
|
|
|
for(i = 0; i < nb_nics; i++)
|
2009-09-25 05:53:51 +04:00
|
|
|
pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
|
2009-01-13 22:47:10 +03:00
|
|
|
|
2011-04-03 15:32:46 +04:00
|
|
|
ide_drive_get(hd, MAX_IDE_BUS);
|
2011-08-08 17:09:17 +04:00
|
|
|
dbdma = DBDMA_init(&dbdma_mem);
|
2010-02-09 19:37:06 +03:00
|
|
|
|
|
|
|
/* We only emulate 2 out of 3 IDE controllers for now */
|
2011-08-08 17:09:17 +04:00
|
|
|
ide_mem[0] = NULL;
|
|
|
|
ide_mem[1] = pmac_ide_init(hd, pic[0x0d], dbdma, 0x16, pic[0x02]);
|
|
|
|
ide_mem[2] = pmac_ide_init(&hd[MAX_IDE_DEVS], pic[0x0e], dbdma, 0x1a, pic[0x02]);
|
2009-02-08 16:05:12 +03:00
|
|
|
|
2011-08-08 17:09:17 +04:00
|
|
|
cuda_init(&cuda_mem, pic[0x19]);
|
2007-11-24 05:56:36 +03:00
|
|
|
|
2007-10-29 02:42:18 +03:00
|
|
|
adb_kbd_init(&adb_bus);
|
|
|
|
adb_mouse_init(&adb_bus);
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2011-08-08 17:09:17 +04:00
|
|
|
macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem,
|
2011-08-24 22:37:05 +04:00
|
|
|
dbdma_mem, cuda_mem, NULL, 3, ide_mem, escc_bar);
|
2006-05-21 20:30:15 +04:00
|
|
|
|
2012-09-02 23:25:28 +04:00
|
|
|
if (usb_enabled(machine_arch == ARCH_MAC99_U3)) {
|
2012-03-07 18:06:32 +04:00
|
|
|
pci_create_simple(pci_bus, -1, "pci-ohci");
|
2012-09-02 23:25:28 +04:00
|
|
|
/* U3 needs to use USB for input because Linux doesn't support via-cuda
|
|
|
|
on PPC64 */
|
|
|
|
if (machine_arch == ARCH_MAC99_U3) {
|
|
|
|
usbdevice_create("keyboard");
|
|
|
|
usbdevice_create("mouse");
|
|
|
|
}
|
2010-02-09 19:37:08 +03:00
|
|
|
}
|
|
|
|
|
2004-06-21 20:55:53 +04:00
|
|
|
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
|
|
|
|
graphic_depth = 15;
|
2009-02-08 19:01:01 +03:00
|
|
|
|
2007-10-29 02:42:18 +03:00
|
|
|
/* The NewWorld NVRAM is not located in the MacIO device */
|
2011-08-08 17:09:17 +04:00
|
|
|
nvr = macio_nvram_init(0x2000, 1);
|
2007-10-29 02:42:18 +03:00
|
|
|
pmac_format_nvram_partition(nvr, 0x2000);
|
2011-08-08 17:09:17 +04:00
|
|
|
macio_nvram_setup_bar(nvr, get_system_memory(), 0xFFF04000);
|
2004-06-21 20:55:53 +04:00
|
|
|
/* No PCI init: the BIOS will do it */
|
2005-06-05 19:11:17 +04:00
|
|
|
|
2009-02-08 18:59:36 +03:00
|
|
|
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
|
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
|
2010-02-09 19:37:02 +03:00
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
|
2009-03-08 12:51:29 +03:00
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
|
|
|
|
if (kernel_cmdline) {
|
2011-06-16 01:27:19 +04:00
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
|
|
|
|
pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
|
2009-03-08 12:51:29 +03:00
|
|
|
} else {
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
|
|
|
}
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
|
2009-08-08 14:47:15 +04:00
|
|
|
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
|
|
|
|
|
2010-08-03 17:22:42 +04:00
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
|
2010-02-09 19:37:05 +03:00
|
|
|
if (kvm_enabled()) {
|
|
|
|
#ifdef CONFIG_KVM
|
2010-08-03 17:22:42 +04:00
|
|
|
uint8_t *hypercall;
|
|
|
|
|
2010-02-09 19:37:05 +03:00
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
|
2011-08-21 07:09:37 +04:00
|
|
|
hypercall = g_malloc(16);
|
2010-08-03 17:22:42 +04:00
|
|
|
kvmppc_get_hypercall(env, hypercall, 16);
|
|
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
|
2010-02-09 19:37:05 +03:00
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());
|
|
|
|
}
|
|
|
|
|
2009-03-08 12:51:29 +03:00
|
|
|
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
|
2007-11-24 05:56:36 +03:00
|
|
|
}
|
2005-06-05 19:11:17 +04:00
|
|
|
|
2009-05-21 03:38:09 +04:00
|
|
|
static QEMUMachine core99_machine = {
|
2008-10-08 00:34:35 +04:00
|
|
|
.name = "mac99",
|
|
|
|
.desc = "Mac99 based PowerMAC",
|
|
|
|
.init = ppc_core99_init,
|
2008-10-28 13:59:59 +03:00
|
|
|
.max_cpus = MAX_CPUS,
|
2009-12-20 02:22:26 +03:00
|
|
|
#ifdef TARGET_PPC64
|
|
|
|
.is_default = 1,
|
|
|
|
#endif
|
2013-01-08 11:06:30 +04:00
|
|
|
DEFAULT_MACHINE_OPTIONS,
|
2005-06-05 19:11:17 +04:00
|
|
|
};
|
2009-05-21 03:38:09 +04:00
|
|
|
|
|
|
|
static void core99_machine_init(void)
|
|
|
|
{
|
|
|
|
qemu_register_machine(&core99_machine);
|
|
|
|
}
|
|
|
|
|
|
|
|
machine_init(core99_machine_init);
|