added Heathrow PowerMAC machine - added UniN memory fake controller for Mac99 - added temporary frame buffer OSI calls to keep Mac OS X happy
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1448 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
938828a263
commit
0aa6a4a250
287
hw/ppc_chrp.c
287
hw/ppc_chrp.c
@ -34,9 +34,10 @@
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static int dbdma_mem_index;
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static int cuda_mem_index;
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static int ide0_mem_index;
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static int ide1_mem_index;
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static int openpic_mem_index;
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static int ide0_mem_index = -1;
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static int ide1_mem_index = -1;
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static int openpic_mem_index = -1;
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static int heathrow_pic_mem_index = -1;
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/* DBDMA: currently no op - should suffice right now */
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@ -84,11 +85,20 @@ static CPUReadMemoryFunc *dbdma_read[] = {
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static void macio_map(PCIDevice *pci_dev, int region_num,
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uint32_t addr, uint32_t size, int type)
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{
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if (heathrow_pic_mem_index >= 0) {
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cpu_register_physical_memory(addr + 0x00000, 0x1000,
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heathrow_pic_mem_index);
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}
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cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index);
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cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index);
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cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index);
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cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
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cpu_register_physical_memory(addr + 0x40000, 0x40000, openpic_mem_index);
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if (ide0_mem_index >= 0)
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cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index);
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if (ide1_mem_index >= 0)
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cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
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if (openpic_mem_index >= 0) {
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cpu_register_physical_memory(addr + 0x40000, 0x40000,
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openpic_mem_index);
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}
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}
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static void macio_init(PCIBus *bus)
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@ -116,20 +126,112 @@ static void macio_init(PCIBus *bus)
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PCI_ADDRESS_SPACE_MEM, macio_map);
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}
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/* PowerPC PREP hardware initialisation */
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void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename)
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/* UniN device */
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static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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}
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static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
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{
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return 0;
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}
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static CPUWriteMemoryFunc *unin_write[] = {
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&unin_writel,
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&unin_writel,
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&unin_writel,
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};
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static CPUReadMemoryFunc *unin_read[] = {
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&unin_readl,
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&unin_readl,
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&unin_readl,
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};
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/* temporary frame buffer OSI calls for the video.x driver. The right
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solution is to modify the driver to use VGA PCI I/Os */
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static int vga_osi_call(CPUState *env)
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{
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static int vga_vbl_enabled;
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int linesize;
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// printf("osi_call R5=%d\n", env->gpr[5]);
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/* same handler as PearPC, coming from the original MOL video
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driver. */
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switch(env->gpr[5]) {
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case 4:
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break;
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case 28: /* set_vmode */
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if (env->gpr[6] != 1 || env->gpr[7] != 0)
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env->gpr[3] = 1;
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else
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env->gpr[3] = 0;
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break;
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case 29: /* get_vmode_info */
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if (env->gpr[6] != 0) {
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if (env->gpr[6] != 1 || env->gpr[7] != 0) {
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env->gpr[3] = 1;
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break;
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}
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}
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env->gpr[3] = 0;
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env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
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env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
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env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
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env->gpr[7] = 85 << 16; /* refresh rate */
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env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
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linesize = ((graphic_depth + 7) >> 3) * graphic_width;
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linesize = (linesize + 3) & ~3;
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env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
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break;
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case 31: /* set_video power */
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env->gpr[3] = 0;
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break;
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case 39: /* video_ctrl */
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if (env->gpr[6] == 0 || env->gpr[6] == 1)
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vga_vbl_enabled = env->gpr[6];
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env->gpr[3] = 0;
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break;
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case 47:
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break;
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case 59: /* set_color */
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/* R6 = index, R7 = RGB */
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env->gpr[3] = 0;
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break;
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case 64: /* get color */
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/* R6 = index */
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env->gpr[3] = 0;
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break;
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case 116: /* set hwcursor */
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/* R6 = x, R7 = y, R8 = visible, R9 = data */
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break;
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default:
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fprintf(stderr, "unsupported OSI call R5=%08x\n", env->gpr[5]);
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break;
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}
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return 1; /* osi_call handled */
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}
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/* PowerPC CHRP hardware initialisation */
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static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename,
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int snapshot,
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const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename,
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int is_heathrow)
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{
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char buf[1024];
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openpic_t *openpic;
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SetIRQFunc *set_irq;
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void *pic;
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m48t59_t *nvram;
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int PPC_io_memory;
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int PPC_io_memory, unin_memory;
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int ret, linux_boot, i;
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unsigned long bios_offset;
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uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
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PCIBus *pci_bus;
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const char *arch_name;
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linux_boot = (kernel_filename != NULL);
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@ -180,49 +282,101 @@ void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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}
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/* Register CPU as a 74x/75x */
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cpu_ppc_register(cpu_single_env, 0x00080000);
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/* Set time-base frequency to 100 Mhz */
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cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL);
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/* Set time-base frequency to 10 Mhz */
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cpu_ppc_tb_init(cpu_single_env, 10UL * 1000UL * 1000UL);
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isa_mem_base = 0x80000000;
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pci_bus = pci_pmac_init();
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cpu_single_env->osi_call = vga_osi_call;
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/* Register 8 MB of ISA IO space */
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PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
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cpu_register_physical_memory(0xF2000000, 0x00800000, PPC_io_memory);
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if (is_heathrow) {
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isa_mem_base = 0x80000000;
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pci_bus = pci_grackle_init(0xfec00000);
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/* Register 2 MB of ISA IO space */
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PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
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cpu_register_physical_memory(0xfe000000, 0x00200000, PPC_io_memory);
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/* init basic PC hardware */
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vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size,
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vga_ram_size);
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pic = heathrow_pic_init(&heathrow_pic_mem_index);
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set_irq = heathrow_pic_set_irq;
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pci_set_pic(pci_bus, set_irq, pic);
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/* init basic PC hardware */
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vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size,
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vga_ram_size);
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openpic = openpic_init(NULL, &openpic_mem_index, 1);
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pci_pmac_set_openpic(pci_bus, openpic);
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/* XXX: suppress that */
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pic_init();
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/* XXX: suppress that */
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pic_init();
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/* XXX: use Mac Serial port */
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serial_init(0x3f8, 4, serial_hds[0]);
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for(i = 0; i < nb_nics; i++) {
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pci_ne2000_init(pci_bus, &nd_table[i]);
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}
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pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
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/* XXX: use Mac Serial port */
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serial_init(0x3f8, 4, serial_hds[0]);
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/* cuda also initialize ADB */
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cuda_mem_index = cuda_init(set_irq, pic, 0x12);
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adb_kbd_init(&adb_bus);
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adb_mouse_init(&adb_bus);
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macio_init(pci_bus);
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nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
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arch_name = "HEATHROW";
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} else {
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isa_mem_base = 0x80000000;
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pci_bus = pci_pmac_init();
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/* Register 8 MB of ISA IO space */
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PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
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cpu_register_physical_memory(0xF2000000, 0x00800000, PPC_io_memory);
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/* UniN init */
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unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);
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cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
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for(i = 0; i < nb_nics; i++) {
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pci_ne2000_init(pci_bus, &nd_table[i]);
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/* init basic PC hardware */
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vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size,
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vga_ram_size);
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pic = openpic_init(NULL, &openpic_mem_index, 1);
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set_irq = openpic_set_irq;
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pci_set_pic(pci_bus, set_irq, pic);
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/* XXX: suppress that */
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pic_init();
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/* XXX: use Mac Serial port */
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serial_init(0x3f8, 4, serial_hds[0]);
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for(i = 0; i < nb_nics; i++) {
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pci_ne2000_init(pci_bus, &nd_table[i]);
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}
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#if 1
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ide0_mem_index = pmac_ide_init(&bs_table[0], set_irq, pic, 0x13);
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ide1_mem_index = pmac_ide_init(&bs_table[2], set_irq, pic, 0x14);
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#else
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pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
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#endif
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/* cuda also initialize ADB */
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cuda_mem_index = cuda_init(set_irq, pic, 0x19);
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adb_kbd_init(&adb_bus);
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adb_mouse_init(&adb_bus);
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macio_init(pci_bus);
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nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
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arch_name = "MAC99";
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}
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ide0_mem_index = pmac_ide_init(&bs_table[0], openpic, 0x13);
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ide1_mem_index = pmac_ide_init(&bs_table[2], openpic, 0x14);
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/* cuda also initialize ADB */
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cuda_mem_index = cuda_init(openpic, 0x19);
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adb_kbd_init(&adb_bus);
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adb_mouse_init(&adb_bus);
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macio_init(pci_bus);
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nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
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if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
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graphic_depth = 15;
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PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "CHRP", ram_size, boot_device,
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PPC_NVRAM_set_params(nvram, NVRAM_SIZE, arch_name, ram_size, boot_device,
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kernel_base, kernel_size,
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kernel_cmdline,
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initrd_base, initrd_size,
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@ -230,4 +384,45 @@ void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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0,
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graphic_width, graphic_height, graphic_depth);
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/* No PCI init: the BIOS will do it */
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/* Special port to get debug messages from Open-Firmware */
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register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
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}
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static void ppc_core99_init(int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename,
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int snapshot,
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const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename)
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{
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ppc_chrp_init(ram_size, vga_ram_size, boot_device,
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ds, fd_filename, snapshot,
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kernel_filename, kernel_cmdline,
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initrd_filename, 0);
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}
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static void ppc_heathrow_init(int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename,
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int snapshot,
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const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename)
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{
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ppc_chrp_init(ram_size, vga_ram_size, boot_device,
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ds, fd_filename, snapshot,
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kernel_filename, kernel_cmdline,
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initrd_filename, 1);
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}
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QEMUMachine core99_machine = {
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"core99",
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"Core99 based PowerMAC",
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ppc_core99_init,
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};
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QEMUMachine heathrow_machine = {
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"heathrow",
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"Heathrow based PowerMAC",
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ppc_heathrow_init,
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};
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