2012-11-15 00:54:05 +04:00
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/*
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2012-10-30 06:11:31 +04:00
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* QEMU ICH9 Emulation
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*
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2012-11-15 00:54:05 +04:00
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* Copyright (c) 2006 Fabrice Bellard
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2012-10-30 06:11:31 +04:00
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* Copyright (c) 2009, 2010, 2011
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* Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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* Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
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*
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2014-08-11 12:10:25 +04:00
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* This is based on piix.c, but heavily modified.
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2012-11-15 00:54:05 +04:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2016-01-26 21:17:03 +03:00
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#include "qemu/osdep.h"
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2012-11-15 00:54:05 +04:00
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#include "qemu-common.h"
|
2016-01-19 23:51:44 +03:00
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#include "cpu.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/hw.h"
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2013-07-24 19:56:10 +04:00
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#include "qapi/visitor.h"
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2012-12-17 21:20:00 +04:00
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#include "qemu/range.h"
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2013-02-05 20:06:20 +04:00
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#include "hw/isa/isa.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/sysbus.h"
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2013-02-05 20:06:20 +04:00
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#include "hw/i386/pc.h"
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#include "hw/isa/apm.h"
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#include "hw/i386/ioapic.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bridge.h"
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2013-02-05 20:06:20 +04:00
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#include "hw/i386/ich9.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/ich9.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/pci/pci_bus.h"
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2012-12-17 21:19:49 +04:00
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#include "exec/address-spaces.h"
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2012-12-17 21:20:04 +04:00
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#include "sysemu/sysemu.h"
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2015-12-04 13:10:07 +03:00
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#include "qom/cpu.h"
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hw/isa/lpc_ich9: add SMI feature negotiation via fw_cfg
Introduce the following fw_cfg files:
- "etc/smi/supported-features": a little endian uint64_t feature bitmap,
presenting the features known by the host to the guest. Read-only for
the guest.
The content of this file will be determined via bit-granularity ICH9-LPC
device properties, to be introduced later. For now, the bitmask is left
zeroed. The bits will be set from machine type compat properties and on
the QEMU command line, hence this file is not migrated.
- "etc/smi/requested-features": a little endian uint64_t feature bitmap,
representing the features the guest would like to request. Read-write
for the guest.
The guest can freely (re)write this file, it has no direct consequence.
Initial value is zero. A nonzero value causes the SMI-related fw_cfg
files and fields that are under guest influence to be migrated.
- "etc/smi/features-ok": contains a uint8_t value, and it is read-only for
the guest. When the guest selects the associated fw_cfg key, the guest
features are validated against the host features. In case of error, the
negotiation doesn't proceed, and the "features-ok" file remains zero. In
case of success, the "features-ok" file becomes (uint8_t)1, and the
negotiated features are locked down internally (to which no further
changes are possible until reset).
The initial value is zero. A nonzero value causes the SMI-related
fw_cfg files and fields that are under guest influence to be migrated.
The C-language fields backing the "supported-features" and
"requested-features" files are uint8_t arrays. This is because they carry
guest-side representation (our choice is little endian), while
VMSTATE_UINT64() assumes / implies host-side endianness for any uint64_t
fields. If we migrate a guest between hosts with different endiannesses
(which is possible with TCG), then the host-side value is preserved, and
the host-side representation is translated. This would be visible to the
guest through fw_cfg, unless we used plain byte arrays. So we do.
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20170126014416.11211-2-lersek@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-26 04:44:14 +03:00
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|
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#include "hw/nvram/fw_cfg.h"
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#include "qemu/cutils.h"
|
2012-11-15 00:54:05 +04:00
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/*****************************************************************************/
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/* ICH9 LPC PCI to ISA bridge */
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static void ich9_lpc_reset(DeviceState *qdev);
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/* chipset configuration register
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* to access chipset configuration registers, pci_[sg]et_{byte, word, long}
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* are used.
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* Although it's not pci configuration space, it's little endian as Intel.
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*/
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static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir)
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|
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{
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|
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int intx;
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for (intx = 0; intx < PCI_NUM_PINS; intx++) {
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irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK;
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}
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}
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static void ich9_cc_update(ICH9LPCState *lpc)
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{
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int slot;
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int pci_intx;
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const int reg_offsets[] = {
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ICH9_CC_D25IR,
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ICH9_CC_D26IR,
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ICH9_CC_D27IR,
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ICH9_CC_D28IR,
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ICH9_CC_D29IR,
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ICH9_CC_D30IR,
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ICH9_CC_D31IR,
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};
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const int *offset;
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/* D{25 - 31}IR, but D30IR is read only to 0. */
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for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) {
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if (slot == 30) {
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continue;
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}
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ich9_cc_update_ir(lpc->irr[slot],
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pci_get_word(lpc->chip_config + *offset));
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}
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/*
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|
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* D30: DMI2PCI bridge
|
2016-05-17 04:41:18 +03:00
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* It is arbitrarily decided how INTx lines of PCI devices behind
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* the bridge are connected to pirq lines. Our choice is PIRQ[E-H].
|
2012-11-15 00:54:05 +04:00
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* INT[A-D] are connected to PIRQ[E-H]
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*/
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for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {
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lpc->irr[30][pci_intx] = pci_intx + 4;
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}
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}
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static void ich9_cc_init(ICH9LPCState *lpc)
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{
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int slot;
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int intx;
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/* the default irq routing is arbitrary as long as it matches with
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* acpi irq routing table.
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* The one that is incompatible with piix_pci(= bochs) one is
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* intentionally chosen to let the users know that the different
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* board is used.
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*
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* int[A-D] -> pirq[E-F]
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* avoid pirq A-D because they are used for pci express port
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*/
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for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
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for (intx = 0; intx < PCI_NUM_PINS; intx++) {
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lpc->irr[slot][intx] = (slot + intx) % 4 + 4;
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}
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}
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ich9_cc_update(lpc);
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}
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static void ich9_cc_reset(ICH9LPCState *lpc)
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{
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uint8_t *c = lpc->chip_config;
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memset(lpc->chip_config, 0, sizeof(lpc->chip_config));
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pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT);
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pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT);
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pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT);
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pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT);
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pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT);
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pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT);
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pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT);
|
2015-06-28 20:58:56 +03:00
|
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pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT);
|
2012-11-15 00:54:05 +04:00
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ich9_cc_update(lpc);
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}
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static void ich9_cc_addr_len(uint64_t *addr, unsigned *len)
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|
|
|
{
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*addr &= ICH9_CC_ADDR_MASK;
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if (*addr + *len >= ICH9_CC_SIZE) {
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*len = ICH9_CC_SIZE - *addr;
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}
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}
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/* val: little endian */
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static void ich9_cc_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned len)
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{
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ICH9LPCState *lpc = (ICH9LPCState *)opaque;
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ich9_cc_addr_len(&addr, &len);
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memcpy(lpc->chip_config + addr, &val, len);
|
2017-11-29 11:46:27 +03:00
|
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pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
|
2012-11-15 00:54:05 +04:00
|
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ich9_cc_update(lpc);
|
|
|
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}
|
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/* return value: little endian */
|
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|
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static uint64_t ich9_cc_read(void *opaque, hwaddr addr,
|
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|
|
unsigned len)
|
|
|
|
{
|
|
|
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ICH9LPCState *lpc = (ICH9LPCState *)opaque;
|
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|
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uint32_t val = 0;
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|
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ich9_cc_addr_len(&addr, &len);
|
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|
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memcpy(&val, lpc->chip_config + addr, len);
|
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|
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return val;
|
|
|
|
}
|
|
|
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|
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|
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/* IRQ routing */
|
|
|
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/* */
|
|
|
|
static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis)
|
|
|
|
{
|
|
|
|
*pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK;
|
|
|
|
*pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN;
|
|
|
|
}
|
|
|
|
|
|
|
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static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num,
|
|
|
|
int *pic_irq, int *pic_dis)
|
|
|
|
{
|
|
|
|
switch (pirq_num) {
|
|
|
|
case 0 ... 3: /* A-D */
|
|
|
|
ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num],
|
|
|
|
pic_irq, pic_dis);
|
|
|
|
return;
|
|
|
|
case 4 ... 7: /* E-H */
|
|
|
|
ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)],
|
|
|
|
pic_irq, pic_dis);
|
|
|
|
return;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
|
2016-06-17 18:07:31 +03:00
|
|
|
/* gsi: i8259+ioapic irq 0-15, otherwise assert */
|
|
|
|
static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi)
|
2012-11-15 00:54:05 +04:00
|
|
|
{
|
|
|
|
int i, pic_level;
|
|
|
|
|
2016-06-17 18:07:31 +03:00
|
|
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assert(gsi < ICH9_LPC_PIC_NUM_PINS);
|
|
|
|
|
2012-11-15 00:54:05 +04:00
|
|
|
/* The pic level is the logical OR of all the PCI irqs mapped to it */
|
|
|
|
pic_level = 0;
|
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|
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for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) {
|
|
|
|
int tmp_irq;
|
|
|
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int tmp_dis;
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|
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ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis);
|
2016-06-17 18:07:31 +03:00
|
|
|
if (!tmp_dis && tmp_irq == gsi) {
|
2017-11-29 11:46:27 +03:00
|
|
|
pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i);
|
2012-11-15 00:54:05 +04:00
|
|
|
}
|
|
|
|
}
|
2016-06-23 08:54:22 +03:00
|
|
|
if (gsi == lpc->sci_gsi) {
|
2012-11-15 00:54:05 +04:00
|
|
|
pic_level |= lpc->sci_level;
|
|
|
|
}
|
|
|
|
|
2016-06-17 18:12:09 +03:00
|
|
|
qemu_set_irq(lpc->gsi[gsi], pic_level);
|
2012-11-15 00:54:05 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */
|
|
|
|
static int ich9_pirq_to_gsi(int pirq)
|
|
|
|
{
|
|
|
|
return pirq + ICH9_LPC_PIC_NUM_PINS;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ich9_gsi_to_pirq(int gsi)
|
|
|
|
{
|
|
|
|
return gsi - ICH9_LPC_PIC_NUM_PINS;
|
|
|
|
}
|
|
|
|
|
2016-06-17 18:07:31 +03:00
|
|
|
/* gsi: ioapic irq 16-23, otherwise assert */
|
2012-11-15 00:54:05 +04:00
|
|
|
static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi)
|
|
|
|
{
|
2012-11-15 00:54:08 +04:00
|
|
|
int level = 0;
|
2012-11-15 00:54:05 +04:00
|
|
|
|
2016-06-17 18:07:31 +03:00
|
|
|
assert(gsi >= ICH9_LPC_PIC_NUM_PINS);
|
|
|
|
|
2017-11-29 11:46:27 +03:00
|
|
|
level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi));
|
2016-06-23 08:54:22 +03:00
|
|
|
if (gsi == lpc->sci_gsi) {
|
2012-11-15 00:54:05 +04:00
|
|
|
level |= lpc->sci_level;
|
|
|
|
}
|
|
|
|
|
2016-06-17 18:12:09 +03:00
|
|
|
qemu_set_irq(lpc->gsi[gsi], level);
|
2012-11-15 00:54:05 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
void ich9_lpc_set_irq(void *opaque, int pirq, int level)
|
|
|
|
{
|
|
|
|
ICH9LPCState *lpc = opaque;
|
2016-06-17 18:07:31 +03:00
|
|
|
int pic_irq, pic_dis;
|
2012-11-15 00:54:05 +04:00
|
|
|
|
|
|
|
assert(0 <= pirq);
|
|
|
|
assert(pirq < ICH9_LPC_NB_PIRQS);
|
|
|
|
|
|
|
|
ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq));
|
2016-06-17 18:07:31 +03:00
|
|
|
ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis);
|
|
|
|
ich9_lpc_update_pic(lpc, pic_irq);
|
2012-11-15 00:54:05 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* return the pirq number (PIRQ[A-H]:0-7) corresponding to
|
|
|
|
* a given device irq pin.
|
|
|
|
*/
|
|
|
|
int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
|
|
|
|
{
|
|
|
|
BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
|
|
|
|
PCIBus *pci_bus = PCI_BUS(bus);
|
|
|
|
PCIDevice *lpc_pdev =
|
|
|
|
pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)];
|
|
|
|
ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev);
|
|
|
|
|
|
|
|
return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
|
|
|
|
}
|
|
|
|
|
2013-01-23 06:11:37 +04:00
|
|
|
PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
|
|
|
|
{
|
|
|
|
ICH9LPCState *lpc = opaque;
|
|
|
|
PCIINTxRoute route;
|
|
|
|
int pic_irq;
|
|
|
|
int pic_dis;
|
|
|
|
|
|
|
|
assert(0 <= pirq_pin);
|
|
|
|
assert(pirq_pin < ICH9_LPC_NB_PIRQS);
|
|
|
|
|
|
|
|
route.mode = PCI_INTX_ENABLED;
|
|
|
|
ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis);
|
|
|
|
if (!pic_dis) {
|
|
|
|
if (pic_irq < ICH9_LPC_PIC_NUM_PINS) {
|
|
|
|
route.irq = pic_irq;
|
|
|
|
} else {
|
|
|
|
route.mode = PCI_INTX_DISABLED;
|
|
|
|
route.irq = -1;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
route.irq = ich9_pirq_to_gsi(pirq_pin);
|
|
|
|
}
|
|
|
|
|
|
|
|
return route;
|
|
|
|
}
|
|
|
|
|
2015-06-28 20:58:56 +03:00
|
|
|
void ich9_generate_smi(void)
|
|
|
|
{
|
|
|
|
cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
|
|
|
|
}
|
|
|
|
|
2012-11-15 00:54:05 +04:00
|
|
|
static int ich9_lpc_sci_irq(ICH9LPCState *lpc)
|
|
|
|
{
|
|
|
|
switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] &
|
|
|
|
ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) {
|
|
|
|
case ICH9_LPC_ACPI_CTRL_9:
|
|
|
|
return 9;
|
|
|
|
case ICH9_LPC_ACPI_CTRL_10:
|
|
|
|
return 10;
|
|
|
|
case ICH9_LPC_ACPI_CTRL_11:
|
|
|
|
return 11;
|
|
|
|
case ICH9_LPC_ACPI_CTRL_20:
|
|
|
|
return 20;
|
|
|
|
case ICH9_LPC_ACPI_CTRL_21:
|
|
|
|
return 21;
|
|
|
|
default:
|
|
|
|
/* reserved */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ich9_set_sci(void *opaque, int irq_num, int level)
|
|
|
|
{
|
|
|
|
ICH9LPCState *lpc = opaque;
|
|
|
|
int irq;
|
|
|
|
|
|
|
|
assert(irq_num == 0);
|
|
|
|
level = !!level;
|
|
|
|
if (level == lpc->sci_level) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
lpc->sci_level = level;
|
|
|
|
|
2016-06-23 08:54:22 +03:00
|
|
|
irq = lpc->sci_gsi;
|
2012-11-15 00:54:05 +04:00
|
|
|
if (irq < 0) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-06-17 18:07:31 +03:00
|
|
|
if (irq >= ICH9_LPC_PIC_NUM_PINS) {
|
|
|
|
ich9_lpc_update_apic(lpc, irq);
|
|
|
|
} else {
|
2012-11-15 00:54:05 +04:00
|
|
|
ich9_lpc_update_pic(lpc, irq);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
hw/isa/lpc_ich9: add SMI feature negotiation via fw_cfg
Introduce the following fw_cfg files:
- "etc/smi/supported-features": a little endian uint64_t feature bitmap,
presenting the features known by the host to the guest. Read-only for
the guest.
The content of this file will be determined via bit-granularity ICH9-LPC
device properties, to be introduced later. For now, the bitmask is left
zeroed. The bits will be set from machine type compat properties and on
the QEMU command line, hence this file is not migrated.
- "etc/smi/requested-features": a little endian uint64_t feature bitmap,
representing the features the guest would like to request. Read-write
for the guest.
The guest can freely (re)write this file, it has no direct consequence.
Initial value is zero. A nonzero value causes the SMI-related fw_cfg
files and fields that are under guest influence to be migrated.
- "etc/smi/features-ok": contains a uint8_t value, and it is read-only for
the guest. When the guest selects the associated fw_cfg key, the guest
features are validated against the host features. In case of error, the
negotiation doesn't proceed, and the "features-ok" file remains zero. In
case of success, the "features-ok" file becomes (uint8_t)1, and the
negotiated features are locked down internally (to which no further
changes are possible until reset).
The initial value is zero. A nonzero value causes the SMI-related
fw_cfg files and fields that are under guest influence to be migrated.
The C-language fields backing the "supported-features" and
"requested-features" files are uint8_t arrays. This is because they carry
guest-side representation (our choice is little endian), while
VMSTATE_UINT64() assumes / implies host-side endianness for any uint64_t
fields. If we migrate a guest between hosts with different endiannesses
(which is possible with TCG), then the host-side value is preserved, and
the host-side representation is translated. This would be visible to the
guest through fw_cfg, unless we used plain byte arrays. So we do.
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20170126014416.11211-2-lersek@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-26 04:44:14 +03:00
|
|
|
static void smi_features_ok_callback(void *opaque)
|
|
|
|
{
|
|
|
|
ICH9LPCState *lpc = opaque;
|
|
|
|
uint64_t guest_features;
|
|
|
|
|
|
|
|
if (lpc->smi_features_ok) {
|
|
|
|
/* negotiation already complete, features locked */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features);
|
|
|
|
le64_to_cpus(&guest_features);
|
|
|
|
if (guest_features & ~lpc->smi_host_features) {
|
|
|
|
/* guest requests invalid features, leave @features_ok at zero */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* valid feature subset requested, lock it down, report success */
|
|
|
|
lpc->smi_negotiated_features = guest_features;
|
|
|
|
lpc->smi_features_ok = 1;
|
|
|
|
}
|
|
|
|
|
2016-01-23 19:02:11 +03:00
|
|
|
void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled)
|
2012-11-15 00:54:05 +04:00
|
|
|
{
|
|
|
|
ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
|
2015-06-18 19:30:51 +03:00
|
|
|
qemu_irq sci_irq;
|
hw/isa/lpc_ich9: add SMI feature negotiation via fw_cfg
Introduce the following fw_cfg files:
- "etc/smi/supported-features": a little endian uint64_t feature bitmap,
presenting the features known by the host to the guest. Read-only for
the guest.
The content of this file will be determined via bit-granularity ICH9-LPC
device properties, to be introduced later. For now, the bitmask is left
zeroed. The bits will be set from machine type compat properties and on
the QEMU command line, hence this file is not migrated.
- "etc/smi/requested-features": a little endian uint64_t feature bitmap,
representing the features the guest would like to request. Read-write
for the guest.
The guest can freely (re)write this file, it has no direct consequence.
Initial value is zero. A nonzero value causes the SMI-related fw_cfg
files and fields that are under guest influence to be migrated.
- "etc/smi/features-ok": contains a uint8_t value, and it is read-only for
the guest. When the guest selects the associated fw_cfg key, the guest
features are validated against the host features. In case of error, the
negotiation doesn't proceed, and the "features-ok" file remains zero. In
case of success, the "features-ok" file becomes (uint8_t)1, and the
negotiated features are locked down internally (to which no further
changes are possible until reset).
The initial value is zero. A nonzero value causes the SMI-related
fw_cfg files and fields that are under guest influence to be migrated.
The C-language fields backing the "supported-features" and
"requested-features" files are uint8_t arrays. This is because they carry
guest-side representation (our choice is little endian), while
VMSTATE_UINT64() assumes / implies host-side endianness for any uint64_t
fields. If we migrate a guest between hosts with different endiannesses
(which is possible with TCG), then the host-side value is preserved, and
the host-side representation is translated. This would be visible to the
guest through fw_cfg, unless we used plain byte arrays. So we do.
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20170126014416.11211-2-lersek@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-26 04:44:14 +03:00
|
|
|
FWCfgState *fw_cfg = fw_cfg_find();
|
2012-11-15 00:54:05 +04:00
|
|
|
|
2015-06-18 19:30:51 +03:00
|
|
|
sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0);
|
2016-01-23 19:02:11 +03:00
|
|
|
ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq);
|
hw/isa/lpc_ich9: add SMI feature negotiation via fw_cfg
Introduce the following fw_cfg files:
- "etc/smi/supported-features": a little endian uint64_t feature bitmap,
presenting the features known by the host to the guest. Read-only for
the guest.
The content of this file will be determined via bit-granularity ICH9-LPC
device properties, to be introduced later. For now, the bitmask is left
zeroed. The bits will be set from machine type compat properties and on
the QEMU command line, hence this file is not migrated.
- "etc/smi/requested-features": a little endian uint64_t feature bitmap,
representing the features the guest would like to request. Read-write
for the guest.
The guest can freely (re)write this file, it has no direct consequence.
Initial value is zero. A nonzero value causes the SMI-related fw_cfg
files and fields that are under guest influence to be migrated.
- "etc/smi/features-ok": contains a uint8_t value, and it is read-only for
the guest. When the guest selects the associated fw_cfg key, the guest
features are validated against the host features. In case of error, the
negotiation doesn't proceed, and the "features-ok" file remains zero. In
case of success, the "features-ok" file becomes (uint8_t)1, and the
negotiated features are locked down internally (to which no further
changes are possible until reset).
The initial value is zero. A nonzero value causes the SMI-related
fw_cfg files and fields that are under guest influence to be migrated.
The C-language fields backing the "supported-features" and
"requested-features" files are uint8_t arrays. This is because they carry
guest-side representation (our choice is little endian), while
VMSTATE_UINT64() assumes / implies host-side endianness for any uint64_t
fields. If we migrate a guest between hosts with different endiannesses
(which is possible with TCG), then the host-side value is preserved, and
the host-side representation is translated. This would be visible to the
guest through fw_cfg, unless we used plain byte arrays. So we do.
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20170126014416.11211-2-lersek@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-26 04:44:14 +03:00
|
|
|
|
|
|
|
if (lpc->smi_host_features && fw_cfg) {
|
|
|
|
uint64_t host_features_le;
|
|
|
|
|
|
|
|
host_features_le = cpu_to_le64(lpc->smi_host_features);
|
|
|
|
memcpy(lpc->smi_host_features_le, &host_features_le,
|
|
|
|
sizeof host_features_le);
|
|
|
|
fw_cfg_add_file(fw_cfg, "etc/smi/supported-features",
|
|
|
|
lpc->smi_host_features_le,
|
|
|
|
sizeof lpc->smi_host_features_le);
|
|
|
|
|
|
|
|
/* The other two guest-visible fields are cleared on device reset, we
|
|
|
|
* just link them into fw_cfg here.
|
|
|
|
*/
|
|
|
|
fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features",
|
2017-09-11 19:59:23 +03:00
|
|
|
NULL, NULL, NULL,
|
hw/isa/lpc_ich9: add SMI feature negotiation via fw_cfg
Introduce the following fw_cfg files:
- "etc/smi/supported-features": a little endian uint64_t feature bitmap,
presenting the features known by the host to the guest. Read-only for
the guest.
The content of this file will be determined via bit-granularity ICH9-LPC
device properties, to be introduced later. For now, the bitmask is left
zeroed. The bits will be set from machine type compat properties and on
the QEMU command line, hence this file is not migrated.
- "etc/smi/requested-features": a little endian uint64_t feature bitmap,
representing the features the guest would like to request. Read-write
for the guest.
The guest can freely (re)write this file, it has no direct consequence.
Initial value is zero. A nonzero value causes the SMI-related fw_cfg
files and fields that are under guest influence to be migrated.
- "etc/smi/features-ok": contains a uint8_t value, and it is read-only for
the guest. When the guest selects the associated fw_cfg key, the guest
features are validated against the host features. In case of error, the
negotiation doesn't proceed, and the "features-ok" file remains zero. In
case of success, the "features-ok" file becomes (uint8_t)1, and the
negotiated features are locked down internally (to which no further
changes are possible until reset).
The initial value is zero. A nonzero value causes the SMI-related
fw_cfg files and fields that are under guest influence to be migrated.
The C-language fields backing the "supported-features" and
"requested-features" files are uint8_t arrays. This is because they carry
guest-side representation (our choice is little endian), while
VMSTATE_UINT64() assumes / implies host-side endianness for any uint64_t
fields. If we migrate a guest between hosts with different endiannesses
(which is possible with TCG), then the host-side value is preserved, and
the host-side representation is translated. This would be visible to the
guest through fw_cfg, unless we used plain byte arrays. So we do.
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20170126014416.11211-2-lersek@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-26 04:44:14 +03:00
|
|
|
lpc->smi_guest_features_le,
|
|
|
|
sizeof lpc->smi_guest_features_le,
|
|
|
|
false);
|
|
|
|
fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok",
|
2017-09-11 19:59:23 +03:00
|
|
|
smi_features_ok_callback, NULL, lpc,
|
hw/isa/lpc_ich9: add SMI feature negotiation via fw_cfg
Introduce the following fw_cfg files:
- "etc/smi/supported-features": a little endian uint64_t feature bitmap,
presenting the features known by the host to the guest. Read-only for
the guest.
The content of this file will be determined via bit-granularity ICH9-LPC
device properties, to be introduced later. For now, the bitmask is left
zeroed. The bits will be set from machine type compat properties and on
the QEMU command line, hence this file is not migrated.
- "etc/smi/requested-features": a little endian uint64_t feature bitmap,
representing the features the guest would like to request. Read-write
for the guest.
The guest can freely (re)write this file, it has no direct consequence.
Initial value is zero. A nonzero value causes the SMI-related fw_cfg
files and fields that are under guest influence to be migrated.
- "etc/smi/features-ok": contains a uint8_t value, and it is read-only for
the guest. When the guest selects the associated fw_cfg key, the guest
features are validated against the host features. In case of error, the
negotiation doesn't proceed, and the "features-ok" file remains zero. In
case of success, the "features-ok" file becomes (uint8_t)1, and the
negotiated features are locked down internally (to which no further
changes are possible until reset).
The initial value is zero. A nonzero value causes the SMI-related
fw_cfg files and fields that are under guest influence to be migrated.
The C-language fields backing the "supported-features" and
"requested-features" files are uint8_t arrays. This is because they carry
guest-side representation (our choice is little endian), while
VMSTATE_UINT64() assumes / implies host-side endianness for any uint64_t
fields. If we migrate a guest between hosts with different endiannesses
(which is possible with TCG), then the host-side value is preserved, and
the host-side representation is translated. This would be visible to the
guest through fw_cfg, unless we used plain byte arrays. So we do.
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20170126014416.11211-2-lersek@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-26 04:44:14 +03:00
|
|
|
&lpc->smi_features_ok,
|
|
|
|
sizeof lpc->smi_features_ok,
|
|
|
|
true);
|
|
|
|
}
|
|
|
|
|
2012-11-15 00:54:05 +04:00
|
|
|
ich9_lpc_reset(&lpc->d.qdev);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* APM */
|
|
|
|
|
|
|
|
static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
|
|
|
|
{
|
|
|
|
ICH9LPCState *lpc = arg;
|
|
|
|
|
|
|
|
/* ACPI specs 3.0, 4.7.2.5 */
|
|
|
|
acpi_pm1_cnt_update(&lpc->pm.acpi_regs,
|
|
|
|
val == ICH9_APM_ACPI_ENABLE,
|
|
|
|
val == ICH9_APM_ACPI_DISABLE);
|
2015-06-18 19:28:41 +03:00
|
|
|
if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) {
|
|
|
|
return;
|
|
|
|
}
|
2012-11-15 00:54:05 +04:00
|
|
|
|
|
|
|
/* SMI_EN = PMBASE + 30. SMI control and enable register */
|
|
|
|
if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) {
|
hw/isa/lpc_ich9: add broadcast SMI feature
The generic edk2 SMM infrastructure prefers
EFI_SMM_CONTROL2_PROTOCOL.Trigger() to inject an SMI on each processor. If
Trigger() only brings the current processor into SMM, then edk2 handles it
in the following ways:
(1) If Trigger() is executed by the BSP (which is guaranteed before
ExitBootServices(), but is not necessarily true at runtime), then:
(a) If edk2 has been configured for "traditional" SMM synchronization,
then the BSP sends directed SMIs to the APs with APIC delivery,
bringing them into SMM individually. Then the BSP runs the SMI
handler / dispatcher.
(b) If edk2 has been configured for "relaxed" SMM synchronization,
then the APs that are not already in SMM are not brought in, and
the BSP runs the SMI handler / dispatcher.
(2) If Trigger() is executed by an AP (which is possible after
ExitBootServices(), and can be forced e.g. by "taskset -c 1
efibootmgr"), then the AP in question brings in the BSP with a
directed SMI, and the BSP runs the SMI handler / dispatcher.
The smaller problem with (1a) and (2) is that the BSP and AP
synchronization is slow. For example, the "taskset -c 1 efibootmgr"
command from (2) can take more than 3 seconds to complete, because
efibootmgr accesses non-volatile UEFI variables intensively.
The larger problem is that QEMU's current behavior diverges from the
behavior usually seen on physical hardware, and that keeps exposing
obscure corner cases, race conditions and other instabilities in edk2,
which generally expects / prefers a software SMI to affect all CPUs at
once.
Therefore introduce the "broadcast SMI" feature that causes QEMU to inject
the SMI on all VCPUs.
While the original posting of this patch
<http://lists.nongnu.org/archive/html/qemu-devel/2015-10/msg05658.html>
only intended to speed up (2), based on our recent "stress testing" of SMM
this patch actually provides functional improvements.
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20170126014416.11211-3-lersek@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-26 04:44:15 +03:00
|
|
|
if (lpc->smi_negotiated_features &
|
|
|
|
(UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) {
|
|
|
|
CPUState *cs;
|
|
|
|
CPU_FOREACH(cs) {
|
|
|
|
cpu_interrupt(cs, CPU_INTERRUPT_SMI);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI);
|
|
|
|
}
|
2012-11-15 00:54:05 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* config:PMBASE */
|
|
|
|
static void
|
2016-06-23 08:49:16 +03:00
|
|
|
ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc)
|
2012-11-15 00:54:05 +04:00
|
|
|
{
|
|
|
|
uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE);
|
2016-06-23 08:49:16 +03:00
|
|
|
uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL);
|
2016-06-23 08:54:22 +03:00
|
|
|
uint8_t new_gsi;
|
2016-06-23 08:49:16 +03:00
|
|
|
|
|
|
|
if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) {
|
|
|
|
pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK;
|
|
|
|
} else {
|
|
|
|
pm_io_base = 0;
|
|
|
|
}
|
2012-11-15 00:54:05 +04:00
|
|
|
|
|
|
|
ich9_pm_iospace_update(&lpc->pm, pm_io_base);
|
2016-06-23 08:54:22 +03:00
|
|
|
|
|
|
|
new_gsi = ich9_lpc_sci_irq(lpc);
|
|
|
|
if (lpc->sci_level && new_gsi != lpc->sci_gsi) {
|
|
|
|
qemu_set_irq(lpc->pm.irq, 0);
|
|
|
|
lpc->sci_gsi = new_gsi;
|
|
|
|
qemu_set_irq(lpc->pm.irq, 1);
|
|
|
|
}
|
|
|
|
lpc->sci_gsi = new_gsi;
|
2012-11-15 00:54:05 +04:00
|
|
|
}
|
|
|
|
|
2016-03-07 15:38:58 +03:00
|
|
|
/* config:RCBA */
|
|
|
|
static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old)
|
2012-11-15 00:54:05 +04:00
|
|
|
{
|
2016-03-07 15:38:58 +03:00
|
|
|
uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA);
|
2012-11-15 00:54:05 +04:00
|
|
|
|
2016-03-07 15:38:58 +03:00
|
|
|
if (rcba_old & ICH9_LPC_RCBA_EN) {
|
|
|
|
memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem);
|
2012-11-15 00:54:05 +04:00
|
|
|
}
|
2016-03-07 15:38:58 +03:00
|
|
|
if (rcba & ICH9_LPC_RCBA_EN) {
|
|
|
|
memory_region_add_subregion_overlap(get_system_memory(),
|
|
|
|
rcba & ICH9_LPC_RCBA_BA_MASK,
|
|
|
|
&lpc->rcrb_mem, 1);
|
2012-11-15 00:54:05 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-05-06 11:58:30 +03:00
|
|
|
/* config:GEN_PMCON* */
|
|
|
|
static void
|
|
|
|
ich9_lpc_pmcon_update(ICH9LPCState *lpc)
|
|
|
|
{
|
|
|
|
uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1);
|
|
|
|
uint16_t wmask;
|
|
|
|
|
|
|
|
if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) {
|
|
|
|
wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1);
|
|
|
|
wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK;
|
|
|
|
pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask);
|
|
|
|
lpc->pm.smi_en_wmask &= ~1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-11-15 00:54:05 +04:00
|
|
|
static int ich9_lpc_post_load(void *opaque, int version_id)
|
|
|
|
{
|
|
|
|
ICH9LPCState *lpc = opaque;
|
|
|
|
|
2016-06-23 08:54:22 +03:00
|
|
|
ich9_lpc_pmbase_sci_update(lpc);
|
2016-03-07 15:38:58 +03:00
|
|
|
ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */);
|
2015-05-06 11:58:30 +03:00
|
|
|
ich9_lpc_pmcon_update(lpc);
|
2012-11-15 00:54:05 +04:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ich9_lpc_config_write(PCIDevice *d,
|
|
|
|
uint32_t addr, uint32_t val, int len)
|
|
|
|
{
|
|
|
|
ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
|
2016-03-07 15:38:58 +03:00
|
|
|
uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA);
|
2012-11-15 00:54:05 +04:00
|
|
|
|
|
|
|
pci_default_write_config(d, addr, val, len);
|
2016-06-23 08:49:16 +03:00
|
|
|
if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) ||
|
|
|
|
ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) {
|
2016-06-23 08:54:22 +03:00
|
|
|
ich9_lpc_pmbase_sci_update(lpc);
|
2012-11-15 00:54:05 +04:00
|
|
|
}
|
|
|
|
if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) {
|
2016-03-07 15:38:58 +03:00
|
|
|
ich9_lpc_rcba_update(lpc, rcba_old);
|
2012-11-15 00:54:05 +04:00
|
|
|
}
|
2013-01-23 06:11:37 +04:00
|
|
|
if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) {
|
2017-11-29 11:46:27 +03:00
|
|
|
pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
|
2013-01-23 06:11:37 +04:00
|
|
|
}
|
|
|
|
if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) {
|
2017-11-29 11:46:27 +03:00
|
|
|
pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
|
2013-01-23 06:11:37 +04:00
|
|
|
}
|
2015-05-06 11:58:30 +03:00
|
|
|
if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) {
|
|
|
|
ich9_lpc_pmcon_update(lpc);
|
|
|
|
}
|
2012-11-15 00:54:05 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void ich9_lpc_reset(DeviceState *qdev)
|
|
|
|
{
|
|
|
|
PCIDevice *d = PCI_DEVICE(qdev);
|
|
|
|
ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
|
2016-03-07 15:38:58 +03:00
|
|
|
uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA);
|
2012-11-15 00:54:05 +04:00
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i,
|
|
|
|
ICH9_LPC_PIRQ_ROUT_DEFAULT);
|
|
|
|
}
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i,
|
|
|
|
ICH9_LPC_PIRQ_ROUT_DEFAULT);
|
|
|
|
}
|
|
|
|
pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT);
|
|
|
|
|
|
|
|
pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT);
|
|
|
|
pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT);
|
|
|
|
|
|
|
|
ich9_cc_reset(lpc);
|
|
|
|
|
2016-06-23 08:54:22 +03:00
|
|
|
ich9_lpc_pmbase_sci_update(lpc);
|
2016-03-07 15:38:58 +03:00
|
|
|
ich9_lpc_rcba_update(lpc, rcba_old);
|
2012-11-15 00:54:05 +04:00
|
|
|
|
|
|
|
lpc->sci_level = 0;
|
2013-02-20 05:51:24 +04:00
|
|
|
lpc->rst_cnt = 0;
|
hw/isa/lpc_ich9: add SMI feature negotiation via fw_cfg
Introduce the following fw_cfg files:
- "etc/smi/supported-features": a little endian uint64_t feature bitmap,
presenting the features known by the host to the guest. Read-only for
the guest.
The content of this file will be determined via bit-granularity ICH9-LPC
device properties, to be introduced later. For now, the bitmask is left
zeroed. The bits will be set from machine type compat properties and on
the QEMU command line, hence this file is not migrated.
- "etc/smi/requested-features": a little endian uint64_t feature bitmap,
representing the features the guest would like to request. Read-write
for the guest.
The guest can freely (re)write this file, it has no direct consequence.
Initial value is zero. A nonzero value causes the SMI-related fw_cfg
files and fields that are under guest influence to be migrated.
- "etc/smi/features-ok": contains a uint8_t value, and it is read-only for
the guest. When the guest selects the associated fw_cfg key, the guest
features are validated against the host features. In case of error, the
negotiation doesn't proceed, and the "features-ok" file remains zero. In
case of success, the "features-ok" file becomes (uint8_t)1, and the
negotiated features are locked down internally (to which no further
changes are possible until reset).
The initial value is zero. A nonzero value causes the SMI-related
fw_cfg files and fields that are under guest influence to be migrated.
The C-language fields backing the "supported-features" and
"requested-features" files are uint8_t arrays. This is because they carry
guest-side representation (our choice is little endian), while
VMSTATE_UINT64() assumes / implies host-side endianness for any uint64_t
fields. If we migrate a guest between hosts with different endiannesses
(which is possible with TCG), then the host-side value is preserved, and
the host-side representation is translated. This would be visible to the
guest through fw_cfg, unless we used plain byte arrays. So we do.
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20170126014416.11211-2-lersek@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-26 04:44:14 +03:00
|
|
|
|
|
|
|
memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le);
|
|
|
|
lpc->smi_features_ok = 0;
|
|
|
|
lpc->smi_negotiated_features = 0;
|
2012-11-15 00:54:05 +04:00
|
|
|
}
|
|
|
|
|
2016-03-07 15:38:58 +03:00
|
|
|
/* root complex register block is mapped into memory space */
|
|
|
|
static const MemoryRegionOps rcrb_mmio_ops = {
|
2012-11-15 00:54:05 +04:00
|
|
|
.read = ich9_cc_read,
|
|
|
|
.write = ich9_cc_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
};
|
|
|
|
|
2012-11-23 18:02:18 +04:00
|
|
|
static void ich9_lpc_machine_ready(Notifier *n, void *opaque)
|
|
|
|
{
|
|
|
|
ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready);
|
2013-06-22 10:07:01 +04:00
|
|
|
MemoryRegion *io_as = pci_address_space_io(&s->d);
|
2012-11-23 18:02:18 +04:00
|
|
|
uint8_t *pci_conf;
|
|
|
|
|
|
|
|
pci_conf = s->d.config;
|
2013-07-02 15:40:48 +04:00
|
|
|
if (memory_region_present(io_as, 0x3f8)) {
|
2012-11-23 18:02:18 +04:00
|
|
|
/* com1 */
|
|
|
|
pci_conf[0x82] |= 0x01;
|
|
|
|
}
|
2013-07-02 15:40:48 +04:00
|
|
|
if (memory_region_present(io_as, 0x2f8)) {
|
2012-11-23 18:02:18 +04:00
|
|
|
/* com2 */
|
|
|
|
pci_conf[0x82] |= 0x02;
|
|
|
|
}
|
2013-07-02 15:40:48 +04:00
|
|
|
if (memory_region_present(io_as, 0x378)) {
|
2012-11-23 18:02:18 +04:00
|
|
|
/* lpt */
|
|
|
|
pci_conf[0x82] |= 0x04;
|
|
|
|
}
|
2015-06-01 17:09:12 +03:00
|
|
|
if (memory_region_present(io_as, 0x3f2)) {
|
2012-11-23 18:02:18 +04:00
|
|
|
/* floppy */
|
|
|
|
pci_conf[0x82] |= 0x08;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-02-20 05:51:24 +04:00
|
|
|
/* reset control */
|
|
|
|
static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val,
|
|
|
|
unsigned len)
|
|
|
|
{
|
|
|
|
ICH9LPCState *lpc = opaque;
|
|
|
|
|
|
|
|
if (val & 4) {
|
2017-05-16 00:41:13 +03:00
|
|
|
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
|
2013-02-20 05:51:24 +04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len)
|
|
|
|
{
|
|
|
|
ICH9LPCState *lpc = opaque;
|
|
|
|
|
|
|
|
return lpc->rst_cnt;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps ich9_rst_cnt_ops = {
|
|
|
|
.read = ich9_rst_cnt_read,
|
|
|
|
.write = ich9_rst_cnt_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN
|
|
|
|
};
|
|
|
|
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 16:48:55 +03:00
|
|
|
static void ich9_lpc_get_sci_int(Object *obj, Visitor *v, const char *name,
|
|
|
|
void *opaque, Error **errp)
|
2013-07-24 19:56:10 +04:00
|
|
|
{
|
|
|
|
ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
|
2016-06-23 08:54:22 +03:00
|
|
|
uint32_t value = lpc->sci_gsi;
|
2013-07-24 19:56:10 +04:00
|
|
|
|
qapi: Swap visit_* arguments for consistent 'name' placement
JSON uses "name":value, but many of our visitor interfaces were
called with visit_type_FOO(v, &value, name, errp). This can be
a bit confusing to have to mentally swap the parameter order to
match JSON order. It's particularly bad for visit_start_struct(),
where the 'name' parameter is smack in the middle of the
otherwise-related group of 'obj, kind, size' parameters! It's
time to do a global swap of the parameter ordering, so that the
'name' parameter is always immediately after the Visitor argument.
Additional reason in favor of the swap: the existing include/qjson.h
prefers listing 'name' first in json_prop_*(), and I have plans to
unify that file with the qapi visitors; listing 'name' first in
qapi will minimize churn to the (admittedly few) qjson.h clients.
Later patches will then fix docs, object.h, visitor-impl.h, and
those clients to match.
Done by first patching scripts/qapi*.py by hand to make generated
files do what I want, then by running the following Coccinelle
script to affect the rest of the code base:
$ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'`
I then had to apply some touchups (Coccinelle insisted on TAB
indentation in visitor.h, and botched the signature of
visit_type_enum() by rewriting 'const char *const strings[]' to
the syntactically invalid 'const char*const[] strings'). The
movement of parameters is sufficient to provoke compiler errors
if any callers were missed.
// Part 1: Swap declaration order
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_start_struct
-(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type bool, TV, T1;
identifier ARG1;
@@
bool visit_optional
-(TV v, T1 ARG1, const char *name)
+(TV v, const char *name, T1 ARG1)
{ ... }
@@
type TV, TErr, TObj, T1;
identifier OBJ, ARG1;
@@
void visit_get_next_type
-(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp)
{ ... }
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_type_enum
-(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type TV, TErr, TObj;
identifier OBJ;
identifier VISIT_TYPE =~ "^visit_type_";
@@
void VISIT_TYPE
-(TV v, TObj OBJ, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, TErr errp)
{ ... }
// Part 2: swap caller order
@@
expression V, NAME, OBJ, ARG1, ARG2, ERR;
identifier VISIT_TYPE =~ "^visit_type_";
@@
(
-visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR)
+visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-visit_optional(V, ARG1, NAME)
+visit_optional(V, NAME, ARG1)
|
-visit_get_next_type(V, OBJ, ARG1, NAME, ERR)
+visit_get_next_type(V, NAME, OBJ, ARG1, ERR)
|
-visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR)
+visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-VISIT_TYPE(V, OBJ, NAME, ERR)
+VISIT_TYPE(V, NAME, OBJ, ERR)
)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 16:48:54 +03:00
|
|
|
visit_type_uint32(v, name, &value, errp);
|
2013-07-24 19:56:10 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void ich9_lpc_add_properties(ICH9LPCState *lpc)
|
|
|
|
{
|
|
|
|
static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
|
|
|
|
static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
|
|
|
|
|
|
|
|
object_property_add(OBJECT(lpc), ACPI_PM_PROP_SCI_INT, "uint32",
|
|
|
|
ich9_lpc_get_sci_int,
|
|
|
|
NULL, NULL, NULL, NULL);
|
|
|
|
object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD,
|
|
|
|
&acpi_enable_cmd, NULL);
|
|
|
|
object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD,
|
|
|
|
&acpi_disable_cmd, NULL);
|
|
|
|
|
|
|
|
ich9_pm_add_properties(OBJECT(lpc), &lpc->pm, NULL);
|
|
|
|
}
|
|
|
|
|
2014-06-02 17:25:21 +04:00
|
|
|
static void ich9_lpc_initfn(Object *obj)
|
|
|
|
{
|
|
|
|
ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
|
|
|
|
|
|
|
|
ich9_lpc_add_properties(lpc);
|
|
|
|
}
|
|
|
|
|
2015-12-17 19:35:17 +03:00
|
|
|
static void ich9_lpc_realize(PCIDevice *d, Error **errp)
|
2012-11-15 00:54:05 +04:00
|
|
|
{
|
|
|
|
ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
|
2016-06-22 15:24:54 +03:00
|
|
|
DeviceState *dev = DEVICE(d);
|
2012-11-15 00:54:05 +04:00
|
|
|
ISABus *isa_bus;
|
|
|
|
|
isa: Clean up error handling around isa_bus_new()
We can have at most one ISA bus. If you try to create another one,
isa_bus_new() complains to stderr and returns null.
isa_bus_new() is called in two contexts, machine's init() and device's
realize() methods. Since complaining to stderr is not proper in the
latter context, convert isa_bus_new() to Error.
Machine's init():
* mips_jazz_init(), called from the init() methods of machines
"magnum" and "pica"
* mips_r4k_init(), the init() method of machine "mips"
* pc_init1() called from the init() methods of non-q35 PC machines
* typhoon_init(), called from clipper_init(), the init() method of
machine "clipper"
These callers always create the first ISA bus, hence isa_bus_new()
can't fail. Simply pass &error_abort.
Device's realize():
* i82378_realize(), of PCI device "i82378"
* ich9_lpc_realize(), of PCI device "ICH9-LPC"
* pci_ebus_realize(), of PCI device "ebus"
* piix3_realize(), of PCI device "pci-piix3", abstract parent of
"PIIX3" and "PIIX3-xen"
* piix4_realize(), of PCI device "PIIX4"
* vt82c686b_realize(), of PCI device "VT82C686B"
Propagate the error. Note that these devices are typically created
only by machine init() methods with qdev_init_nofail() or similar. If
we screwed up and created an ISA bus before that call, we now give up
right away. Before, we'd hobble on, and typically die in
isa_bus_irqs(). Similar if someone finds a way to hot-plug one of
these critters.
Cc: Richard Henderson <rth@twiddle.net>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: "Hervé Poussineau" <hpoussin@reactos.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Markus Armbruster <armbru@pond.sub.org>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <1450370121-5768-11-git-send-email-armbru@redhat.com>
2015-12-17 19:35:18 +03:00
|
|
|
isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(),
|
|
|
|
errp);
|
|
|
|
if (!isa_bus) {
|
|
|
|
return;
|
|
|
|
}
|
2012-11-15 00:54:05 +04:00
|
|
|
|
|
|
|
pci_set_long(d->wmask + ICH9_LPC_PMBASE,
|
|
|
|
ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
|
2016-06-23 08:49:16 +03:00
|
|
|
pci_set_byte(d->wmask + ICH9_LPC_PMBASE,
|
2016-06-23 08:54:22 +03:00
|
|
|
ICH9_LPC_ACPI_CTRL_ACPI_EN |
|
|
|
|
ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK);
|
2012-11-15 00:54:05 +04:00
|
|
|
|
2016-03-07 15:38:58 +03:00
|
|
|
memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc,
|
|
|
|
"lpc-rcrb-mmio", ICH9_CC_SIZE);
|
2012-11-15 00:54:05 +04:00
|
|
|
|
|
|
|
lpc->isa_bus = isa_bus;
|
|
|
|
|
|
|
|
ich9_cc_init(lpc);
|
2012-09-19 15:50:03 +04:00
|
|
|
apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc);
|
2012-11-23 18:02:18 +04:00
|
|
|
|
|
|
|
lpc->machine_ready.notify = ich9_lpc_machine_ready;
|
|
|
|
qemu_add_machine_init_done_notifier(&lpc->machine_ready);
|
|
|
|
|
2013-06-07 05:25:08 +04:00
|
|
|
memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc,
|
2013-02-20 05:51:24 +04:00
|
|
|
"lpc-reset-control", 1);
|
|
|
|
memory_region_add_subregion_overlap(pci_address_space_io(d),
|
|
|
|
ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem,
|
|
|
|
1);
|
2016-06-22 15:24:54 +03:00
|
|
|
|
|
|
|
qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS);
|
2016-06-22 15:24:55 +03:00
|
|
|
|
|
|
|
isa_bus_irqs(isa_bus, lpc->gsi);
|
2012-11-15 00:54:05 +04:00
|
|
|
}
|
|
|
|
|
2013-02-20 05:51:24 +04:00
|
|
|
static bool ich9_rst_cnt_needed(void *opaque)
|
|
|
|
{
|
|
|
|
ICH9LPCState *lpc = opaque;
|
|
|
|
|
|
|
|
return (lpc->rst_cnt != 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_ich9_rst_cnt = {
|
|
|
|
.name = "ICH9LPC/rst_cnt",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
2014-09-23 16:09:54 +04:00
|
|
|
.needed = ich9_rst_cnt_needed,
|
2013-02-20 05:51:24 +04:00
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT8(rst_cnt, ICH9LPCState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
hw/isa/lpc_ich9: add SMI feature negotiation via fw_cfg
Introduce the following fw_cfg files:
- "etc/smi/supported-features": a little endian uint64_t feature bitmap,
presenting the features known by the host to the guest. Read-only for
the guest.
The content of this file will be determined via bit-granularity ICH9-LPC
device properties, to be introduced later. For now, the bitmask is left
zeroed. The bits will be set from machine type compat properties and on
the QEMU command line, hence this file is not migrated.
- "etc/smi/requested-features": a little endian uint64_t feature bitmap,
representing the features the guest would like to request. Read-write
for the guest.
The guest can freely (re)write this file, it has no direct consequence.
Initial value is zero. A nonzero value causes the SMI-related fw_cfg
files and fields that are under guest influence to be migrated.
- "etc/smi/features-ok": contains a uint8_t value, and it is read-only for
the guest. When the guest selects the associated fw_cfg key, the guest
features are validated against the host features. In case of error, the
negotiation doesn't proceed, and the "features-ok" file remains zero. In
case of success, the "features-ok" file becomes (uint8_t)1, and the
negotiated features are locked down internally (to which no further
changes are possible until reset).
The initial value is zero. A nonzero value causes the SMI-related
fw_cfg files and fields that are under guest influence to be migrated.
The C-language fields backing the "supported-features" and
"requested-features" files are uint8_t arrays. This is because they carry
guest-side representation (our choice is little endian), while
VMSTATE_UINT64() assumes / implies host-side endianness for any uint64_t
fields. If we migrate a guest between hosts with different endiannesses
(which is possible with TCG), then the host-side value is preserved, and
the host-side representation is translated. This would be visible to the
guest through fw_cfg, unless we used plain byte arrays. So we do.
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20170126014416.11211-2-lersek@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-26 04:44:14 +03:00
|
|
|
static bool ich9_smi_feat_needed(void *opaque)
|
|
|
|
{
|
|
|
|
ICH9LPCState *lpc = opaque;
|
|
|
|
|
|
|
|
return !buffer_is_zero(lpc->smi_guest_features_le,
|
|
|
|
sizeof lpc->smi_guest_features_le) ||
|
|
|
|
lpc->smi_features_ok;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_ich9_smi_feat = {
|
|
|
|
.name = "ICH9LPC/smi_feat",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.needed = ich9_smi_feat_needed,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState,
|
|
|
|
sizeof(uint64_t)),
|
|
|
|
VMSTATE_UINT8(smi_features_ok, ICH9LPCState),
|
|
|
|
VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2012-11-15 00:54:05 +04:00
|
|
|
static const VMStateDescription vmstate_ich9_lpc = {
|
|
|
|
.name = "ICH9LPC",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.post_load = ich9_lpc_post_load,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_PCI_DEVICE(d, ICH9LPCState),
|
|
|
|
VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState),
|
|
|
|
VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs),
|
|
|
|
VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE),
|
|
|
|
VMSTATE_UINT32(sci_level, ICH9LPCState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
2013-02-20 05:51:24 +04:00
|
|
|
},
|
2014-09-23 16:09:54 +04:00
|
|
|
.subsections = (const VMStateDescription*[]) {
|
|
|
|
&vmstate_ich9_rst_cnt,
|
hw/isa/lpc_ich9: add SMI feature negotiation via fw_cfg
Introduce the following fw_cfg files:
- "etc/smi/supported-features": a little endian uint64_t feature bitmap,
presenting the features known by the host to the guest. Read-only for
the guest.
The content of this file will be determined via bit-granularity ICH9-LPC
device properties, to be introduced later. For now, the bitmask is left
zeroed. The bits will be set from machine type compat properties and on
the QEMU command line, hence this file is not migrated.
- "etc/smi/requested-features": a little endian uint64_t feature bitmap,
representing the features the guest would like to request. Read-write
for the guest.
The guest can freely (re)write this file, it has no direct consequence.
Initial value is zero. A nonzero value causes the SMI-related fw_cfg
files and fields that are under guest influence to be migrated.
- "etc/smi/features-ok": contains a uint8_t value, and it is read-only for
the guest. When the guest selects the associated fw_cfg key, the guest
features are validated against the host features. In case of error, the
negotiation doesn't proceed, and the "features-ok" file remains zero. In
case of success, the "features-ok" file becomes (uint8_t)1, and the
negotiated features are locked down internally (to which no further
changes are possible until reset).
The initial value is zero. A nonzero value causes the SMI-related
fw_cfg files and fields that are under guest influence to be migrated.
The C-language fields backing the "supported-features" and
"requested-features" files are uint8_t arrays. This is because they carry
guest-side representation (our choice is little endian), while
VMSTATE_UINT64() assumes / implies host-side endianness for any uint64_t
fields. If we migrate a guest between hosts with different endiannesses
(which is possible with TCG), then the host-side value is preserved, and
the host-side representation is translated. This would be visible to the
guest through fw_cfg, unless we used plain byte arrays. So we do.
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20170126014416.11211-2-lersek@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-26 04:44:14 +03:00
|
|
|
&vmstate_ich9_smi_feat,
|
2014-09-23 16:09:54 +04:00
|
|
|
NULL
|
2012-11-15 00:54:05 +04:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2015-06-28 20:58:58 +03:00
|
|
|
static Property ich9_lpc_properties[] = {
|
|
|
|
DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true),
|
2017-01-26 04:44:16 +03:00
|
|
|
DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features,
|
|
|
|
ICH9_LPC_SMI_F_BROADCAST_BIT, true),
|
2015-06-28 20:58:58 +03:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
2016-05-31 12:57:57 +03:00
|
|
|
static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
|
|
|
|
{
|
|
|
|
ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
|
|
|
|
|
|
|
|
acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev);
|
|
|
|
}
|
|
|
|
|
2012-11-15 00:54:05 +04:00
|
|
|
static void ich9_lpc_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
2014-06-02 17:25:22 +04:00
|
|
|
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
|
2014-06-16 21:12:27 +04:00
|
|
|
AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
|
2012-11-15 00:54:05 +04:00
|
|
|
|
2013-07-29 18:17:45 +04:00
|
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
2012-11-15 00:54:05 +04:00
|
|
|
dc->reset = ich9_lpc_reset;
|
2015-12-17 19:35:17 +03:00
|
|
|
k->realize = ich9_lpc_realize;
|
2012-11-15 00:54:05 +04:00
|
|
|
dc->vmsd = &vmstate_ich9_lpc;
|
2015-06-28 20:58:58 +03:00
|
|
|
dc->props = ich9_lpc_properties;
|
2012-11-15 00:54:05 +04:00
|
|
|
k->config_write = ich9_lpc_config_write;
|
|
|
|
dc->desc = "ICH9 LPC bridge";
|
|
|
|
k->vendor_id = PCI_VENDOR_ID_INTEL;
|
|
|
|
k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8;
|
|
|
|
k->revision = ICH9_A2_LPC_REVISION;
|
|
|
|
k->class_id = PCI_CLASS_BRIDGE_ISA;
|
2013-11-28 20:26:59 +04:00
|
|
|
/*
|
|
|
|
* Reason: part of ICH9 southbridge, needs to be wired up by
|
|
|
|
* pc_q35_init()
|
|
|
|
*/
|
2017-05-03 23:35:44 +03:00
|
|
|
dc->user_creatable = false;
|
2019-03-01 06:35:48 +03:00
|
|
|
hc->pre_plug = ich9_pm_device_pre_plug_cb;
|
2016-05-31 13:01:17 +03:00
|
|
|
hc->plug = ich9_pm_device_plug_cb;
|
|
|
|
hc->unplug_request = ich9_pm_device_unplug_request_cb;
|
|
|
|
hc->unplug = ich9_pm_device_unplug_cb;
|
2014-06-16 21:12:27 +04:00
|
|
|
adevc->ospm_status = ich9_pm_ospm_status;
|
2016-05-31 12:57:57 +03:00
|
|
|
adevc->send_event = ich9_send_gpe;
|
2016-04-20 12:28:57 +03:00
|
|
|
adevc->madt_cpu = pc_madt_cpu_entry;
|
2012-11-15 00:54:05 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo ich9_lpc_info = {
|
|
|
|
.name = TYPE_ICH9_LPC_DEVICE,
|
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(struct ICH9LPCState),
|
2014-06-02 17:25:21 +04:00
|
|
|
.instance_init = ich9_lpc_initfn,
|
2012-11-15 00:54:05 +04:00
|
|
|
.class_init = ich9_lpc_class_init,
|
2014-06-02 17:25:22 +04:00
|
|
|
.interfaces = (InterfaceInfo[]) {
|
|
|
|
{ TYPE_HOTPLUG_HANDLER },
|
2014-06-16 21:12:27 +04:00
|
|
|
{ TYPE_ACPI_DEVICE_IF },
|
2017-09-27 22:56:34 +03:00
|
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
2014-06-02 17:25:22 +04:00
|
|
|
{ }
|
|
|
|
}
|
2012-11-15 00:54:05 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
static void ich9_lpc_register(void)
|
|
|
|
{
|
|
|
|
type_register_static(&ich9_lpc_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(ich9_lpc_register);
|