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ich9: unify pic and ioapic IRQ vectors

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ich9->pic and ich9->ioapic differ for the first 16 GSIs (because
ich9->pic is wired to 8259+IOAPIC but ich9->ioapic is wired to
IOAPIC only).  However, ich9->ioapic is never used for the first
16 GSIs, so the two vectors can be merged.

Reviewed-by: Efimov Vasily <real@ispras.ru>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2016-06-17 17:12:09 +02:00
parent a94dd6a9d6
commit 35a6b23c82
3 changed files with 4 additions and 6 deletions
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3
hw/i386/pc_q35.c
View File

@ -190,8 +190,7 @@ static void pc_q35_init(MachineState *machine)
PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
ich9_lpc = ICH9_LPC_DEVICE(lpc);
ich9_lpc->pic = gsi;
ich9_lpc->ioapic = gsi_state->ioapic_irq;
ich9_lpc->gsi = gsi;
pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
ICH9_LPC_NB_PIRQS);
pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);

4
hw/isa/lpc_ich9.c
View File

@ -225,7 +225,7 @@ static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi)
pic_level |= lpc->sci_level;
}
qemu_set_irq(lpc->pic[gsi], pic_level);
qemu_set_irq(lpc->gsi[gsi], pic_level);
}
/* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */
@ -251,7 +251,7 @@ static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi)
level |= lpc->sci_level;
}
qemu_set_irq(lpc->ioapic[gsi], level);
qemu_set_irq(lpc->gsi[gsi], level);
}
void ich9_lpc_set_irq(void *opaque, int pirq, int level)

3
include/hw/i386/ich9.h
View File

@ -68,8 +68,7 @@ typedef struct ICH9LPCState {
MemoryRegion rcrb_mem; /* root complex register block */
Notifier machine_ready;
qemu_irq *pic;
qemu_irq *ioapic;
qemu_irq *gsi;
} ICH9LPCState;
Object *ich9_lpc_find(void);