ich9: add TCO interface emulation
This interface provides some registers within a 32-byte range and can be acessed through PCI-to-LPC bridge interface (PMBASE + 0x60). It's commonly used as a watchdog timer to detect system lockups through SMIs that are generated -- if TCO_EN bit is set -- on every timeout. If NO_REBOOT bit is not set in GCS (General Control and Status register), the system will be resetted upon second timeout if TCO_RLD register wasn't previously written to prevent timeout. This patch adds support to TCO watchdog logic and few other features like mapping NMIs to SMIs (NMI2SMI_EN bit), system intruder detection, etc. are not implemented yet. Signed-off-by: Paulo Alcantara <pcacjr@zytor.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
parent
71ba2f0af3
commit
920557971b
@ -1,5 +1,5 @@
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common-obj-$(CONFIG_ACPI_X86) += core.o piix4.o pcihp.o
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common-obj-$(CONFIG_ACPI_X86_ICH) += ich9.o
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common-obj-$(CONFIG_ACPI_X86_ICH) += ich9.o tco.o
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common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o
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common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o
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common-obj-$(CONFIG_ACPI) += acpi_interface.o
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@ -30,6 +30,7 @@
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#include "qemu/timer.h"
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#include "sysemu/sysemu.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/tco.h"
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#include "sysemu/kvm.h"
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#include "exec/address-spaces.h"
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@ -92,8 +93,16 @@ static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val,
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unsigned width)
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{
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ICH9LPCPMRegs *pm = opaque;
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TCOIORegs *tr = &pm->tco_regs;
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uint64_t tco_en;
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switch (addr) {
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case 0:
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tco_en = pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN;
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/* once TCO_LOCK bit is set, TCO_EN bit cannot be overwritten */
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if (tr->tco.cnt1 & TCO_LOCK) {
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val = (val & ~ICH9_PMIO_SMI_EN_TCO_EN) | tco_en;
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}
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pm->smi_en &= ~pm->smi_en_wmask;
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pm->smi_en |= (val & pm->smi_en_wmask);
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break;
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@ -159,6 +168,25 @@ static const VMStateDescription vmstate_memhp_state = {
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}
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};
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static bool vmstate_test_use_tco(void *opaque)
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{
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ICH9LPCPMRegs *s = opaque;
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return s->enable_tco;
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}
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static const VMStateDescription vmstate_tco_io_state = {
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.name = "ich9_pm/tco",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.needed = vmstate_test_use_tco,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT(tco_regs, ICH9LPCPMRegs, 1, vmstate_tco_io_sts,
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TCOIORegs),
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VMSTATE_END_OF_LIST()
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}
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};
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const VMStateDescription vmstate_ich9_pm = {
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.name = "ich9_pm",
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.version_id = 1,
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@ -179,6 +207,10 @@ const VMStateDescription vmstate_ich9_pm = {
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.subsections = (const VMStateDescription*[]) {
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&vmstate_memhp_state,
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NULL
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},
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.subsections = (const VMStateDescription*[]) {
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&vmstate_tco_io_state,
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NULL
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}
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};
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@ -209,7 +241,8 @@ static void pm_powerdown_req(Notifier *n, void *opaque)
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acpi_pm1_evt_power_down(&pm->acpi_regs);
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}
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void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, bool smm_enabled,
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void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
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bool smm_enabled, bool enable_tco,
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qemu_irq sci_irq)
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{
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memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
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@ -232,6 +265,12 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, bool smm_enabled,
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memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
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pm->smm_enabled = smm_enabled;
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pm->enable_tco = enable_tco;
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if (pm->enable_tco) {
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acpi_pm_tco_init(&pm->tco_regs, &pm->io);
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}
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pm->irq = sci_irq;
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qemu_register_reset(pm_reset, pm);
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pm->powerdown_notifier.notify = pm_powerdown_req;
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@ -352,6 +391,18 @@ out:
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error_propagate(errp, local_err);
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}
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static bool ich9_pm_get_enable_tco(Object *obj, Error **errp)
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{
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ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
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return s->pm.enable_tco;
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}
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static void ich9_pm_set_enable_tco(Object *obj, bool value, Error **errp)
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{
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ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
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s->pm.enable_tco = value;
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}
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void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp)
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{
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static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
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@ -383,6 +434,10 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp)
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ich9_pm_get_s4_val,
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ich9_pm_set_s4_val,
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NULL, pm, NULL);
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object_property_add_bool(obj, ACPI_PM_PROP_TCO_ENABLED,
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ich9_pm_get_enable_tco,
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ich9_pm_set_enable_tco,
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NULL);
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}
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void ich9_pm_device_plug_cb(ICH9LPCPMRegs *pm, DeviceState *dev, Error **errp)
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264
hw/acpi/tco.c
Normal file
264
hw/acpi/tco.c
Normal file
@ -0,0 +1,264 @@
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/*
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* QEMU ICH9 TCO emulation
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*
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* Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu-common.h"
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#include "sysemu/watchdog.h"
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#include "hw/i386/ich9.h"
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#include "hw/acpi/tco.h"
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//#define DEBUG
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#ifdef DEBUG
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#define TCO_DEBUG(fmt, ...) \
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do { \
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fprintf(stderr, "%s "fmt, __func__, ## __VA_ARGS__); \
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} while (0)
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#else
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#define TCO_DEBUG(fmt, ...) do { } while (0)
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#endif
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enum {
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TCO_RLD_DEFAULT = 0x0000,
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TCO_DAT_IN_DEFAULT = 0x00,
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TCO_DAT_OUT_DEFAULT = 0x00,
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TCO1_STS_DEFAULT = 0x0000,
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TCO2_STS_DEFAULT = 0x0000,
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TCO1_CNT_DEFAULT = 0x0000,
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TCO2_CNT_DEFAULT = 0x0008,
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TCO_MESSAGE1_DEFAULT = 0x00,
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TCO_MESSAGE2_DEFAULT = 0x00,
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TCO_WDCNT_DEFAULT = 0x00,
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TCO_TMR_DEFAULT = 0x0004,
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SW_IRQ_GEN_DEFAULT = 0x03,
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};
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static inline void tco_timer_reload(TCOIORegs *tr)
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{
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tr->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
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((int64_t)(tr->tco.tmr & TCO_TMR_MASK) * TCO_TICK_NSEC);
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timer_mod(tr->tco_timer, tr->expire_time);
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}
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static inline void tco_timer_stop(TCOIORegs *tr)
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{
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tr->expire_time = -1;
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}
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static void tco_timer_expired(void *opaque)
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{
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TCOIORegs *tr = opaque;
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ICH9LPCPMRegs *pm = container_of(tr, ICH9LPCPMRegs, tco_regs);
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ICH9LPCState *lpc = container_of(pm, ICH9LPCState, pm);
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uint32_t gcs = pci_get_long(lpc->chip_config + ICH9_CC_GCS);
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tr->tco.rld = 0;
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tr->tco.sts1 |= TCO_TIMEOUT;
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if (++tr->timeouts_no == 2) {
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tr->tco.sts2 |= TCO_SECOND_TO_STS;
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tr->tco.sts2 |= TCO_BOOT_STS;
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tr->timeouts_no = 0;
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if (!(gcs & ICH9_CC_GCS_NO_REBOOT)) {
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watchdog_perform_action();
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tco_timer_stop(tr);
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return;
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}
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}
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if (pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN) {
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ich9_generate_smi();
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} else {
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ich9_generate_nmi();
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}
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tr->tco.rld = tr->tco.tmr;
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tco_timer_reload(tr);
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}
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/* NOTE: values of 0 or 1 will be ignored by ICH */
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static inline int can_start_tco_timer(TCOIORegs *tr)
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{
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return !(tr->tco.cnt1 & TCO_TMR_HLT) && tr->tco.tmr > 1;
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}
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static uint32_t tco_ioport_readw(TCOIORegs *tr, uint32_t addr)
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{
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uint16_t rld;
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switch (addr) {
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case TCO_RLD:
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if (tr->expire_time != -1) {
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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int64_t elapsed = (tr->expire_time - now) / TCO_TICK_NSEC;
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rld = (uint16_t)elapsed | (tr->tco.rld & ~TCO_RLD_MASK);
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} else {
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rld = tr->tco.rld;
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}
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return rld;
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case TCO_DAT_IN:
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return tr->tco.din;
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case TCO_DAT_OUT:
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return tr->tco.dout;
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case TCO1_STS:
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return tr->tco.sts1;
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case TCO2_STS:
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return tr->tco.sts2;
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case TCO1_CNT:
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return tr->tco.cnt1;
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case TCO2_CNT:
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return tr->tco.cnt2;
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case TCO_MESSAGE1:
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return tr->tco.msg1;
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case TCO_MESSAGE2:
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return tr->tco.msg2;
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case TCO_WDCNT:
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return tr->tco.wdcnt;
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case TCO_TMR:
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return tr->tco.tmr;
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case SW_IRQ_GEN:
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return tr->sw_irq_gen;
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}
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return 0;
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}
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static void tco_ioport_writew(TCOIORegs *tr, uint32_t addr, uint32_t val)
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{
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switch (addr) {
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case TCO_RLD:
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tr->timeouts_no = 0;
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if (can_start_tco_timer(tr)) {
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tr->tco.rld = tr->tco.tmr;
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tco_timer_reload(tr);
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} else {
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tr->tco.rld = val;
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}
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break;
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case TCO_DAT_IN:
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tr->tco.din = val;
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tr->tco.sts1 |= SW_TCO_SMI;
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ich9_generate_smi();
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break;
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case TCO_DAT_OUT:
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tr->tco.dout = val;
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tr->tco.sts1 |= TCO_INT_STS;
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/* TODO: cause an interrupt, as selected by the TCO_INT_SEL bits */
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break;
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case TCO1_STS:
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tr->tco.sts1 = val & TCO1_STS_MASK;
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break;
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case TCO2_STS:
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tr->tco.sts2 = val & TCO2_STS_MASK;
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break;
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case TCO1_CNT:
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val &= TCO1_CNT_MASK;
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/*
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* once TCO_LOCK bit is set, it can not be cleared by software. a reset
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* is required to change this bit from 1 to 0 -- it defaults to 0.
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*/
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tr->tco.cnt1 = val | (tr->tco.cnt1 & TCO_LOCK);
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if (can_start_tco_timer(tr)) {
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tr->tco.rld = tr->tco.tmr;
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tco_timer_reload(tr);
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} else {
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tco_timer_stop(tr);
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}
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break;
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case TCO2_CNT:
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tr->tco.cnt2 = val;
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break;
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case TCO_MESSAGE1:
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tr->tco.msg1 = val;
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break;
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case TCO_MESSAGE2:
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tr->tco.msg2 = val;
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break;
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case TCO_WDCNT:
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tr->tco.wdcnt = val;
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break;
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case TCO_TMR:
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tr->tco.tmr = val;
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break;
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case SW_IRQ_GEN:
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tr->sw_irq_gen = val;
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break;
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}
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}
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static uint64_t tco_io_readw(void *opaque, hwaddr addr, unsigned width)
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{
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TCOIORegs *tr = opaque;
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return tco_ioport_readw(tr, addr);
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}
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static void tco_io_writew(void *opaque, hwaddr addr, uint64_t val,
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unsigned width)
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{
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TCOIORegs *tr = opaque;
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tco_ioport_writew(tr, addr, val);
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}
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static const MemoryRegionOps tco_io_ops = {
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.read = tco_io_readw,
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.write = tco_io_writew,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.impl.min_access_size = 1,
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.impl.max_access_size = 2,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent)
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{
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*tr = (TCOIORegs) {
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.tco = {
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.rld = TCO_RLD_DEFAULT,
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.din = TCO_DAT_IN_DEFAULT,
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.dout = TCO_DAT_OUT_DEFAULT,
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.sts1 = TCO1_STS_DEFAULT,
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.sts2 = TCO2_STS_DEFAULT,
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.cnt1 = TCO1_CNT_DEFAULT,
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.cnt2 = TCO2_CNT_DEFAULT,
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.msg1 = TCO_MESSAGE1_DEFAULT,
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.msg2 = TCO_MESSAGE2_DEFAULT,
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.wdcnt = TCO_WDCNT_DEFAULT,
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.tmr = TCO_TMR_DEFAULT,
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},
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.sw_irq_gen = SW_IRQ_GEN_DEFAULT,
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.tco_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tco_timer_expired, tr),
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.expire_time = -1,
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.timeouts_no = 0,
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};
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memory_region_init_io(&tr->io, memory_region_owner(parent),
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&tco_io_ops, tr, "sm-tco", ICH9_PMIO_TCO_LEN);
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memory_region_add_subregion(parent, ICH9_PMIO_TCO_RLD, &tr->io);
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}
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const VMStateDescription vmstate_tco_io_sts = {
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.name = "tco io device status",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT16(tco.rld, TCOIORegs),
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VMSTATE_UINT8(tco.din, TCOIORegs),
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VMSTATE_UINT8(tco.dout, TCOIORegs),
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VMSTATE_UINT16(tco.sts1, TCOIORegs),
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VMSTATE_UINT16(tco.sts2, TCOIORegs),
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VMSTATE_UINT16(tco.cnt1, TCOIORegs),
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VMSTATE_UINT16(tco.cnt2, TCOIORegs),
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VMSTATE_UINT8(tco.msg1, TCOIORegs),
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VMSTATE_UINT8(tco.msg2, TCOIORegs),
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VMSTATE_UINT8(tco.wdcnt, TCOIORegs),
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VMSTATE_UINT16(tco.tmr, TCOIORegs),
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VMSTATE_UINT8(sw_irq_gen, TCOIORegs),
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VMSTATE_TIMER_PTR(tco_timer, TCOIORegs),
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VMSTATE_INT64(expire_time, TCOIORegs),
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VMSTATE_UINT8(timeouts_no, TCOIORegs),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -253,7 +253,7 @@ static void pc_q35_init(MachineState *machine)
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(pc_machine->vmport != ON_OFF_AUTO_ON), 0xff0104);
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/* connect pm stuff to lpc */
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ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pc_machine));
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ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pc_machine), !mc->no_tco);
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/* ahci and SATA device, for q35 1 ahci controller is built-in */
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ahci = pci_create_simple_multifunction(host_bus,
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@ -397,6 +397,7 @@ static void pc_q35_2_4_machine_options(MachineClass *m)
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m->default_machine_opts = "firmware=bios-256k.bin";
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m->default_display = "std";
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m->no_floppy = 1;
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m->no_tco = 0;
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m->alias = "q35";
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}
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@ -408,6 +409,7 @@ static void pc_q35_2_3_machine_options(MachineClass *m)
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{
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pc_q35_2_4_machine_options(m);
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m->no_floppy = 0;
|
||||
m->no_tco = 1;
|
||||
m->alias = NULL;
|
||||
SET_MACHINE_COMPAT(m, PC_COMPAT_2_3);
|
||||
}
|
||||
|
@ -138,6 +138,7 @@ static void ich9_cc_reset(ICH9LPCState *lpc)
|
||||
pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT);
|
||||
pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT);
|
||||
pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT);
|
||||
pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT);
|
||||
|
||||
ich9_cc_update(lpc);
|
||||
}
|
||||
@ -313,6 +314,16 @@ PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
|
||||
return route;
|
||||
}
|
||||
|
||||
void ich9_generate_smi(void)
|
||||
{
|
||||
cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
|
||||
}
|
||||
|
||||
void ich9_generate_nmi(void)
|
||||
{
|
||||
cpu_interrupt(first_cpu, CPU_INTERRUPT_NMI);
|
||||
}
|
||||
|
||||
static int ich9_lpc_sci_irq(ICH9LPCState *lpc)
|
||||
{
|
||||
switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] &
|
||||
@ -357,13 +368,13 @@ static void ich9_set_sci(void *opaque, int irq_num, int level)
|
||||
}
|
||||
}
|
||||
|
||||
void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled)
|
||||
void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled, bool enable_tco)
|
||||
{
|
||||
ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
|
||||
qemu_irq sci_irq;
|
||||
|
||||
sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0);
|
||||
ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq);
|
||||
ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, enable_tco, sci_irq);
|
||||
ich9_lpc_reset(&lpc->d.qdev);
|
||||
}
|
||||
|
||||
|
@ -25,6 +25,7 @@
|
||||
#include "hw/acpi/cpu_hotplug.h"
|
||||
#include "hw/acpi/memory_hotplug.h"
|
||||
#include "hw/acpi/acpi_dev_interface.h"
|
||||
#include "hw/acpi/tco.h"
|
||||
|
||||
typedef struct ICH9LPCPMRegs {
|
||||
/*
|
||||
@ -55,10 +56,15 @@ typedef struct ICH9LPCPMRegs {
|
||||
uint8_t disable_s4;
|
||||
uint8_t s4_val;
|
||||
uint8_t smm_enabled;
|
||||
bool enable_tco;
|
||||
TCOIORegs tco_regs;
|
||||
} ICH9LPCPMRegs;
|
||||
|
||||
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
|
||||
bool smm_enabled, qemu_irq sci_irq);
|
||||
bool smm_enabled,
|
||||
bool enable_tco,
|
||||
qemu_irq sci_irq);
|
||||
|
||||
void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
|
||||
extern const VMStateDescription vmstate_ich9_pm;
|
||||
|
||||
|
82
include/hw/acpi/tco.h
Normal file
82
include/hw/acpi/tco.h
Normal file
@ -0,0 +1,82 @@
|
||||
/*
|
||||
* QEMU ICH9 TCO emulation
|
||||
*
|
||||
* Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*/
|
||||
#ifndef HW_ACPI_TCO_H
|
||||
#define HW_ACPI_TCO_H
|
||||
|
||||
#include "qemu/typedefs.h"
|
||||
#include "qemu-common.h"
|
||||
|
||||
/* As per ICH9 spec, the internal timer has an error of ~0.6s on every tick */
|
||||
#define TCO_TICK_NSEC 600000000LL
|
||||
|
||||
/* TCO I/O register offsets */
|
||||
enum {
|
||||
TCO_RLD = 0x00,
|
||||
TCO_DAT_IN = 0x02,
|
||||
TCO_DAT_OUT = 0x03,
|
||||
TCO1_STS = 0x04,
|
||||
TCO2_STS = 0x06,
|
||||
TCO1_CNT = 0x08,
|
||||
TCO2_CNT = 0x0a,
|
||||
TCO_MESSAGE1 = 0x0c,
|
||||
TCO_MESSAGE2 = 0x0d,
|
||||
TCO_WDCNT = 0x0e,
|
||||
SW_IRQ_GEN = 0x10,
|
||||
TCO_TMR = 0x12,
|
||||
};
|
||||
|
||||
/* TCO I/O register control/status bits */
|
||||
enum {
|
||||
SW_TCO_SMI = 1 << 1,
|
||||
TCO_INT_STS = 1 << 2,
|
||||
TCO_LOCK = 1 << 12,
|
||||
TCO_TMR_HLT = 1 << 11,
|
||||
TCO_TIMEOUT = 1 << 3,
|
||||
TCO_SECOND_TO_STS = 1 << 1,
|
||||
TCO_BOOT_STS = 1 << 2,
|
||||
};
|
||||
|
||||
/* TCO I/O registers mask bits */
|
||||
enum {
|
||||
TCO_RLD_MASK = 0x3ff,
|
||||
TCO1_STS_MASK = 0xe870,
|
||||
TCO2_STS_MASK = 0xfff8,
|
||||
TCO1_CNT_MASK = 0xfeff,
|
||||
TCO_TMR_MASK = 0x3ff,
|
||||
};
|
||||
|
||||
typedef struct TCOIORegs {
|
||||
struct {
|
||||
uint16_t rld;
|
||||
uint8_t din;
|
||||
uint8_t dout;
|
||||
uint16_t sts1;
|
||||
uint16_t sts2;
|
||||
uint16_t cnt1;
|
||||
uint16_t cnt2;
|
||||
uint8_t msg1;
|
||||
uint8_t msg2;
|
||||
uint8_t wdcnt;
|
||||
uint16_t tmr;
|
||||
} tco;
|
||||
uint8_t sw_irq_gen;
|
||||
|
||||
QEMUTimer *tco_timer;
|
||||
int64_t expire_time;
|
||||
uint8_t timeouts_no;
|
||||
|
||||
MemoryRegion io;
|
||||
} TCOIORegs;
|
||||
|
||||
/* tco.c */
|
||||
void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent);
|
||||
|
||||
extern const VMStateDescription vmstate_tco_io_sts;
|
||||
|
||||
#endif /* HW_ACPI_TCO_H */
|
@ -99,7 +99,8 @@ struct MachineClass {
|
||||
no_floppy:1,
|
||||
no_cdrom:1,
|
||||
no_sdcard:1,
|
||||
has_dynamic_sysbus:1;
|
||||
has_dynamic_sysbus:1,
|
||||
no_tco:1;
|
||||
int is_default;
|
||||
const char *default_machine_opts;
|
||||
const char *default_boot_order;
|
||||
|
@ -17,9 +17,12 @@
|
||||
void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
|
||||
int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
|
||||
PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
|
||||
void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
|
||||
void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled, bool enable_tco);
|
||||
I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
|
||||
|
||||
void ich9_generate_smi(void);
|
||||
void ich9_generate_nmi(void);
|
||||
|
||||
#define ICH9_CC_SIZE (16 * 1024) /* 16KB */
|
||||
|
||||
#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
|
||||
@ -90,6 +93,9 @@ Object *ich9_lpc_find(void);
|
||||
#define ICH9_CC_DIR_MASK 0x7
|
||||
#define ICH9_CC_OIC 0x31FF
|
||||
#define ICH9_CC_OIC_AEN 0x1
|
||||
#define ICH9_CC_GCS 0x3410
|
||||
#define ICH9_CC_GCS_DEFAULT 0x00000020
|
||||
#define ICH9_CC_GCS_NO_REBOOT (1 << 5)
|
||||
|
||||
/* D28:F[0-5] */
|
||||
#define ICH9_PCIE_DEV 28
|
||||
@ -186,7 +192,10 @@ Object *ich9_lpc_find(void);
|
||||
#define ICH9_PMIO_GPE0_LEN 16
|
||||
#define ICH9_PMIO_SMI_EN 0x30
|
||||
#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
|
||||
#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13)
|
||||
#define ICH9_PMIO_SMI_STS 0x34
|
||||
#define ICH9_PMIO_TCO_RLD 0x60
|
||||
#define ICH9_PMIO_TCO_LEN 32
|
||||
|
||||
/* FADT ACPI_ENABLE/ACPI_DISABLE */
|
||||
#define ICH9_APM_ACPI_ENABLE 0x2
|
||||
|
@ -88,6 +88,7 @@ typedef struct PcPciInfo {
|
||||
#define ACPI_PM_PROP_PM_IO_BASE "pm_io_base"
|
||||
#define ACPI_PM_PROP_GPE0_BLK "gpe0_blk"
|
||||
#define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"
|
||||
#define ACPI_PM_PROP_TCO_ENABLED "enable_tco"
|
||||
|
||||
struct PcGuestInfo {
|
||||
bool isapc_ram_fw;
|
||||
|
Loading…
Reference in New Issue
Block a user