2013-09-03 23:12:07 +04:00
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/*
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* QEMU AArch64 CPU
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*
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* Copyright (c) 2013 Linaro Ltd
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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2015-12-07 19:23:44 +03:00
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#include "qemu/osdep.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 11:01:28 +03:00
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#include "qapi/error.h"
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2013-09-03 23:12:07 +04:00
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#include "cpu.h"
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2019-05-23 17:35:07 +03:00
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#include "qemu/module.h"
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2013-09-03 23:12:07 +04:00
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h"
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#endif
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#include "sysemu/kvm.h"
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2018-03-09 20:09:44 +03:00
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#include "kvm_arm.h"
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2018-08-16 16:05:28 +03:00
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#include "qapi/visitor.h"
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2013-09-03 23:12:07 +04:00
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static inline void set_feature(CPUARMState *env, int feature)
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{
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env->features |= 1ULL << feature;
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}
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2015-02-13 08:46:08 +03:00
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static inline void unset_feature(CPUARMState *env, int feature)
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{
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env->features &= ~(1ULL << feature);
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}
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2014-04-15 22:18:48 +04:00
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#ifndef CONFIG_USER_ONLY
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2015-05-15 05:22:52 +03:00
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static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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2014-04-15 22:18:48 +04:00
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{
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2019-03-23 03:41:14 +03:00
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ARMCPU *cpu = env_archcpu(env);
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2018-03-09 20:09:43 +03:00
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/* Number of cores is in [25:24]; otherwise we RAZ */
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return (cpu->core_count - 1) << 24;
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2014-04-15 22:18:48 +04:00
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}
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#endif
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2018-10-11 05:19:29 +03:00
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static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
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2014-04-15 22:18:48 +04:00
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#ifndef CONFIG_USER_ONLY
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{ .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
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2015-05-15 05:22:52 +03:00
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.access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
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2014-04-15 22:18:48 +04:00
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.writefn = arm_cp_write_ignore },
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{ .name = "L2CTLR",
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.cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
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2015-05-15 05:22:52 +03:00
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.access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
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2014-04-15 22:18:48 +04:00
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.writefn = arm_cp_write_ignore },
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#endif
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{ .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "L2ECTLR",
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.cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUACTLR",
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.cp = 15, .opc1 = 0, .crm = 15,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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{ .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUECTLR",
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.cp = 15, .opc1 = 1, .crm = 15,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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{ .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUMERRSR",
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.cp = 15, .opc1 = 2, .crm = 15,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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{ .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "L2MERRSR",
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.cp = 15, .opc1 = 3, .crm = 15,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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REGINFO_SENTINEL
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};
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2014-04-15 22:18:44 +04:00
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static void aarch64_a57_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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2015-03-11 16:21:06 +03:00
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cpu->dtb_compatible = "arm,cortex-a57";
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2014-04-15 22:18:44 +04:00
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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2014-04-15 22:18:49 +04:00
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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2017-01-20 14:15:10 +03:00
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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2016-02-11 14:17:31 +03:00
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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2016-10-28 16:12:31 +03:00
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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2014-04-15 22:18:44 +04:00
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
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cpu->midr = 0x411fd070;
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2015-06-15 20:06:08 +03:00
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cpu->revidr = 0x00000000;
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2014-04-15 22:18:44 +04:00
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cpu->reset_fpsid = 0x41034070;
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2018-10-24 09:50:16 +03:00
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x12111111;
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cpu->isar.mvfr2 = 0x00000043;
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2014-04-15 22:18:44 +04:00
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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2018-10-24 09:50:16 +03:00
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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cpu->isar.id_isar3 = 0x01112131;
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cpu->isar.id_isar4 = 0x00011142;
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cpu->isar.id_isar5 = 0x00011121;
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cpu->isar.id_isar6 = 0;
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cpu->isar.id_aa64pfr0 = 0x00002222;
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2014-04-15 22:18:44 +04:00
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cpu->id_aa64dfr0 = 0x10305106;
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2018-10-24 09:50:16 +03:00
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cpu->isar.id_aa64isar0 = 0x00011120;
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2018-12-13 17:40:56 +03:00
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cpu->isar.id_aa64mmfr0 = 0x00001124;
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2014-08-19 21:56:25 +04:00
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cpu->dbgdidr = 0x3516d000;
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2014-04-15 22:18:44 +04:00
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
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cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
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cpu->dcz_blocksize = 4; /* 64 bytes */
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2017-01-20 14:15:09 +03:00
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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cpu->gic_vprebits = 5;
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2018-10-11 05:19:29 +03:00
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define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
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2014-04-15 22:18:44 +04:00
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}
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2015-05-15 05:22:55 +03:00
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static void aarch64_a53_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,cortex-a53";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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2017-01-20 14:15:10 +03:00
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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2016-02-11 14:17:31 +03:00
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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2016-10-28 16:12:31 +03:00
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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2015-06-15 20:06:08 +03:00
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
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2015-05-15 05:22:55 +03:00
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cpu->midr = 0x410fd034;
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2015-06-15 20:06:08 +03:00
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cpu->revidr = 0x00000000;
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2015-05-15 05:22:55 +03:00
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cpu->reset_fpsid = 0x41034070;
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2018-10-24 09:50:16 +03:00
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x12111111;
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cpu->isar.mvfr2 = 0x00000043;
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2015-05-15 05:22:55 +03:00
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cpu->ctr = 0x84448004; /* L1Ip = VIPT */
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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2018-10-24 09:50:16 +03:00
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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cpu->isar.id_isar3 = 0x01112131;
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cpu->isar.id_isar4 = 0x00011142;
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cpu->isar.id_isar5 = 0x00011121;
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cpu->isar.id_isar6 = 0;
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cpu->isar.id_aa64pfr0 = 0x00002222;
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2015-05-15 05:22:55 +03:00
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cpu->id_aa64dfr0 = 0x10305106;
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2018-10-24 09:50:16 +03:00
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cpu->isar.id_aa64isar0 = 0x00011120;
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2018-12-13 17:40:56 +03:00
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cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
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2015-05-15 05:22:55 +03:00
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cpu->dbgdidr = 0x3516d000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
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cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
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cpu->dcz_blocksize = 4; /* 64 bytes */
|
2017-01-20 14:15:09 +03:00
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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cpu->gic_vprebits = 5;
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2018-10-11 05:19:29 +03:00
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define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
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}
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static void aarch64_a72_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,cortex-a72";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->midr = 0x410fd083;
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cpu->revidr = 0x00000000;
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cpu->reset_fpsid = 0x41034080;
|
2018-10-24 09:50:16 +03:00
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x12111111;
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cpu->isar.mvfr2 = 0x00000043;
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2018-10-11 05:19:29 +03:00
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10201105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
|
2018-10-24 09:50:16 +03:00
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|
|
cpu->isar.id_isar0 = 0x02101110;
|
|
|
|
cpu->isar.id_isar1 = 0x13112111;
|
|
|
|
cpu->isar.id_isar2 = 0x21232042;
|
|
|
|
cpu->isar.id_isar3 = 0x01112131;
|
|
|
|
cpu->isar.id_isar4 = 0x00011142;
|
|
|
|
cpu->isar.id_isar5 = 0x00011121;
|
|
|
|
cpu->isar.id_aa64pfr0 = 0x00002222;
|
2018-10-11 05:19:29 +03:00
|
|
|
cpu->id_aa64dfr0 = 0x10305106;
|
2018-10-24 09:50:16 +03:00
|
|
|
cpu->isar.id_aa64isar0 = 0x00011120;
|
2018-12-13 17:40:56 +03:00
|
|
|
cpu->isar.id_aa64mmfr0 = 0x00001124;
|
2018-10-11 05:19:29 +03:00
|
|
|
cpu->dbgdidr = 0x3516d000;
|
|
|
|
cpu->clidr = 0x0a200023;
|
|
|
|
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
|
|
|
|
cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
|
|
|
|
cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
|
|
|
|
cpu->dcz_blocksize = 4; /* 64 bytes */
|
|
|
|
cpu->gic_num_lrs = 4;
|
|
|
|
cpu->gic_vpribits = 5;
|
|
|
|
cpu->gic_vprebits = 5;
|
|
|
|
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
|
2015-05-15 05:22:55 +03:00
|
|
|
}
|
|
|
|
|
target/arm/cpu64: max cpu: Introduce sve<N> properties
Introduce cpu properties to give fine control over SVE vector lengths.
We introduce a property for each valid length up to the current
maximum supported, which is 2048-bits. The properties are named, e.g.
sve128, sve256, sve384, sve512, ..., where the number is the number of
bits. See the updates to docs/arm-cpu-features.rst for a description
of the semantics and for example uses.
Note, as sve-max-vq is still present and we'd like to be able to
support qmp_query_cpu_model_expansion with guests launched with e.g.
-cpu max,sve-max-vq=8 on their command lines, then we do allow
sve-max-vq and sve<N> properties to be provided at the same time, but
this is not recommended, and is why sve-max-vq is not mentioned in the
document. If sve-max-vq is provided then it enables all lengths smaller
than and including the max and disables all lengths larger. It also has
the side-effect that no larger lengths may be enabled and that the max
itself cannot be disabled. Smaller non-power-of-two lengths may,
however, be disabled, e.g. -cpu max,sve-max-vq=4,sve384=off provides a
guest the vector lengths 128, 256, and 512 bits.
This patch has been co-authored with Richard Henderson, who reworked
the target/arm/cpu64.c changes in order to push all the validation and
auto-enabling/disabling steps into the finalizer, resulting in a nice
LOC reduction.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-31 17:27:29 +03:00
|
|
|
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* If any vector lengths are explicitly enabled with sve<N> properties,
|
|
|
|
* then all other lengths are implicitly disabled. If sve-max-vq is
|
|
|
|
* specified then it is the same as explicitly enabling all lengths
|
|
|
|
* up to and including the specified maximum, which means all larger
|
|
|
|
* lengths will be implicitly disabled. If no sve<N> properties
|
|
|
|
* are enabled and sve-max-vq is not specified, then all lengths not
|
|
|
|
* explicitly disabled will be enabled. Additionally, all power-of-two
|
|
|
|
* vector lengths less than the maximum enabled length will be
|
|
|
|
* automatically enabled and all vector lengths larger than the largest
|
|
|
|
* disabled power-of-two vector length will be automatically disabled.
|
|
|
|
* Errors are generated if the user provided input that interferes with
|
|
|
|
* any of the above. Finally, if SVE is not disabled, then at least one
|
|
|
|
* vector length must be enabled.
|
|
|
|
*/
|
2019-10-31 17:27:33 +03:00
|
|
|
DECLARE_BITMAP(kvm_supported, ARM_MAX_VQ);
|
target/arm/cpu64: max cpu: Introduce sve<N> properties
Introduce cpu properties to give fine control over SVE vector lengths.
We introduce a property for each valid length up to the current
maximum supported, which is 2048-bits. The properties are named, e.g.
sve128, sve256, sve384, sve512, ..., where the number is the number of
bits. See the updates to docs/arm-cpu-features.rst for a description
of the semantics and for example uses.
Note, as sve-max-vq is still present and we'd like to be able to
support qmp_query_cpu_model_expansion with guests launched with e.g.
-cpu max,sve-max-vq=8 on their command lines, then we do allow
sve-max-vq and sve<N> properties to be provided at the same time, but
this is not recommended, and is why sve-max-vq is not mentioned in the
document. If sve-max-vq is provided then it enables all lengths smaller
than and including the max and disables all lengths larger. It also has
the side-effect that no larger lengths may be enabled and that the max
itself cannot be disabled. Smaller non-power-of-two lengths may,
however, be disabled, e.g. -cpu max,sve-max-vq=4,sve384=off provides a
guest the vector lengths 128, 256, and 512 bits.
This patch has been co-authored with Richard Henderson, who reworked
the target/arm/cpu64.c changes in order to push all the validation and
auto-enabling/disabling steps into the finalizer, resulting in a nice
LOC reduction.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-31 17:27:29 +03:00
|
|
|
DECLARE_BITMAP(tmp, ARM_MAX_VQ);
|
|
|
|
uint32_t vq, max_vq = 0;
|
|
|
|
|
2019-10-31 17:27:33 +03:00
|
|
|
/* Collect the set of vector lengths supported by KVM. */
|
|
|
|
bitmap_zero(kvm_supported, ARM_MAX_VQ);
|
|
|
|
if (kvm_enabled() && kvm_arm_sve_supported(CPU(cpu))) {
|
|
|
|
kvm_arm_sve_get_vls(CPU(cpu), kvm_supported);
|
|
|
|
} else if (kvm_enabled()) {
|
|
|
|
assert(!cpu_isar_feature(aa64_sve, cpu));
|
|
|
|
}
|
|
|
|
|
target/arm/cpu64: max cpu: Introduce sve<N> properties
Introduce cpu properties to give fine control over SVE vector lengths.
We introduce a property for each valid length up to the current
maximum supported, which is 2048-bits. The properties are named, e.g.
sve128, sve256, sve384, sve512, ..., where the number is the number of
bits. See the updates to docs/arm-cpu-features.rst for a description
of the semantics and for example uses.
Note, as sve-max-vq is still present and we'd like to be able to
support qmp_query_cpu_model_expansion with guests launched with e.g.
-cpu max,sve-max-vq=8 on their command lines, then we do allow
sve-max-vq and sve<N> properties to be provided at the same time, but
this is not recommended, and is why sve-max-vq is not mentioned in the
document. If sve-max-vq is provided then it enables all lengths smaller
than and including the max and disables all lengths larger. It also has
the side-effect that no larger lengths may be enabled and that the max
itself cannot be disabled. Smaller non-power-of-two lengths may,
however, be disabled, e.g. -cpu max,sve-max-vq=4,sve384=off provides a
guest the vector lengths 128, 256, and 512 bits.
This patch has been co-authored with Richard Henderson, who reworked
the target/arm/cpu64.c changes in order to push all the validation and
auto-enabling/disabling steps into the finalizer, resulting in a nice
LOC reduction.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-31 17:27:29 +03:00
|
|
|
/*
|
|
|
|
* Process explicit sve<N> properties.
|
|
|
|
* From the properties, sve_vq_map<N> implies sve_vq_init<N>.
|
|
|
|
* Check first for any sve<N> enabled.
|
|
|
|
*/
|
|
|
|
if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) {
|
|
|
|
max_vq = find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1;
|
|
|
|
|
|
|
|
if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) {
|
|
|
|
error_setg(errp, "cannot enable sve%d", max_vq * 128);
|
|
|
|
error_append_hint(errp, "sve%d is larger than the maximum vector "
|
|
|
|
"length, sve-max-vq=%d (%d bits)\n",
|
|
|
|
max_vq * 128, cpu->sve_max_vq,
|
|
|
|
cpu->sve_max_vq * 128);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2019-10-31 17:27:33 +03:00
|
|
|
if (kvm_enabled()) {
|
|
|
|
/*
|
|
|
|
* For KVM we have to automatically enable all supported unitialized
|
|
|
|
* lengths, even when the smaller lengths are not all powers-of-two.
|
|
|
|
*/
|
|
|
|
bitmap_andnot(tmp, kvm_supported, cpu->sve_vq_init, max_vq);
|
|
|
|
bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq);
|
|
|
|
} else {
|
|
|
|
/* Propagate enabled bits down through required powers-of-two. */
|
|
|
|
for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
|
|
|
|
if (!test_bit(vq - 1, cpu->sve_vq_init)) {
|
|
|
|
set_bit(vq - 1, cpu->sve_vq_map);
|
|
|
|
}
|
target/arm/cpu64: max cpu: Introduce sve<N> properties
Introduce cpu properties to give fine control over SVE vector lengths.
We introduce a property for each valid length up to the current
maximum supported, which is 2048-bits. The properties are named, e.g.
sve128, sve256, sve384, sve512, ..., where the number is the number of
bits. See the updates to docs/arm-cpu-features.rst for a description
of the semantics and for example uses.
Note, as sve-max-vq is still present and we'd like to be able to
support qmp_query_cpu_model_expansion with guests launched with e.g.
-cpu max,sve-max-vq=8 on their command lines, then we do allow
sve-max-vq and sve<N> properties to be provided at the same time, but
this is not recommended, and is why sve-max-vq is not mentioned in the
document. If sve-max-vq is provided then it enables all lengths smaller
than and including the max and disables all lengths larger. It also has
the side-effect that no larger lengths may be enabled and that the max
itself cannot be disabled. Smaller non-power-of-two lengths may,
however, be disabled, e.g. -cpu max,sve-max-vq=4,sve384=off provides a
guest the vector lengths 128, 256, and 512 bits.
This patch has been co-authored with Richard Henderson, who reworked
the target/arm/cpu64.c changes in order to push all the validation and
auto-enabling/disabling steps into the finalizer, resulting in a nice
LOC reduction.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-31 17:27:29 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
} else if (cpu->sve_max_vq == 0) {
|
|
|
|
/*
|
|
|
|
* No explicit bits enabled, and no implicit bits from sve-max-vq.
|
|
|
|
*/
|
|
|
|
if (!cpu_isar_feature(aa64_sve, cpu)) {
|
|
|
|
/* SVE is disabled and so are all vector lengths. Good. */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2019-10-31 17:27:33 +03:00
|
|
|
if (kvm_enabled()) {
|
|
|
|
/* Disabling a supported length disables all larger lengths. */
|
|
|
|
for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
|
|
|
|
if (test_bit(vq - 1, cpu->sve_vq_init) &&
|
|
|
|
test_bit(vq - 1, kvm_supported)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
|
|
|
|
bitmap_andnot(cpu->sve_vq_map, kvm_supported,
|
|
|
|
cpu->sve_vq_init, max_vq);
|
|
|
|
if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) {
|
|
|
|
error_setg(errp, "cannot disable sve%d", vq * 128);
|
|
|
|
error_append_hint(errp, "Disabling sve%d results in all "
|
|
|
|
"vector lengths being disabled.\n",
|
|
|
|
vq * 128);
|
|
|
|
error_append_hint(errp, "With SVE enabled, at least one "
|
|
|
|
"vector length must be enabled.\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* Disabling a power-of-two disables all larger lengths. */
|
|
|
|
if (test_bit(0, cpu->sve_vq_init)) {
|
|
|
|
error_setg(errp, "cannot disable sve128");
|
|
|
|
error_append_hint(errp, "Disabling sve128 results in all "
|
|
|
|
"vector lengths being disabled.\n");
|
|
|
|
error_append_hint(errp, "With SVE enabled, at least one "
|
|
|
|
"vector length must be enabled.\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
|
|
|
|
if (test_bit(vq - 1, cpu->sve_vq_init)) {
|
|
|
|
break;
|
|
|
|
}
|
target/arm/cpu64: max cpu: Introduce sve<N> properties
Introduce cpu properties to give fine control over SVE vector lengths.
We introduce a property for each valid length up to the current
maximum supported, which is 2048-bits. The properties are named, e.g.
sve128, sve256, sve384, sve512, ..., where the number is the number of
bits. See the updates to docs/arm-cpu-features.rst for a description
of the semantics and for example uses.
Note, as sve-max-vq is still present and we'd like to be able to
support qmp_query_cpu_model_expansion with guests launched with e.g.
-cpu max,sve-max-vq=8 on their command lines, then we do allow
sve-max-vq and sve<N> properties to be provided at the same time, but
this is not recommended, and is why sve-max-vq is not mentioned in the
document. If sve-max-vq is provided then it enables all lengths smaller
than and including the max and disables all lengths larger. It also has
the side-effect that no larger lengths may be enabled and that the max
itself cannot be disabled. Smaller non-power-of-two lengths may,
however, be disabled, e.g. -cpu max,sve-max-vq=4,sve384=off provides a
guest the vector lengths 128, 256, and 512 bits.
This patch has been co-authored with Richard Henderson, who reworked
the target/arm/cpu64.c changes in order to push all the validation and
auto-enabling/disabling steps into the finalizer, resulting in a nice
LOC reduction.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-31 17:27:29 +03:00
|
|
|
}
|
2019-10-31 17:27:33 +03:00
|
|
|
max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
|
|
|
|
bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
|
target/arm/cpu64: max cpu: Introduce sve<N> properties
Introduce cpu properties to give fine control over SVE vector lengths.
We introduce a property for each valid length up to the current
maximum supported, which is 2048-bits. The properties are named, e.g.
sve128, sve256, sve384, sve512, ..., where the number is the number of
bits. See the updates to docs/arm-cpu-features.rst for a description
of the semantics and for example uses.
Note, as sve-max-vq is still present and we'd like to be able to
support qmp_query_cpu_model_expansion with guests launched with e.g.
-cpu max,sve-max-vq=8 on their command lines, then we do allow
sve-max-vq and sve<N> properties to be provided at the same time, but
this is not recommended, and is why sve-max-vq is not mentioned in the
document. If sve-max-vq is provided then it enables all lengths smaller
than and including the max and disables all lengths larger. It also has
the side-effect that no larger lengths may be enabled and that the max
itself cannot be disabled. Smaller non-power-of-two lengths may,
however, be disabled, e.g. -cpu max,sve-max-vq=4,sve384=off provides a
guest the vector lengths 128, 256, and 512 bits.
This patch has been co-authored with Richard Henderson, who reworked
the target/arm/cpu64.c changes in order to push all the validation and
auto-enabling/disabling steps into the finalizer, resulting in a nice
LOC reduction.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-31 17:27:29 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Process the sve-max-vq property.
|
|
|
|
* Note that we know from the above that no bit above
|
|
|
|
* sve-max-vq is currently set.
|
|
|
|
*/
|
|
|
|
if (cpu->sve_max_vq != 0) {
|
|
|
|
max_vq = cpu->sve_max_vq;
|
|
|
|
|
|
|
|
if (!test_bit(max_vq - 1, cpu->sve_vq_map) &&
|
|
|
|
test_bit(max_vq - 1, cpu->sve_vq_init)) {
|
|
|
|
error_setg(errp, "cannot disable sve%d", max_vq * 128);
|
|
|
|
error_append_hint(errp, "The maximum vector length must be "
|
|
|
|
"enabled, sve-max-vq=%d (%d bits)\n",
|
|
|
|
max_vq, max_vq * 128);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set all bits not explicitly set within sve-max-vq. */
|
|
|
|
bitmap_complement(tmp, cpu->sve_vq_init, max_vq);
|
|
|
|
bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We should know what max-vq is now. Also, as we're done
|
|
|
|
* manipulating sve-vq-map, we ensure any bits above max-vq
|
|
|
|
* are clear, just in case anybody looks.
|
|
|
|
*/
|
|
|
|
assert(max_vq != 0);
|
|
|
|
bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq);
|
|
|
|
|
2019-10-31 17:27:33 +03:00
|
|
|
if (kvm_enabled()) {
|
|
|
|
/* Ensure the set of lengths matches what KVM supports. */
|
|
|
|
bitmap_xor(tmp, cpu->sve_vq_map, kvm_supported, max_vq);
|
|
|
|
if (!bitmap_empty(tmp, max_vq)) {
|
|
|
|
vq = find_last_bit(tmp, max_vq) + 1;
|
|
|
|
if (test_bit(vq - 1, cpu->sve_vq_map)) {
|
|
|
|
if (cpu->sve_max_vq) {
|
|
|
|
error_setg(errp, "cannot set sve-max-vq=%d",
|
|
|
|
cpu->sve_max_vq);
|
|
|
|
error_append_hint(errp, "This KVM host does not support "
|
|
|
|
"the vector length %d-bits.\n",
|
|
|
|
vq * 128);
|
|
|
|
error_append_hint(errp, "It may not be possible to use "
|
|
|
|
"sve-max-vq with this KVM host. Try "
|
|
|
|
"using only sve<N> properties.\n");
|
|
|
|
} else {
|
|
|
|
error_setg(errp, "cannot enable sve%d", vq * 128);
|
|
|
|
error_append_hint(errp, "This KVM host does not support "
|
|
|
|
"the vector length %d-bits.\n",
|
|
|
|
vq * 128);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
error_setg(errp, "cannot disable sve%d", vq * 128);
|
|
|
|
error_append_hint(errp, "The KVM host requires all "
|
|
|
|
"supported vector lengths smaller "
|
|
|
|
"than %d bits to also be enabled.\n",
|
|
|
|
max_vq * 128);
|
|
|
|
}
|
target/arm/cpu64: max cpu: Introduce sve<N> properties
Introduce cpu properties to give fine control over SVE vector lengths.
We introduce a property for each valid length up to the current
maximum supported, which is 2048-bits. The properties are named, e.g.
sve128, sve256, sve384, sve512, ..., where the number is the number of
bits. See the updates to docs/arm-cpu-features.rst for a description
of the semantics and for example uses.
Note, as sve-max-vq is still present and we'd like to be able to
support qmp_query_cpu_model_expansion with guests launched with e.g.
-cpu max,sve-max-vq=8 on their command lines, then we do allow
sve-max-vq and sve<N> properties to be provided at the same time, but
this is not recommended, and is why sve-max-vq is not mentioned in the
document. If sve-max-vq is provided then it enables all lengths smaller
than and including the max and disables all lengths larger. It also has
the side-effect that no larger lengths may be enabled and that the max
itself cannot be disabled. Smaller non-power-of-two lengths may,
however, be disabled, e.g. -cpu max,sve-max-vq=4,sve384=off provides a
guest the vector lengths 128, 256, and 512 bits.
This patch has been co-authored with Richard Henderson, who reworked
the target/arm/cpu64.c changes in order to push all the validation and
auto-enabling/disabling steps into the finalizer, resulting in a nice
LOC reduction.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-31 17:27:29 +03:00
|
|
|
return;
|
|
|
|
}
|
2019-10-31 17:27:33 +03:00
|
|
|
} else {
|
|
|
|
/* Ensure all required powers-of-two are enabled. */
|
|
|
|
for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
|
|
|
|
if (!test_bit(vq - 1, cpu->sve_vq_map)) {
|
|
|
|
error_setg(errp, "cannot disable sve%d", vq * 128);
|
|
|
|
error_append_hint(errp, "sve%d is required as it "
|
|
|
|
"is a power-of-two length smaller than "
|
|
|
|
"the maximum, sve%d\n",
|
|
|
|
vq * 128, max_vq * 128);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
target/arm/cpu64: max cpu: Introduce sve<N> properties
Introduce cpu properties to give fine control over SVE vector lengths.
We introduce a property for each valid length up to the current
maximum supported, which is 2048-bits. The properties are named, e.g.
sve128, sve256, sve384, sve512, ..., where the number is the number of
bits. See the updates to docs/arm-cpu-features.rst for a description
of the semantics and for example uses.
Note, as sve-max-vq is still present and we'd like to be able to
support qmp_query_cpu_model_expansion with guests launched with e.g.
-cpu max,sve-max-vq=8 on their command lines, then we do allow
sve-max-vq and sve<N> properties to be provided at the same time, but
this is not recommended, and is why sve-max-vq is not mentioned in the
document. If sve-max-vq is provided then it enables all lengths smaller
than and including the max and disables all lengths larger. It also has
the side-effect that no larger lengths may be enabled and that the max
itself cannot be disabled. Smaller non-power-of-two lengths may,
however, be disabled, e.g. -cpu max,sve-max-vq=4,sve384=off provides a
guest the vector lengths 128, 256, and 512 bits.
This patch has been co-authored with Richard Henderson, who reworked
the target/arm/cpu64.c changes in order to push all the validation and
auto-enabling/disabling steps into the finalizer, resulting in a nice
LOC reduction.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-31 17:27:29 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Now that we validated all our vector lengths, the only question
|
|
|
|
* left to answer is if we even want SVE at all.
|
|
|
|
*/
|
|
|
|
if (!cpu_isar_feature(aa64_sve, cpu)) {
|
|
|
|
error_setg(errp, "cannot enable sve%d", max_vq * 128);
|
|
|
|
error_append_hint(errp, "SVE must be enabled to enable vector "
|
|
|
|
"lengths.\n");
|
|
|
|
error_append_hint(errp, "Add sve=on to the CPU property list.\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* From now on sve_max_vq is the actual maximum supported length. */
|
|
|
|
cpu->sve_max_vq = max_vq;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
|
|
|
|
{
|
|
|
|
uint32_t bitnum;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We allow vq == ARM_MAX_VQ + 1 to be input because the caller may want
|
|
|
|
* to find the maximum vq enabled, which may be ARM_MAX_VQ, but this
|
|
|
|
* function always returns the next smaller than the input.
|
|
|
|
*/
|
|
|
|
assert(vq && vq <= ARM_MAX_VQ + 1);
|
|
|
|
|
|
|
|
bitnum = find_last_bit(cpu->sve_vq_map, vq - 1);
|
|
|
|
return bitnum == vq - 1 ? 0 : bitnum + 1;
|
|
|
|
}
|
|
|
|
|
2019-10-31 17:27:28 +03:00
|
|
|
static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
|
|
|
|
void *opaque, Error **errp)
|
2018-08-16 16:05:28 +03:00
|
|
|
{
|
|
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
2019-10-31 17:27:28 +03:00
|
|
|
uint32_t value;
|
|
|
|
|
|
|
|
/* All vector lengths are disabled when SVE is off. */
|
|
|
|
if (!cpu_isar_feature(aa64_sve, cpu)) {
|
|
|
|
value = 0;
|
|
|
|
} else {
|
|
|
|
value = cpu->sve_max_vq;
|
|
|
|
}
|
|
|
|
visit_type_uint32(v, name, &value, errp);
|
2018-08-16 16:05:28 +03:00
|
|
|
}
|
|
|
|
|
2019-10-31 17:27:28 +03:00
|
|
|
static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
|
|
|
|
void *opaque, Error **errp)
|
2018-08-16 16:05:28 +03:00
|
|
|
{
|
|
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
Error *err = NULL;
|
2019-10-31 17:27:33 +03:00
|
|
|
uint32_t max_vq;
|
|
|
|
|
|
|
|
visit_type_uint32(v, name, &max_vq, &err);
|
|
|
|
if (err) {
|
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
|
|
|
}
|
2018-08-16 16:05:28 +03:00
|
|
|
|
2019-10-31 17:27:33 +03:00
|
|
|
if (kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
|
|
|
|
error_setg(errp, "cannot set sve-max-vq");
|
|
|
|
error_append_hint(errp, "SVE not supported by KVM on this host\n");
|
|
|
|
return;
|
|
|
|
}
|
2018-08-16 16:05:28 +03:00
|
|
|
|
2019-10-31 17:27:33 +03:00
|
|
|
if (max_vq == 0 || max_vq > ARM_MAX_VQ) {
|
|
|
|
error_setg(errp, "unsupported SVE vector length");
|
|
|
|
error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n",
|
2018-08-16 16:05:28 +03:00
|
|
|
ARM_MAX_VQ);
|
2019-10-31 17:27:33 +03:00
|
|
|
return;
|
2018-08-16 16:05:28 +03:00
|
|
|
}
|
2019-10-31 17:27:33 +03:00
|
|
|
|
|
|
|
cpu->sve_max_vq = max_vq;
|
2018-08-16 16:05:28 +03:00
|
|
|
}
|
|
|
|
|
target/arm/cpu64: max cpu: Introduce sve<N> properties
Introduce cpu properties to give fine control over SVE vector lengths.
We introduce a property for each valid length up to the current
maximum supported, which is 2048-bits. The properties are named, e.g.
sve128, sve256, sve384, sve512, ..., where the number is the number of
bits. See the updates to docs/arm-cpu-features.rst for a description
of the semantics and for example uses.
Note, as sve-max-vq is still present and we'd like to be able to
support qmp_query_cpu_model_expansion with guests launched with e.g.
-cpu max,sve-max-vq=8 on their command lines, then we do allow
sve-max-vq and sve<N> properties to be provided at the same time, but
this is not recommended, and is why sve-max-vq is not mentioned in the
document. If sve-max-vq is provided then it enables all lengths smaller
than and including the max and disables all lengths larger. It also has
the side-effect that no larger lengths may be enabled and that the max
itself cannot be disabled. Smaller non-power-of-two lengths may,
however, be disabled, e.g. -cpu max,sve-max-vq=4,sve384=off provides a
guest the vector lengths 128, 256, and 512 bits.
This patch has been co-authored with Richard Henderson, who reworked
the target/arm/cpu64.c changes in order to push all the validation and
auto-enabling/disabling steps into the finalizer, resulting in a nice
LOC reduction.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-31 17:27:29 +03:00
|
|
|
static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name,
|
|
|
|
void *opaque, Error **errp)
|
|
|
|
{
|
|
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
uint32_t vq = atoi(&name[3]) / 128;
|
|
|
|
bool value;
|
|
|
|
|
|
|
|
/* All vector lengths are disabled when SVE is off. */
|
|
|
|
if (!cpu_isar_feature(aa64_sve, cpu)) {
|
|
|
|
value = false;
|
|
|
|
} else {
|
|
|
|
value = test_bit(vq - 1, cpu->sve_vq_map);
|
|
|
|
}
|
|
|
|
visit_type_bool(v, name, &value, errp);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
|
|
|
|
void *opaque, Error **errp)
|
|
|
|
{
|
|
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
uint32_t vq = atoi(&name[3]) / 128;
|
|
|
|
Error *err = NULL;
|
|
|
|
bool value;
|
|
|
|
|
|
|
|
visit_type_bool(v, name, &value, &err);
|
|
|
|
if (err) {
|
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2019-10-31 17:27:33 +03:00
|
|
|
if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
|
|
|
|
error_setg(errp, "cannot enable %s", name);
|
|
|
|
error_append_hint(errp, "SVE not supported by KVM on this host\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
target/arm/cpu64: max cpu: Introduce sve<N> properties
Introduce cpu properties to give fine control over SVE vector lengths.
We introduce a property for each valid length up to the current
maximum supported, which is 2048-bits. The properties are named, e.g.
sve128, sve256, sve384, sve512, ..., where the number is the number of
bits. See the updates to docs/arm-cpu-features.rst for a description
of the semantics and for example uses.
Note, as sve-max-vq is still present and we'd like to be able to
support qmp_query_cpu_model_expansion with guests launched with e.g.
-cpu max,sve-max-vq=8 on their command lines, then we do allow
sve-max-vq and sve<N> properties to be provided at the same time, but
this is not recommended, and is why sve-max-vq is not mentioned in the
document. If sve-max-vq is provided then it enables all lengths smaller
than and including the max and disables all lengths larger. It also has
the side-effect that no larger lengths may be enabled and that the max
itself cannot be disabled. Smaller non-power-of-two lengths may,
however, be disabled, e.g. -cpu max,sve-max-vq=4,sve384=off provides a
guest the vector lengths 128, 256, and 512 bits.
This patch has been co-authored with Richard Henderson, who reworked
the target/arm/cpu64.c changes in order to push all the validation and
auto-enabling/disabling steps into the finalizer, resulting in a nice
LOC reduction.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-31 17:27:29 +03:00
|
|
|
if (value) {
|
|
|
|
set_bit(vq - 1, cpu->sve_vq_map);
|
|
|
|
} else {
|
|
|
|
clear_bit(vq - 1, cpu->sve_vq_map);
|
|
|
|
}
|
|
|
|
set_bit(vq - 1, cpu->sve_vq_init);
|
|
|
|
}
|
|
|
|
|
2019-10-31 17:27:28 +03:00
|
|
|
static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name,
|
|
|
|
void *opaque, Error **errp)
|
|
|
|
{
|
|
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
bool value = cpu_isar_feature(aa64_sve, cpu);
|
|
|
|
|
|
|
|
visit_type_bool(v, name, &value, errp);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
|
|
|
|
void *opaque, Error **errp)
|
|
|
|
{
|
|
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
Error *err = NULL;
|
|
|
|
bool value;
|
|
|
|
uint64_t t;
|
|
|
|
|
|
|
|
visit_type_bool(v, name, &value, &err);
|
|
|
|
if (err) {
|
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2019-10-31 17:27:31 +03:00
|
|
|
if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
|
|
|
|
error_setg(errp, "'sve' feature not supported by KVM on this host");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2019-10-31 17:27:28 +03:00
|
|
|
t = cpu->isar.id_aa64pfr0;
|
|
|
|
t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
|
|
|
|
cpu->isar.id_aa64pfr0 = t;
|
|
|
|
}
|
|
|
|
|
2019-10-31 17:27:34 +03:00
|
|
|
void aarch64_add_sve_properties(Object *obj)
|
|
|
|
{
|
|
|
|
uint32_t vq;
|
|
|
|
|
|
|
|
object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
|
|
|
|
cpu_arm_set_sve, NULL, NULL, &error_fatal);
|
|
|
|
|
|
|
|
for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
|
|
|
|
char name[8];
|
|
|
|
sprintf(name, "sve%d", vq * 128);
|
|
|
|
object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
|
|
|
|
cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-03-09 20:09:44 +03:00
|
|
|
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
|
|
|
|
* otherwise, a CPU with as many features enabled as our emulation supports.
|
|
|
|
* The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
|
|
|
|
* this only needs to handle 64 bits.
|
|
|
|
*/
|
|
|
|
static void aarch64_max_initfn(Object *obj)
|
|
|
|
{
|
|
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
|
|
|
|
if (kvm_enabled()) {
|
|
|
|
kvm_arm_set_cpu_features_from_host(cpu);
|
|
|
|
} else {
|
2019-10-31 17:27:34 +03:00
|
|
|
uint64_t t;
|
2018-10-24 09:50:16 +03:00
|
|
|
uint32_t u;
|
2018-03-09 20:09:44 +03:00
|
|
|
aarch64_a57_initfn(obj);
|
2018-10-24 09:50:16 +03:00
|
|
|
|
2019-08-15 11:46:41 +03:00
|
|
|
/*
|
|
|
|
* Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
|
|
|
|
* one and try to apply errata workarounds or use impdef features we
|
|
|
|
* don't provide.
|
|
|
|
* An IMPLEMENTER field of 0 means "reserved for software use";
|
|
|
|
* ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
|
|
|
|
* to see which features are present";
|
|
|
|
* the VARIANT, PARTNUM and REVISION fields are all implementation
|
|
|
|
* defined and we choose to define PARTNUM just in case guest
|
|
|
|
* code needs to distinguish this QEMU CPU from other software
|
|
|
|
* implementations, though this shouldn't be needed.
|
|
|
|
*/
|
|
|
|
t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
|
|
|
|
t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
|
|
|
|
t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
|
|
|
|
t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
|
|
|
|
t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
|
|
|
|
cpu->midr = t;
|
|
|
|
|
2018-10-24 09:50:16 +03:00
|
|
|
t = cpu->isar.id_aa64isar0;
|
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
|
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
|
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
|
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
|
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
|
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
|
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
|
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
|
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
|
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
|
2019-02-28 13:55:17 +03:00
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
|
2019-03-01 23:04:59 +03:00
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
|
2019-03-13 07:57:35 +03:00
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
|
2018-10-24 09:50:16 +03:00
|
|
|
cpu->isar.id_aa64isar0 = t;
|
|
|
|
|
|
|
|
t = cpu->isar.id_aa64isar1;
|
2019-02-21 21:17:46 +03:00
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
|
2018-10-24 09:50:16 +03:00
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
|
2019-01-21 13:23:13 +03:00
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */
|
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
|
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);
|
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
|
2019-03-01 23:04:53 +03:00
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
|
2019-03-01 23:04:54 +03:00
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
|
2019-03-01 23:05:01 +03:00
|
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
|
2018-10-24 09:50:16 +03:00
|
|
|
cpu->isar.id_aa64isar1 = t;
|
|
|
|
|
2018-10-24 09:50:17 +03:00
|
|
|
t = cpu->isar.id_aa64pfr0;
|
|
|
|
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
|
2018-10-24 09:50:17 +03:00
|
|
|
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
|
|
|
|
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
|
2018-10-24 09:50:17 +03:00
|
|
|
cpu->isar.id_aa64pfr0 = t;
|
|
|
|
|
2019-02-05 19:52:38 +03:00
|
|
|
t = cpu->isar.id_aa64pfr1;
|
|
|
|
t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
|
|
|
|
cpu->isar.id_aa64pfr1 = t;
|
|
|
|
|
2018-12-13 16:48:06 +03:00
|
|
|
t = cpu->isar.id_aa64mmfr1;
|
|
|
|
t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
|
2018-12-13 16:48:08 +03:00
|
|
|
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
|
2018-12-13 16:48:06 +03:00
|
|
|
cpu->isar.id_aa64mmfr1 = t;
|
|
|
|
|
2018-10-24 09:50:16 +03:00
|
|
|
/* Replicate the same data to the 32-bit id registers. */
|
|
|
|
u = cpu->isar.id_isar5;
|
|
|
|
u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
|
|
|
|
u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
|
|
|
|
u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
|
|
|
|
u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
|
|
|
|
u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
|
|
|
|
u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
|
|
|
|
cpu->isar.id_isar5 = u;
|
|
|
|
|
|
|
|
u = cpu->isar.id_isar6;
|
2019-02-21 21:17:46 +03:00
|
|
|
u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
|
2018-10-24 09:50:16 +03:00
|
|
|
u = FIELD_DP32(u, ID_ISAR6, DP, 1);
|
2019-02-28 13:55:17 +03:00
|
|
|
u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
|
2019-03-01 23:04:53 +03:00
|
|
|
u = FIELD_DP32(u, ID_ISAR6, SB, 1);
|
2019-03-01 23:04:54 +03:00
|
|
|
u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
|
2018-10-24 09:50:16 +03:00
|
|
|
cpu->isar.id_isar6 = u;
|
|
|
|
|
2018-10-24 09:50:17 +03:00
|
|
|
/*
|
|
|
|
* FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
|
|
|
|
* so do not set MVFR1.FPHP. Strictly speaking this is not legal,
|
|
|
|
* but it is also not legal to enable SVE without support for FP16,
|
|
|
|
* and enabling SVE in system mode is more useful in the short term.
|
2018-03-09 20:09:44 +03:00
|
|
|
*/
|
2018-10-24 09:50:17 +03:00
|
|
|
|
|
|
|
#ifdef CONFIG_USER_ONLY
|
2018-03-09 20:09:44 +03:00
|
|
|
/* For usermode -cpu max we can use a larger and more efficient DCZ
|
|
|
|
* blocksize since we don't have to follow what the hardware does.
|
2018-03-09 20:09:44 +03:00
|
|
|
*/
|
2018-03-09 20:09:44 +03:00
|
|
|
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
|
|
|
|
cpu->dcz_blocksize = 7; /* 512 bytes */
|
|
|
|
#endif
|
2018-03-09 20:09:44 +03:00
|
|
|
}
|
2019-10-31 17:27:31 +03:00
|
|
|
|
2019-10-31 17:27:34 +03:00
|
|
|
aarch64_add_sve_properties(obj);
|
2019-10-31 17:27:33 +03:00
|
|
|
object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
|
|
|
|
cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
|
2018-03-09 20:09:44 +03:00
|
|
|
}
|
|
|
|
|
2018-11-27 11:55:59 +03:00
|
|
|
struct ARMCPUInfo {
|
2013-09-03 23:12:07 +04:00
|
|
|
const char *name;
|
|
|
|
void (*initfn)(Object *obj);
|
|
|
|
void (*class_init)(ObjectClass *oc, void *data);
|
2018-11-27 11:55:59 +03:00
|
|
|
};
|
2013-09-03 23:12:07 +04:00
|
|
|
|
|
|
|
static const ARMCPUInfo aarch64_cpus[] = {
|
2014-04-15 22:18:44 +04:00
|
|
|
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
|
2015-05-15 05:22:55 +03:00
|
|
|
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
|
2018-10-11 05:19:29 +03:00
|
|
|
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
|
2018-03-09 20:09:44 +03:00
|
|
|
{ .name = "max", .initfn = aarch64_max_initfn },
|
2014-01-13 14:26:16 +04:00
|
|
|
{ .name = NULL }
|
2013-09-03 23:12:07 +04:00
|
|
|
};
|
|
|
|
|
2015-02-13 08:46:08 +03:00
|
|
|
static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
|
|
|
|
{
|
|
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
|
|
|
|
return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
|
|
|
|
{
|
|
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
|
|
|
|
/* At this time, this property is only allowed if KVM is enabled. This
|
|
|
|
* restriction allows us to avoid fixing up functionality that assumes a
|
|
|
|
* uniform execution state like do_interrupt.
|
|
|
|
*/
|
|
|
|
if (value == false) {
|
2019-08-02 15:25:26 +03:00
|
|
|
if (!kvm_enabled() || !kvm_arm_aarch32_supported(CPU(cpu))) {
|
|
|
|
error_setg(errp, "'aarch64' feature cannot be disabled "
|
|
|
|
"unless KVM is enabled and 32-bit EL1 "
|
|
|
|
"is supported");
|
|
|
|
return;
|
|
|
|
}
|
2015-02-13 08:46:08 +03:00
|
|
|
unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
|
|
|
} else {
|
|
|
|
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-09-03 23:12:07 +04:00
|
|
|
static void aarch64_cpu_initfn(Object *obj)
|
|
|
|
{
|
2015-02-13 08:46:08 +03:00
|
|
|
object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
|
|
|
|
aarch64_cpu_set_aarch64, NULL);
|
|
|
|
object_property_set_description(obj, "aarch64",
|
|
|
|
"Set on/off to enable/disable aarch64 "
|
|
|
|
"execution state ",
|
|
|
|
NULL);
|
2013-09-03 23:12:07 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void aarch64_cpu_finalizefn(Object *obj)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2015-12-03 15:14:41 +03:00
|
|
|
static gchar *aarch64_gdb_arch_name(CPUState *cs)
|
|
|
|
{
|
|
|
|
return g_strdup("aarch64");
|
|
|
|
}
|
|
|
|
|
2013-09-03 23:12:07 +04:00
|
|
|
static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-09-03 23:12:10 +04:00
|
|
|
CPUClass *cc = CPU_CLASS(oc);
|
|
|
|
|
2014-09-13 20:45:25 +04:00
|
|
|
cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
|
2013-09-03 23:12:11 +04:00
|
|
|
cc->gdb_read_register = aarch64_cpu_gdb_read_register;
|
|
|
|
cc->gdb_write_register = aarch64_cpu_gdb_write_register;
|
|
|
|
cc->gdb_num_core_regs = 34;
|
|
|
|
cc->gdb_core_xml_file = "aarch64-core.xml";
|
2015-12-03 15:14:41 +03:00
|
|
|
cc->gdb_arch_name = aarch64_gdb_arch_name;
|
2013-09-03 23:12:07 +04:00
|
|
|
}
|
|
|
|
|
2018-11-27 11:55:59 +03:00
|
|
|
static void aarch64_cpu_instance_init(Object *obj)
|
|
|
|
{
|
|
|
|
ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
|
|
|
|
|
|
|
|
acc->info->initfn(obj);
|
|
|
|
arm_cpu_post_init(obj);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cpu_register_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
|
|
|
|
|
|
|
|
acc->info = data;
|
|
|
|
}
|
|
|
|
|
2013-09-03 23:12:07 +04:00
|
|
|
static void aarch64_cpu_register(const ARMCPUInfo *info)
|
|
|
|
{
|
|
|
|
TypeInfo type_info = {
|
|
|
|
.parent = TYPE_AARCH64_CPU,
|
|
|
|
.instance_size = sizeof(ARMCPU),
|
2018-11-27 11:55:59 +03:00
|
|
|
.instance_init = aarch64_cpu_instance_init,
|
2013-09-03 23:12:07 +04:00
|
|
|
.class_size = sizeof(ARMCPUClass),
|
2018-11-27 11:55:59 +03:00
|
|
|
.class_init = info->class_init ?: cpu_register_class_init,
|
|
|
|
.class_data = (void *)info,
|
2013-09-03 23:12:07 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
|
|
|
|
type_register(&type_info);
|
|
|
|
g_free((void *)type_info.name);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo aarch64_cpu_type_info = {
|
|
|
|
.name = TYPE_AARCH64_CPU,
|
|
|
|
.parent = TYPE_ARM_CPU,
|
|
|
|
.instance_size = sizeof(ARMCPU),
|
|
|
|
.instance_init = aarch64_cpu_initfn,
|
|
|
|
.instance_finalize = aarch64_cpu_finalizefn,
|
|
|
|
.abstract = true,
|
|
|
|
.class_size = sizeof(AArch64CPUClass),
|
|
|
|
.class_init = aarch64_cpu_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void aarch64_cpu_register_types(void)
|
|
|
|
{
|
2014-01-13 14:26:16 +04:00
|
|
|
const ARMCPUInfo *info = aarch64_cpus;
|
2013-09-03 23:12:07 +04:00
|
|
|
|
|
|
|
type_register_static(&aarch64_cpu_type_info);
|
2014-01-13 14:26:16 +04:00
|
|
|
|
|
|
|
while (info->name) {
|
|
|
|
aarch64_cpu_register(info);
|
|
|
|
info++;
|
2013-09-03 23:12:07 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(aarch64_cpu_register_types)
|