target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# LoongArch instruction decode definitions.
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#
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# Copyright (c) 2021 Loongson Technology Corporation Limited
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#
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#
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# Fields
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#
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2022-06-06 15:42:57 +03:00
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%i14s2 10:s14 !function=shl_2
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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%sa2p1 15:2 !function=plus_1
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2022-06-06 15:43:05 +03:00
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%offs21 0:s5 10:16 !function=shl_2
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%offs16 10:s16 !function=shl_2
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%offs26 0:s10 10:16 !function=shl_2
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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#
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# Argument sets
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#
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2022-06-06 15:42:57 +03:00
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&i imm
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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&r_i rd imm
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2022-06-06 15:42:56 +03:00
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&rr rd rj
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2022-06-06 15:42:59 +03:00
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&rr_jk rj rk
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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&rrr rd rj rk
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&rr_i rd rj imm
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2022-06-06 15:42:57 +03:00
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&hint_r_i hint rj imm
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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&rrr_sa rd rj rk sa
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2022-06-06 15:42:56 +03:00
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&rr_ms_ls rd rj ms ls
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2022-06-06 15:43:00 +03:00
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&ff fd fj
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&fff fd fj fk
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&ffff fd fj fk fa
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2022-06-06 15:43:01 +03:00
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&cff_fcond cd fj fk fcond
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2022-06-06 15:43:03 +03:00
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&fffc fd fj fk ca
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&fr fd rj
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&rf rd fj
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&fcsrd_r fcsrd rj
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&r_fcsrs rd fcsrs
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&cf cd fj
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&fc fd cj
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&cr cd rj
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&rc rd cj
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2022-06-06 15:43:04 +03:00
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&frr fd rj rk
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&fr_i fd rj imm
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2022-06-06 15:43:05 +03:00
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&r_offs rj offs
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&c_offs cj offs
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&offs offs
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&rr_offs rj rd offs
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2022-06-06 15:43:15 +03:00
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&r_csr rd csr
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&rr_csr rd rj csr
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2022-06-06 15:43:17 +03:00
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&empty
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&i_rr imm rj rk
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2022-06-06 15:43:18 +03:00
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&cop_r_i cop rj imm
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&j_i rj imm
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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#
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# Formats
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#
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2022-06-06 15:42:57 +03:00
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@i15 .... ........ ..... imm:15 &i
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2022-06-06 15:42:56 +03:00
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@rr .... ........ ..... ..... rj:5 rd:5 &rr
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2022-06-06 15:42:59 +03:00
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@rr_jk .... ........ ..... rk:5 rj:5 ..... &rr_jk
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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@rrr .... ........ ..... rk:5 rj:5 rd:5 &rrr
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@r_i20 .... ... imm:s20 rd:5 &r_i
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target/loongarch: Add fixed point shift instruction translation
This includes:
- SLL.W, SRL.W, SRA.W, ROTR.W
- SLLI.W, SRLI.W, SRAI.W, ROTRI.W
- SLL.D, SRL.D, SRA.D, ROTR.D
- SLLI.D, SRLI.D, SRAI.D, ROTRI.D
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-6-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:55 +03:00
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@rr_ui5 .... ........ ..... imm:5 rj:5 rd:5 &rr_i
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@rr_ui6 .... ........ .... imm:6 rj:5 rd:5 &rr_i
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2022-06-06 15:43:18 +03:00
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@rr_ui8 .. ........ .... imm:8 rj:5 rd:5 &rr_i
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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@rr_i12 .... ...... imm:s12 rj:5 rd:5 &rr_i
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@rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i
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2022-06-06 15:42:57 +03:00
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@rr_i14s2 .... .... .............. rj:5 rd:5 &rr_i imm=%i14s2
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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@rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i
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2023-01-18 03:32:38 +03:00
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@rr_i16s2 .... .. ................ rj:5 rd:5 &rr_i imm=%offs16
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2022-06-06 15:42:57 +03:00
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@hint_r_i12 .... ...... imm:s12 rj:5 hint:5 &hint_r_i
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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@rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1
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2022-06-06 15:42:56 +03:00
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@rrr_sa2 .... ........ ... sa:2 rk:5 rj:5 rd:5 &rrr_sa
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@rrr_sa3 .... ........ .. sa:3 rk:5 rj:5 rd:5 &rrr_sa
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@rr_2bw .... ....... ms:5 . ls:5 rj:5 rd:5 &rr_ms_ls
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@rr_2bd .... ...... ms:6 ls:6 rj:5 rd:5 &rr_ms_ls
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2022-06-06 15:43:00 +03:00
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@ff .... ........ ..... ..... fj:5 fd:5 &ff
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@fff .... ........ ..... fk:5 fj:5 fd:5 &fff
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@ffff .... ........ fa:5 fk:5 fj:5 fd:5 &ffff
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2022-06-06 15:43:01 +03:00
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@cff_fcond .... ........ fcond:5 fk:5 fj:5 .. cd:3 &cff_fcond
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2022-06-06 15:43:03 +03:00
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@fffc .... ........ .. ca:3 fk:5 fj:5 fd:5 &fffc
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@fr .... ........ ..... ..... rj:5 fd:5 &fr
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@rf .... ........ ..... ..... fj:5 rd:5 &rf
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@fcsrd_r .... ........ ..... ..... rj:5 fcsrd:5 &fcsrd_r
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@r_fcsrs .... ........ ..... ..... fcsrs:5 rd:5 &r_fcsrs
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@cf .... ........ ..... ..... fj:5 .. cd:3 &cf
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@fc .... ........ ..... ..... .. cj:3 fd:5 &fc
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@cr .... ........ ..... ..... rj:5 .. cd:3 &cr
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@rc .... ........ ..... ..... .. cj:3 rd:5 &rc
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2022-06-06 15:43:04 +03:00
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@frr .... ........ ..... rk:5 rj:5 fd:5 &frr
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@fr_i12 .... ...... imm:s12 rj:5 fd:5 &fr_i
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2022-06-06 15:43:05 +03:00
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@r_offs21 .... .. ................ rj:5 ..... &r_offs offs=%offs21
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@c_offs21 .... .. ................ .. cj:3 ..... &c_offs offs=%offs21
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@offs26 .... .. .......................... &offs offs=%offs26
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@rr_offs16 .... .. ................ rj:5 rd:5 &rr_offs offs=%offs16
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2022-06-06 15:43:15 +03:00
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@r_csr .... .... csr:14 ..... rd:5 &r_csr
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@rr_csr .... .... csr:14 rj:5 rd:5 &rr_csr
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2022-06-06 15:43:17 +03:00
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@empty .... ........ ..... ..... ..... ..... &empty
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@i_rr ...... ...... ..... rk:5 rj:5 imm:5 &i_rr
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2022-06-06 15:43:18 +03:00
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@cop_r_i .... ...... imm:s12 rj:5 cop:5 &cop_r_i
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@j_i .... ........ .. imm:8 rj:5 ..... &j_i
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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#
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# Fixed point arithmetic operation instruction
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#
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add_w 0000 00000001 00000 ..... ..... ..... @rrr
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add_d 0000 00000001 00001 ..... ..... ..... @rrr
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sub_w 0000 00000001 00010 ..... ..... ..... @rrr
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sub_d 0000 00000001 00011 ..... ..... ..... @rrr
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slt 0000 00000001 00100 ..... ..... ..... @rrr
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sltu 0000 00000001 00101 ..... ..... ..... @rrr
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slti 0000 001000 ............ ..... ..... @rr_i12
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sltui 0000 001001 ............ ..... ..... @rr_i12
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nor 0000 00000001 01000 ..... ..... ..... @rrr
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and 0000 00000001 01001 ..... ..... ..... @rrr
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or 0000 00000001 01010 ..... ..... ..... @rrr
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xor 0000 00000001 01011 ..... ..... ..... @rrr
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orn 0000 00000001 01100 ..... ..... ..... @rrr
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andn 0000 00000001 01101 ..... ..... ..... @rrr
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mul_w 0000 00000001 11000 ..... ..... ..... @rrr
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mulh_w 0000 00000001 11001 ..... ..... ..... @rrr
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mulh_wu 0000 00000001 11010 ..... ..... ..... @rrr
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mul_d 0000 00000001 11011 ..... ..... ..... @rrr
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mulh_d 0000 00000001 11100 ..... ..... ..... @rrr
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mulh_du 0000 00000001 11101 ..... ..... ..... @rrr
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mulw_d_w 0000 00000001 11110 ..... ..... ..... @rrr
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mulw_d_wu 0000 00000001 11111 ..... ..... ..... @rrr
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div_w 0000 00000010 00000 ..... ..... ..... @rrr
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mod_w 0000 00000010 00001 ..... ..... ..... @rrr
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div_wu 0000 00000010 00010 ..... ..... ..... @rrr
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mod_wu 0000 00000010 00011 ..... ..... ..... @rrr
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div_d 0000 00000010 00100 ..... ..... ..... @rrr
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mod_d 0000 00000010 00101 ..... ..... ..... @rrr
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div_du 0000 00000010 00110 ..... ..... ..... @rrr
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mod_du 0000 00000010 00111 ..... ..... ..... @rrr
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alsl_w 0000 00000000 010 .. ..... ..... ..... @rrr_sa2p1
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alsl_wu 0000 00000000 011 .. ..... ..... ..... @rrr_sa2p1
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alsl_d 0000 00000010 110 .. ..... ..... ..... @rrr_sa2p1
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lu12i_w 0001 010 .................... ..... @r_i20
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lu32i_d 0001 011 .................... ..... @r_i20
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lu52i_d 0000 001100 ............ ..... ..... @rr_i12
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pcaddi 0001 100 .................... ..... @r_i20
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pcalau12i 0001 101 .................... ..... @r_i20
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pcaddu12i 0001 110 .................... ..... @r_i20
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pcaddu18i 0001 111 .................... ..... @r_i20
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addi_w 0000 001010 ............ ..... ..... @rr_i12
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addi_d 0000 001011 ............ ..... ..... @rr_i12
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addu16i_d 0001 00 ................ ..... ..... @rr_i16
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andi 0000 001101 ............ ..... ..... @rr_ui12
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ori 0000 001110 ............ ..... ..... @rr_ui12
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xori 0000 001111 ............ ..... ..... @rr_ui12
|
target/loongarch: Add fixed point shift instruction translation
This includes:
- SLL.W, SRL.W, SRA.W, ROTR.W
- SLLI.W, SRLI.W, SRAI.W, ROTRI.W
- SLL.D, SRL.D, SRA.D, ROTR.D
- SLLI.D, SRLI.D, SRAI.D, ROTRI.D
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-6-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:55 +03:00
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#
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# Fixed point shift operation instruction
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#
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sll_w 0000 00000001 01110 ..... ..... ..... @rrr
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srl_w 0000 00000001 01111 ..... ..... ..... @rrr
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sra_w 0000 00000001 10000 ..... ..... ..... @rrr
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sll_d 0000 00000001 10001 ..... ..... ..... @rrr
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srl_d 0000 00000001 10010 ..... ..... ..... @rrr
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sra_d 0000 00000001 10011 ..... ..... ..... @rrr
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rotr_w 0000 00000001 10110 ..... ..... ..... @rrr
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rotr_d 0000 00000001 10111 ..... ..... ..... @rrr
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slli_w 0000 00000100 00001 ..... ..... ..... @rr_ui5
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slli_d 0000 00000100 0001 ...... ..... ..... @rr_ui6
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srli_w 0000 00000100 01001 ..... ..... ..... @rr_ui5
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srli_d 0000 00000100 0101 ...... ..... ..... @rr_ui6
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srai_w 0000 00000100 10001 ..... ..... ..... @rr_ui5
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srai_d 0000 00000100 1001 ...... ..... ..... @rr_ui6
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rotri_w 0000 00000100 11001 ..... ..... ..... @rr_ui5
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rotri_d 0000 00000100 1101 ...... ..... ..... @rr_ui6
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2022-06-06 15:42:56 +03:00
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#
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# Fixed point bit operation instruction
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#
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ext_w_h 0000 00000000 00000 10110 ..... ..... @rr
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ext_w_b 0000 00000000 00000 10111 ..... ..... @rr
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clo_w 0000 00000000 00000 00100 ..... ..... @rr
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clz_w 0000 00000000 00000 00101 ..... ..... @rr
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cto_w 0000 00000000 00000 00110 ..... ..... @rr
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ctz_w 0000 00000000 00000 00111 ..... ..... @rr
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clo_d 0000 00000000 00000 01000 ..... ..... @rr
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clz_d 0000 00000000 00000 01001 ..... ..... @rr
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cto_d 0000 00000000 00000 01010 ..... ..... @rr
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ctz_d 0000 00000000 00000 01011 ..... ..... @rr
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revb_2h 0000 00000000 00000 01100 ..... ..... @rr
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revb_4h 0000 00000000 00000 01101 ..... ..... @rr
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revb_2w 0000 00000000 00000 01110 ..... ..... @rr
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revb_d 0000 00000000 00000 01111 ..... ..... @rr
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revh_2w 0000 00000000 00000 10000 ..... ..... @rr
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revh_d 0000 00000000 00000 10001 ..... ..... @rr
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bitrev_4b 0000 00000000 00000 10010 ..... ..... @rr
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bitrev_8b 0000 00000000 00000 10011 ..... ..... @rr
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bitrev_w 0000 00000000 00000 10100 ..... ..... @rr
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bitrev_d 0000 00000000 00000 10101 ..... ..... @rr
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bytepick_w 0000 00000000 100 .. ..... ..... ..... @rrr_sa2
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bytepick_d 0000 00000000 11 ... ..... ..... ..... @rrr_sa3
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maskeqz 0000 00000001 00110 ..... ..... ..... @rrr
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masknez 0000 00000001 00111 ..... ..... ..... @rrr
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bstrins_w 0000 0000011 ..... 0 ..... ..... ..... @rr_2bw
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bstrpick_w 0000 0000011 ..... 1 ..... ..... ..... @rr_2bw
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bstrins_d 0000 000010 ...... ...... ..... ..... @rr_2bd
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bstrpick_d 0000 000011 ...... ...... ..... ..... @rr_2bd
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2022-06-06 15:42:57 +03:00
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#
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# Fixed point load/store instruction
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#
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ld_b 0010 100000 ............ ..... ..... @rr_i12
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ld_h 0010 100001 ............ ..... ..... @rr_i12
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ld_w 0010 100010 ............ ..... ..... @rr_i12
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ld_d 0010 100011 ............ ..... ..... @rr_i12
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st_b 0010 100100 ............ ..... ..... @rr_i12
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st_h 0010 100101 ............ ..... ..... @rr_i12
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st_w 0010 100110 ............ ..... ..... @rr_i12
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st_d 0010 100111 ............ ..... ..... @rr_i12
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ld_bu 0010 101000 ............ ..... ..... @rr_i12
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ld_hu 0010 101001 ............ ..... ..... @rr_i12
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ld_wu 0010 101010 ............ ..... ..... @rr_i12
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ldx_b 0011 10000000 00000 ..... ..... ..... @rrr
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ldx_h 0011 10000000 01000 ..... ..... ..... @rrr
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ldx_w 0011 10000000 10000 ..... ..... ..... @rrr
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ldx_d 0011 10000000 11000 ..... ..... ..... @rrr
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stx_b 0011 10000001 00000 ..... ..... ..... @rrr
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stx_h 0011 10000001 01000 ..... ..... ..... @rrr
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stx_w 0011 10000001 10000 ..... ..... ..... @rrr
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stx_d 0011 10000001 11000 ..... ..... ..... @rrr
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ldx_bu 0011 10000010 00000 ..... ..... ..... @rrr
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ldx_hu 0011 10000010 01000 ..... ..... ..... @rrr
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ldx_wu 0011 10000010 10000 ..... ..... ..... @rrr
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preld 0010 101011 ............ ..... ..... @hint_r_i12
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dbar 0011 10000111 00100 ............... @i15
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ibar 0011 10000111 00101 ............... @i15
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ldptr_w 0010 0100 .............. ..... ..... @rr_i14s2
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stptr_w 0010 0101 .............. ..... ..... @rr_i14s2
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ldptr_d 0010 0110 .............. ..... ..... @rr_i14s2
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stptr_d 0010 0111 .............. ..... ..... @rr_i14s2
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ldgt_b 0011 10000111 10000 ..... ..... ..... @rrr
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ldgt_h 0011 10000111 10001 ..... ..... ..... @rrr
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ldgt_w 0011 10000111 10010 ..... ..... ..... @rrr
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ldgt_d 0011 10000111 10011 ..... ..... ..... @rrr
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ldle_b 0011 10000111 10100 ..... ..... ..... @rrr
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ldle_h 0011 10000111 10101 ..... ..... ..... @rrr
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ldle_w 0011 10000111 10110 ..... ..... ..... @rrr
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ldle_d 0011 10000111 10111 ..... ..... ..... @rrr
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stgt_b 0011 10000111 11000 ..... ..... ..... @rrr
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stgt_h 0011 10000111 11001 ..... ..... ..... @rrr
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stgt_w 0011 10000111 11010 ..... ..... ..... @rrr
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stgt_d 0011 10000111 11011 ..... ..... ..... @rrr
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stle_b 0011 10000111 11100 ..... ..... ..... @rrr
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stle_h 0011 10000111 11101 ..... ..... ..... @rrr
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stle_w 0011 10000111 11110 ..... ..... ..... @rrr
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stle_d 0011 10000111 11111 ..... ..... ..... @rrr
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2022-06-06 15:42:58 +03:00
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|
#
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|
# Fixed point atomic instruction
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#
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ll_w 0010 0000 .............. ..... ..... @rr_i14s2
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sc_w 0010 0001 .............. ..... ..... @rr_i14s2
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ll_d 0010 0010 .............. ..... ..... @rr_i14s2
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sc_d 0010 0011 .............. ..... ..... @rr_i14s2
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amswap_w 0011 10000110 00000 ..... ..... ..... @rrr
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amswap_d 0011 10000110 00001 ..... ..... ..... @rrr
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amadd_w 0011 10000110 00010 ..... ..... ..... @rrr
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amadd_d 0011 10000110 00011 ..... ..... ..... @rrr
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amand_w 0011 10000110 00100 ..... ..... ..... @rrr
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amand_d 0011 10000110 00101 ..... ..... ..... @rrr
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amor_w 0011 10000110 00110 ..... ..... ..... @rrr
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amor_d 0011 10000110 00111 ..... ..... ..... @rrr
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amxor_w 0011 10000110 01000 ..... ..... ..... @rrr
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amxor_d 0011 10000110 01001 ..... ..... ..... @rrr
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ammax_w 0011 10000110 01010 ..... ..... ..... @rrr
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ammax_d 0011 10000110 01011 ..... ..... ..... @rrr
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ammin_w 0011 10000110 01100 ..... ..... ..... @rrr
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ammin_d 0011 10000110 01101 ..... ..... ..... @rrr
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ammax_wu 0011 10000110 01110 ..... ..... ..... @rrr
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ammax_du 0011 10000110 01111 ..... ..... ..... @rrr
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ammin_wu 0011 10000110 10000 ..... ..... ..... @rrr
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ammin_du 0011 10000110 10001 ..... ..... ..... @rrr
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amswap_db_w 0011 10000110 10010 ..... ..... ..... @rrr
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amswap_db_d 0011 10000110 10011 ..... ..... ..... @rrr
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amadd_db_w 0011 10000110 10100 ..... ..... ..... @rrr
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amadd_db_d 0011 10000110 10101 ..... ..... ..... @rrr
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amand_db_w 0011 10000110 10110 ..... ..... ..... @rrr
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amand_db_d 0011 10000110 10111 ..... ..... ..... @rrr
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amor_db_w 0011 10000110 11000 ..... ..... ..... @rrr
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amor_db_d 0011 10000110 11001 ..... ..... ..... @rrr
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amxor_db_w 0011 10000110 11010 ..... ..... ..... @rrr
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amxor_db_d 0011 10000110 11011 ..... ..... ..... @rrr
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ammax_db_w 0011 10000110 11100 ..... ..... ..... @rrr
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ammax_db_d 0011 10000110 11101 ..... ..... ..... @rrr
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ammin_db_w 0011 10000110 11110 ..... ..... ..... @rrr
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ammin_db_d 0011 10000110 11111 ..... ..... ..... @rrr
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ammax_db_wu 0011 10000111 00000 ..... ..... ..... @rrr
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ammax_db_du 0011 10000111 00001 ..... ..... ..... @rrr
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ammin_db_wu 0011 10000111 00010 ..... ..... ..... @rrr
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ammin_db_du 0011 10000111 00011 ..... ..... ..... @rrr
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2022-06-06 15:42:59 +03:00
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|
#
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|
|
# Fixed point extra instruction
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|
|
#
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crc_w_b_w 0000 00000010 01000 ..... ..... ..... @rrr
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crc_w_h_w 0000 00000010 01001 ..... ..... ..... @rrr
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crc_w_w_w 0000 00000010 01010 ..... ..... ..... @rrr
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crc_w_d_w 0000 00000010 01011 ..... ..... ..... @rrr
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crcc_w_b_w 0000 00000010 01100 ..... ..... ..... @rrr
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crcc_w_h_w 0000 00000010 01101 ..... ..... ..... @rrr
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crcc_w_w_w 0000 00000010 01110 ..... ..... ..... @rrr
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crcc_w_d_w 0000 00000010 01111 ..... ..... ..... @rrr
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break 0000 00000010 10100 ............... @i15
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syscall 0000 00000010 10110 ............... @i15
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asrtle_d 0000 00000000 00010 ..... ..... 00000 @rr_jk
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asrtgt_d 0000 00000000 00011 ..... ..... 00000 @rr_jk
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2022-06-06 15:43:19 +03:00
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rdtimel_w 0000 00000000 00000 11000 ..... ..... @rr
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rdtimeh_w 0000 00000000 00000 11001 ..... ..... @rr
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rdtime_d 0000 00000000 00000 11010 ..... ..... @rr
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2022-06-06 15:42:59 +03:00
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cpucfg 0000 00000000 00000 11011 ..... ..... @rr
|
2022-06-06 15:43:00 +03:00
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#
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# Floating point arithmetic operation instruction
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#
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fadd_s 0000 00010000 00001 ..... ..... ..... @fff
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fadd_d 0000 00010000 00010 ..... ..... ..... @fff
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fsub_s 0000 00010000 00101 ..... ..... ..... @fff
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fsub_d 0000 00010000 00110 ..... ..... ..... @fff
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fmul_s 0000 00010000 01001 ..... ..... ..... @fff
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fmul_d 0000 00010000 01010 ..... ..... ..... @fff
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fdiv_s 0000 00010000 01101 ..... ..... ..... @fff
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fdiv_d 0000 00010000 01110 ..... ..... ..... @fff
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fmadd_s 0000 10000001 ..... ..... ..... ..... @ffff
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fmadd_d 0000 10000010 ..... ..... ..... ..... @ffff
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fmsub_s 0000 10000101 ..... ..... ..... ..... @ffff
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fmsub_d 0000 10000110 ..... ..... ..... ..... @ffff
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fnmadd_s 0000 10001001 ..... ..... ..... ..... @ffff
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fnmadd_d 0000 10001010 ..... ..... ..... ..... @ffff
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fnmsub_s 0000 10001101 ..... ..... ..... ..... @ffff
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fnmsub_d 0000 10001110 ..... ..... ..... ..... @ffff
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|
|
fmax_s 0000 00010000 10001 ..... ..... ..... @fff
|
|
|
|
|
fmax_d 0000 00010000 10010 ..... ..... ..... @fff
|
|
|
|
|
fmin_s 0000 00010000 10101 ..... ..... ..... @fff
|
|
|
|
|
fmin_d 0000 00010000 10110 ..... ..... ..... @fff
|
|
|
|
|
fmaxa_s 0000 00010000 11001 ..... ..... ..... @fff
|
|
|
|
|
fmaxa_d 0000 00010000 11010 ..... ..... ..... @fff
|
|
|
|
|
fmina_s 0000 00010000 11101 ..... ..... ..... @fff
|
|
|
|
|
fmina_d 0000 00010000 11110 ..... ..... ..... @fff
|
|
|
|
|
fabs_s 0000 00010001 01000 00001 ..... ..... @ff
|
|
|
|
|
fabs_d 0000 00010001 01000 00010 ..... ..... @ff
|
|
|
|
|
fneg_s 0000 00010001 01000 00101 ..... ..... @ff
|
|
|
|
|
fneg_d 0000 00010001 01000 00110 ..... ..... @ff
|
|
|
|
|
fsqrt_s 0000 00010001 01000 10001 ..... ..... @ff
|
|
|
|
|
fsqrt_d 0000 00010001 01000 10010 ..... ..... @ff
|
|
|
|
|
frecip_s 0000 00010001 01000 10101 ..... ..... @ff
|
|
|
|
|
frecip_d 0000 00010001 01000 10110 ..... ..... @ff
|
|
|
|
|
frsqrt_s 0000 00010001 01000 11001 ..... ..... @ff
|
|
|
|
|
frsqrt_d 0000 00010001 01000 11010 ..... ..... @ff
|
|
|
|
|
fscaleb_s 0000 00010001 00001 ..... ..... ..... @fff
|
|
|
|
|
fscaleb_d 0000 00010001 00010 ..... ..... ..... @fff
|
|
|
|
|
flogb_s 0000 00010001 01000 01001 ..... ..... @ff
|
|
|
|
|
flogb_d 0000 00010001 01000 01010 ..... ..... @ff
|
|
|
|
|
fcopysign_s 0000 00010001 00101 ..... ..... ..... @fff
|
|
|
|
|
fcopysign_d 0000 00010001 00110 ..... ..... ..... @fff
|
|
|
|
|
fclass_s 0000 00010001 01000 01101 ..... ..... @ff
|
|
|
|
|
fclass_d 0000 00010001 01000 01110 ..... ..... @ff
|
2022-06-06 15:43:01 +03:00
|
|
|
|
|
|
|
|
#
|
|
|
|
|
# Floating point compare instruction
|
|
|
|
|
#
|
|
|
|
|
fcmp_cond_s 0000 11000001 ..... ..... ..... 00 ... @cff_fcond
|
|
|
|
|
fcmp_cond_d 0000 11000010 ..... ..... ..... 00 ... @cff_fcond
|
2022-06-06 15:43:02 +03:00
|
|
|
|
|
|
|
|
#
|
|
|
|
|
# Floating point conversion instruction
|
|
|
|
|
#
|
|
|
|
|
fcvt_s_d 0000 00010001 10010 00110 ..... ..... @ff
|
|
|
|
|
fcvt_d_s 0000 00010001 10010 01001 ..... ..... @ff
|
|
|
|
|
ftintrm_w_s 0000 00010001 10100 00001 ..... ..... @ff
|
|
|
|
|
ftintrm_w_d 0000 00010001 10100 00010 ..... ..... @ff
|
|
|
|
|
ftintrm_l_s 0000 00010001 10100 01001 ..... ..... @ff
|
|
|
|
|
ftintrm_l_d 0000 00010001 10100 01010 ..... ..... @ff
|
|
|
|
|
ftintrp_w_s 0000 00010001 10100 10001 ..... ..... @ff
|
|
|
|
|
ftintrp_w_d 0000 00010001 10100 10010 ..... ..... @ff
|
|
|
|
|
ftintrp_l_s 0000 00010001 10100 11001 ..... ..... @ff
|
|
|
|
|
ftintrp_l_d 0000 00010001 10100 11010 ..... ..... @ff
|
|
|
|
|
ftintrz_w_s 0000 00010001 10101 00001 ..... ..... @ff
|
|
|
|
|
ftintrz_w_d 0000 00010001 10101 00010 ..... ..... @ff
|
|
|
|
|
ftintrz_l_s 0000 00010001 10101 01001 ..... ..... @ff
|
|
|
|
|
ftintrz_l_d 0000 00010001 10101 01010 ..... ..... @ff
|
|
|
|
|
ftintrne_w_s 0000 00010001 10101 10001 ..... ..... @ff
|
|
|
|
|
ftintrne_w_d 0000 00010001 10101 10010 ..... ..... @ff
|
|
|
|
|
ftintrne_l_s 0000 00010001 10101 11001 ..... ..... @ff
|
|
|
|
|
ftintrne_l_d 0000 00010001 10101 11010 ..... ..... @ff
|
|
|
|
|
ftint_w_s 0000 00010001 10110 00001 ..... ..... @ff
|
|
|
|
|
ftint_w_d 0000 00010001 10110 00010 ..... ..... @ff
|
|
|
|
|
ftint_l_s 0000 00010001 10110 01001 ..... ..... @ff
|
|
|
|
|
ftint_l_d 0000 00010001 10110 01010 ..... ..... @ff
|
|
|
|
|
ffint_s_w 0000 00010001 11010 00100 ..... ..... @ff
|
|
|
|
|
ffint_s_l 0000 00010001 11010 00110 ..... ..... @ff
|
|
|
|
|
ffint_d_w 0000 00010001 11010 01000 ..... ..... @ff
|
|
|
|
|
ffint_d_l 0000 00010001 11010 01010 ..... ..... @ff
|
|
|
|
|
frint_s 0000 00010001 11100 10001 ..... ..... @ff
|
|
|
|
|
frint_d 0000 00010001 11100 10010 ..... ..... @ff
|
2022-06-06 15:43:03 +03:00
|
|
|
|
|
|
|
|
#
|
|
|
|
|
# Floating point move instruction
|
|
|
|
|
#
|
|
|
|
|
fmov_s 0000 00010001 01001 00101 ..... ..... @ff
|
|
|
|
|
fmov_d 0000 00010001 01001 00110 ..... ..... @ff
|
|
|
|
|
fsel 0000 11010000 00 ... ..... ..... ..... @fffc
|
|
|
|
|
movgr2fr_w 0000 00010001 01001 01001 ..... ..... @fr
|
|
|
|
|
movgr2fr_d 0000 00010001 01001 01010 ..... ..... @fr
|
|
|
|
|
movgr2frh_w 0000 00010001 01001 01011 ..... ..... @fr
|
|
|
|
|
movfr2gr_s 0000 00010001 01001 01101 ..... ..... @rf
|
|
|
|
|
movfr2gr_d 0000 00010001 01001 01110 ..... ..... @rf
|
|
|
|
|
movfrh2gr_s 0000 00010001 01001 01111 ..... ..... @rf
|
|
|
|
|
movgr2fcsr 0000 00010001 01001 10000 ..... ..... @fcsrd_r
|
|
|
|
|
movfcsr2gr 0000 00010001 01001 10010 ..... ..... @r_fcsrs
|
|
|
|
|
movfr2cf 0000 00010001 01001 10100 ..... 00 ... @cf
|
|
|
|
|
movcf2fr 0000 00010001 01001 10101 00 ... ..... @fc
|
|
|
|
|
movgr2cf 0000 00010001 01001 10110 ..... 00 ... @cr
|
|
|
|
|
movcf2gr 0000 00010001 01001 10111 00 ... ..... @rc
|
2022-06-06 15:43:04 +03:00
|
|
|
|
|
|
|
|
#
|
|
|
|
|
# Floating point load/store instruction
|
|
|
|
|
#
|
|
|
|
|
fld_s 0010 101100 ............ ..... ..... @fr_i12
|
|
|
|
|
fst_s 0010 101101 ............ ..... ..... @fr_i12
|
|
|
|
|
fld_d 0010 101110 ............ ..... ..... @fr_i12
|
|
|
|
|
fst_d 0010 101111 ............ ..... ..... @fr_i12
|
|
|
|
|
fldx_s 0011 10000011 00000 ..... ..... ..... @frr
|
|
|
|
|
fldx_d 0011 10000011 01000 ..... ..... ..... @frr
|
|
|
|
|
fstx_s 0011 10000011 10000 ..... ..... ..... @frr
|
|
|
|
|
fstx_d 0011 10000011 11000 ..... ..... ..... @frr
|
|
|
|
|
fldgt_s 0011 10000111 01000 ..... ..... ..... @frr
|
|
|
|
|
fldgt_d 0011 10000111 01001 ..... ..... ..... @frr
|
|
|
|
|
fldle_s 0011 10000111 01010 ..... ..... ..... @frr
|
|
|
|
|
fldle_d 0011 10000111 01011 ..... ..... ..... @frr
|
|
|
|
|
fstgt_s 0011 10000111 01100 ..... ..... ..... @frr
|
|
|
|
|
fstgt_d 0011 10000111 01101 ..... ..... ..... @frr
|
|
|
|
|
fstle_s 0011 10000111 01110 ..... ..... ..... @frr
|
|
|
|
|
fstle_d 0011 10000111 01111 ..... ..... ..... @frr
|
2022-06-06 15:43:05 +03:00
|
|
|
|
|
|
|
|
#
|
|
|
|
|
# Branch instructions
|
|
|
|
|
#
|
|
|
|
|
beqz 0100 00 ................ ..... ..... @r_offs21
|
|
|
|
|
bnez 0100 01 ................ ..... ..... @r_offs21
|
|
|
|
|
bceqz 0100 10 ................ 00 ... ..... @c_offs21
|
|
|
|
|
bcnez 0100 10 ................ 01 ... ..... @c_offs21
|
2023-01-18 03:32:38 +03:00
|
|
|
jirl 0100 11 ................ ..... ..... @rr_i16s2
|
2022-06-06 15:43:05 +03:00
|
|
|
b 0101 00 .......................... @offs26
|
|
|
|
|
bl 0101 01 .......................... @offs26
|
|
|
|
|
beq 0101 10 ................ ..... ..... @rr_offs16
|
|
|
|
|
bne 0101 11 ................ ..... ..... @rr_offs16
|
|
|
|
|
blt 0110 00 ................ ..... ..... @rr_offs16
|
|
|
|
|
bge 0110 01 ................ ..... ..... @rr_offs16
|
|
|
|
|
bltu 0110 10 ................ ..... ..... @rr_offs16
|
|
|
|
|
bgeu 0110 11 ................ ..... ..... @rr_offs16
|
2022-06-06 15:43:15 +03:00
|
|
|
|
|
|
|
|
#
|
|
|
|
|
# Core instructions
|
|
|
|
|
#
|
|
|
|
|
{
|
|
|
|
|
csrrd 0000 0100 .............. 00000 ..... @r_csr
|
|
|
|
|
csrwr 0000 0100 .............. 00001 ..... @r_csr
|
|
|
|
|
csrxchg 0000 0100 .............. ..... ..... @rr_csr
|
|
|
|
|
}
|
2022-06-06 15:43:16 +03:00
|
|
|
|
|
|
|
|
iocsrrd_b 0000 01100100 10000 00000 ..... ..... @rr
|
|
|
|
|
iocsrrd_h 0000 01100100 10000 00001 ..... ..... @rr
|
|
|
|
|
iocsrrd_w 0000 01100100 10000 00010 ..... ..... @rr
|
|
|
|
|
iocsrrd_d 0000 01100100 10000 00011 ..... ..... @rr
|
|
|
|
|
iocsrwr_b 0000 01100100 10000 00100 ..... ..... @rr
|
|
|
|
|
iocsrwr_h 0000 01100100 10000 00101 ..... ..... @rr
|
|
|
|
|
iocsrwr_w 0000 01100100 10000 00110 ..... ..... @rr
|
|
|
|
|
iocsrwr_d 0000 01100100 10000 00111 ..... ..... @rr
|
2022-06-06 15:43:17 +03:00
|
|
|
tlbsrch 0000 01100100 10000 01010 00000 00000 @empty
|
|
|
|
|
tlbrd 0000 01100100 10000 01011 00000 00000 @empty
|
|
|
|
|
tlbwr 0000 01100100 10000 01100 00000 00000 @empty
|
|
|
|
|
tlbfill 0000 01100100 10000 01101 00000 00000 @empty
|
|
|
|
|
tlbclr 0000 01100100 10000 01000 00000 00000 @empty
|
|
|
|
|
tlbflush 0000 01100100 10000 01001 00000 00000 @empty
|
|
|
|
|
invtlb 0000 01100100 10011 ..... ..... ..... @i_rr
|
2022-06-06 15:43:18 +03:00
|
|
|
cacop 0000 011000 ............ ..... ..... @cop_r_i
|
|
|
|
|
lddir 0000 01100100 00 ........ ..... ..... @rr_ui8
|
|
|
|
|
ldpte 0000 01100100 01 ........ ..... 00000 @j_i
|
|
|
|
|
ertn 0000 01100100 10000 01110 00000 00000 @empty
|
|
|
|
|
idle 0000 01100100 10001 ............... @i15
|
|
|
|
|
dbcl 0000 00000010 10101 ............... @i15
|
2023-05-04 15:27:30 +03:00
|
|
|
|
2023-05-04 15:28:07 +03:00
|
|
|
#
|
|
|
|
|
# LSX Fields
|
|
|
|
|
#
|
|
|
|
|
|
|
|
|
|
%i9s3 10:s9 !function=shl_3
|
|
|
|
|
%i10s2 10:s10 !function=shl_2
|
|
|
|
|
%i11s1 10:s11 !function=shl_1
|
|
|
|
|
%i8s3 10:s8 !function=shl_3
|
|
|
|
|
%i8s2 10:s8 !function=shl_2
|
|
|
|
|
%i8s1 10:s8 !function=shl_1
|
|
|
|
|
|
2023-05-04 15:27:30 +03:00
|
|
|
#
|
|
|
|
|
# LSX Argument sets
|
|
|
|
|
#
|
|
|
|
|
|
2023-05-04 15:27:32 +03:00
|
|
|
&vv vd vj
|
2023-05-04 15:28:03 +03:00
|
|
|
&cv cd vj
|
2023-05-04 15:27:30 +03:00
|
|
|
&vvv vd vj vk
|
2023-05-04 15:27:31 +03:00
|
|
|
&vv_i vd vj imm
|
2023-05-04 15:27:59 +03:00
|
|
|
&vvvv vd vj vk va
|
2023-05-04 15:28:02 +03:00
|
|
|
&vvv_fcond vd vj vk fcond
|
2023-05-04 15:28:04 +03:00
|
|
|
&vr_i vd rj imm
|
|
|
|
|
&rv_i rd vj imm
|
|
|
|
|
&vr vd rj
|
2023-05-04 15:28:05 +03:00
|
|
|
&vvr vd vj rk
|
2023-05-04 15:28:07 +03:00
|
|
|
&vrr vd rj rk
|
|
|
|
|
&vr_ii vd rj imm imm2
|
2023-05-04 15:28:08 +03:00
|
|
|
&v_i vd imm
|
2023-05-04 15:27:30 +03:00
|
|
|
|
|
|
|
|
#
|
|
|
|
|
# LSX Formats
|
|
|
|
|
#
|
2023-05-04 15:27:32 +03:00
|
|
|
@vv .... ........ ..... ..... vj:5 vd:5 &vv
|
2023-05-04 15:28:03 +03:00
|
|
|
@cv .... ........ ..... ..... vj:5 .. cd:3 &cv
|
2023-05-04 15:27:30 +03:00
|
|
|
@vvv .... ........ ..... vk:5 vj:5 vd:5 &vvv
|
2023-05-04 15:28:05 +03:00
|
|
|
@vv_ui1 .... ........ ..... .... imm:1 vj:5 vd:5 &vv_i
|
|
|
|
|
@vv_ui2 .... ........ ..... ... imm:2 vj:5 vd:5 &vv_i
|
2023-05-04 15:27:43 +03:00
|
|
|
@vv_ui3 .... ........ ..... .. imm:3 vj:5 vd:5 &vv_i
|
|
|
|
|
@vv_ui4 .... ........ ..... . imm:4 vj:5 vd:5 &vv_i
|
2023-05-04 15:27:31 +03:00
|
|
|
@vv_ui5 .... ........ ..... imm:5 vj:5 vd:5 &vv_i
|
2023-05-04 15:27:43 +03:00
|
|
|
@vv_ui6 .... ........ .... imm:6 vj:5 vd:5 &vv_i
|
2023-05-04 15:27:51 +03:00
|
|
|
@vv_ui7 .... ........ ... imm:7 vj:5 vd:5 &vv_i
|
2023-05-04 15:27:47 +03:00
|
|
|
@vv_ui8 .... ........ .. imm:8 vj:5 vd:5 &vv_i
|
2023-05-04 15:27:39 +03:00
|
|
|
@vv_i5 .... ........ ..... imm:s5 vj:5 vd:5 &vv_i
|
2023-05-04 15:27:59 +03:00
|
|
|
@vvvv .... ........ va:5 vk:5 vj:5 vd:5 &vvvv
|
2023-05-04 15:28:02 +03:00
|
|
|
@vvv_fcond .... ........ fcond:5 vk:5 vj:5 vd:5 &vvv_fcond
|
2023-05-04 15:28:04 +03:00
|
|
|
@vr_ui4 .... ........ ..... . imm:4 rj:5 vd:5 &vr_i
|
|
|
|
|
@vr_ui3 .... ........ ..... .. imm:3 rj:5 vd:5 &vr_i
|
|
|
|
|
@vr_ui2 .... ........ ..... ... imm:2 rj:5 vd:5 &vr_i
|
|
|
|
|
@vr_ui1 .... ........ ..... .... imm:1 rj:5 vd:5 &vr_i
|
|
|
|
|
@rv_ui4 .... ........ ..... . imm:4 vj:5 rd:5 &rv_i
|
|
|
|
|
@rv_ui3 .... ........ ..... .. imm:3 vj:5 rd:5 &rv_i
|
|
|
|
|
@rv_ui2 .... ........ ..... ... imm:2 vj:5 rd:5 &rv_i
|
|
|
|
|
@rv_ui1 .... ........ ..... .... imm:1 vj:5 rd:5 &rv_i
|
|
|
|
|
@vr .... ........ ..... ..... rj:5 vd:5 &vr
|
2023-05-04 15:28:05 +03:00
|
|
|
@vvr .... ........ ..... rk:5 vj:5 vd:5 &vvr
|
2023-05-04 15:28:07 +03:00
|
|
|
@vr_i9 .... ........ . ......... rj:5 vd:5 &vr_i imm=%i9s3
|
|
|
|
|
@vr_i10 .... ........ .......... rj:5 vd:5 &vr_i imm=%i10s2
|
|
|
|
|
@vr_i11 .... ....... ........... rj:5 vd:5 &vr_i imm=%i11s1
|
|
|
|
|
@vr_i12 .... ...... imm:s12 rj:5 vd:5 &vr_i
|
|
|
|
|
@vr_i8i1 .... ........ . imm2:1 ........ rj:5 vd:5 &vr_ii imm=%i8s3
|
|
|
|
|
@vr_i8i2 .... ........ imm2:2 ........ rj:5 vd:5 &vr_ii imm=%i8s2
|
|
|
|
|
@vr_i8i3 .... ....... imm2:3 ........ rj:5 vd:5 &vr_ii imm=%i8s1
|
|
|
|
|
@vr_i8i4 .... ...... imm2:4 imm:s8 rj:5 vd:5 &vr_ii
|
|
|
|
|
@vrr .... ........ ..... rk:5 rj:5 vd:5 &vrr
|
2023-05-04 15:28:08 +03:00
|
|
|
@v_i13 .... ........ .. imm:13 vd:5 &v_i
|
2023-05-04 15:27:30 +03:00
|
|
|
|
|
|
|
|
vadd_b 0111 00000000 10100 ..... ..... ..... @vvv
|
|
|
|
|
vadd_h 0111 00000000 10101 ..... ..... ..... @vvv
|
|
|
|
|
vadd_w 0111 00000000 10110 ..... ..... ..... @vvv
|
|
|
|
|
vadd_d 0111 00000000 10111 ..... ..... ..... @vvv
|
|
|
|
|
vadd_q 0111 00010010 11010 ..... ..... ..... @vvv
|
|
|
|
|
vsub_b 0111 00000000 11000 ..... ..... ..... @vvv
|
|
|
|
|
vsub_h 0111 00000000 11001 ..... ..... ..... @vvv
|
|
|
|
|
vsub_w 0111 00000000 11010 ..... ..... ..... @vvv
|
|
|
|
|
vsub_d 0111 00000000 11011 ..... ..... ..... @vvv
|
|
|
|
|
vsub_q 0111 00010010 11011 ..... ..... ..... @vvv
|
2023-05-04 15:27:31 +03:00
|
|
|
|
|
|
|
|
vaddi_bu 0111 00101000 10100 ..... ..... ..... @vv_ui5
|
|
|
|
|
vaddi_hu 0111 00101000 10101 ..... ..... ..... @vv_ui5
|
|
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|
vaddi_wu 0111 00101000 10110 ..... ..... ..... @vv_ui5
|
|
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|
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vaddi_du 0111 00101000 10111 ..... ..... ..... @vv_ui5
|
|
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|
vsubi_bu 0111 00101000 11000 ..... ..... ..... @vv_ui5
|
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|
vsubi_hu 0111 00101000 11001 ..... ..... ..... @vv_ui5
|
|
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|
|
vsubi_wu 0111 00101000 11010 ..... ..... ..... @vv_ui5
|
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|
vsubi_du 0111 00101000 11011 ..... ..... ..... @vv_ui5
|
2023-05-04 15:27:32 +03:00
|
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vneg_b 0111 00101001 11000 01100 ..... ..... @vv
|
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vneg_h 0111 00101001 11000 01101 ..... ..... @vv
|
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vneg_w 0111 00101001 11000 01110 ..... ..... @vv
|
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vneg_d 0111 00101001 11000 01111 ..... ..... @vv
|
2023-05-04 15:27:33 +03:00
|
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vsadd_b 0111 00000100 01100 ..... ..... ..... @vvv
|
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vsadd_h 0111 00000100 01101 ..... ..... ..... @vvv
|
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vsadd_w 0111 00000100 01110 ..... ..... ..... @vvv
|
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vsadd_d 0111 00000100 01111 ..... ..... ..... @vvv
|
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vsadd_bu 0111 00000100 10100 ..... ..... ..... @vvv
|
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vsadd_hu 0111 00000100 10101 ..... ..... ..... @vvv
|
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|
vsadd_wu 0111 00000100 10110 ..... ..... ..... @vvv
|
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vsadd_du 0111 00000100 10111 ..... ..... ..... @vvv
|
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vssub_b 0111 00000100 10000 ..... ..... ..... @vvv
|
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vssub_h 0111 00000100 10001 ..... ..... ..... @vvv
|
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vssub_w 0111 00000100 10010 ..... ..... ..... @vvv
|
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vssub_d 0111 00000100 10011 ..... ..... ..... @vvv
|
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vssub_bu 0111 00000100 11000 ..... ..... ..... @vvv
|
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|
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vssub_hu 0111 00000100 11001 ..... ..... ..... @vvv
|
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vssub_wu 0111 00000100 11010 ..... ..... ..... @vvv
|
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vssub_du 0111 00000100 11011 ..... ..... ..... @vvv
|
2023-05-04 15:27:34 +03:00
|
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vhaddw_h_b 0111 00000101 01000 ..... ..... ..... @vvv
|
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vhaddw_w_h 0111 00000101 01001 ..... ..... ..... @vvv
|
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vhaddw_d_w 0111 00000101 01010 ..... ..... ..... @vvv
|
|
|
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vhaddw_q_d 0111 00000101 01011 ..... ..... ..... @vvv
|
|
|
|
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vhaddw_hu_bu 0111 00000101 10000 ..... ..... ..... @vvv
|
|
|
|
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vhaddw_wu_hu 0111 00000101 10001 ..... ..... ..... @vvv
|
|
|
|
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vhaddw_du_wu 0111 00000101 10010 ..... ..... ..... @vvv
|
|
|
|
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vhaddw_qu_du 0111 00000101 10011 ..... ..... ..... @vvv
|
|
|
|
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vhsubw_h_b 0111 00000101 01100 ..... ..... ..... @vvv
|
|
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|
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vhsubw_w_h 0111 00000101 01101 ..... ..... ..... @vvv
|
|
|
|
|
vhsubw_d_w 0111 00000101 01110 ..... ..... ..... @vvv
|
|
|
|
|
vhsubw_q_d 0111 00000101 01111 ..... ..... ..... @vvv
|
|
|
|
|
vhsubw_hu_bu 0111 00000101 10100 ..... ..... ..... @vvv
|
|
|
|
|
vhsubw_wu_hu 0111 00000101 10101 ..... ..... ..... @vvv
|
|
|
|
|
vhsubw_du_wu 0111 00000101 10110 ..... ..... ..... @vvv
|
|
|
|
|
vhsubw_qu_du 0111 00000101 10111 ..... ..... ..... @vvv
|
2023-05-04 15:27:35 +03:00
|
|
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|
|
vaddwev_h_b 0111 00000001 11100 ..... ..... ..... @vvv
|
|
|
|
|
vaddwev_w_h 0111 00000001 11101 ..... ..... ..... @vvv
|
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|
|
|
vaddwev_d_w 0111 00000001 11110 ..... ..... ..... @vvv
|
|
|
|
|
vaddwev_q_d 0111 00000001 11111 ..... ..... ..... @vvv
|
|
|
|
|
vaddwod_h_b 0111 00000010 00100 ..... ..... ..... @vvv
|
|
|
|
|
vaddwod_w_h 0111 00000010 00101 ..... ..... ..... @vvv
|
|
|
|
|
vaddwod_d_w 0111 00000010 00110 ..... ..... ..... @vvv
|
|
|
|
|
vaddwod_q_d 0111 00000010 00111 ..... ..... ..... @vvv
|
|
|
|
|
vsubwev_h_b 0111 00000010 00000 ..... ..... ..... @vvv
|
|
|
|
|
vsubwev_w_h 0111 00000010 00001 ..... ..... ..... @vvv
|
|
|
|
|
vsubwev_d_w 0111 00000010 00010 ..... ..... ..... @vvv
|
|
|
|
|
vsubwev_q_d 0111 00000010 00011 ..... ..... ..... @vvv
|
|
|
|
|
vsubwod_h_b 0111 00000010 01000 ..... ..... ..... @vvv
|
|
|
|
|
vsubwod_w_h 0111 00000010 01001 ..... ..... ..... @vvv
|
|
|
|
|
vsubwod_d_w 0111 00000010 01010 ..... ..... ..... @vvv
|
|
|
|
|
vsubwod_q_d 0111 00000010 01011 ..... ..... ..... @vvv
|
|
|
|
|
|
|
|
|
|
vaddwev_h_bu 0111 00000010 11100 ..... ..... ..... @vvv
|
|
|
|
|
vaddwev_w_hu 0111 00000010 11101 ..... ..... ..... @vvv
|
|
|
|
|
vaddwev_d_wu 0111 00000010 11110 ..... ..... ..... @vvv
|
|
|
|
|
vaddwev_q_du 0111 00000010 11111 ..... ..... ..... @vvv
|
|
|
|
|
vaddwod_h_bu 0111 00000011 00100 ..... ..... ..... @vvv
|
|
|
|
|
vaddwod_w_hu 0111 00000011 00101 ..... ..... ..... @vvv
|
|
|
|
|
vaddwod_d_wu 0111 00000011 00110 ..... ..... ..... @vvv
|
|
|
|
|
vaddwod_q_du 0111 00000011 00111 ..... ..... ..... @vvv
|
|
|
|
|
vsubwev_h_bu 0111 00000011 00000 ..... ..... ..... @vvv
|
|
|
|
|
vsubwev_w_hu 0111 00000011 00001 ..... ..... ..... @vvv
|
|
|
|
|
vsubwev_d_wu 0111 00000011 00010 ..... ..... ..... @vvv
|
|
|
|
|
vsubwev_q_du 0111 00000011 00011 ..... ..... ..... @vvv
|
|
|
|
|
vsubwod_h_bu 0111 00000011 01000 ..... ..... ..... @vvv
|
|
|
|
|
vsubwod_w_hu 0111 00000011 01001 ..... ..... ..... @vvv
|
|
|
|
|
vsubwod_d_wu 0111 00000011 01010 ..... ..... ..... @vvv
|
|
|
|
|
vsubwod_q_du 0111 00000011 01011 ..... ..... ..... @vvv
|
|
|
|
|
|
|
|
|
|
vaddwev_h_bu_b 0111 00000011 11100 ..... ..... ..... @vvv
|
|
|
|
|
vaddwev_w_hu_h 0111 00000011 11101 ..... ..... ..... @vvv
|
|
|
|
|
vaddwev_d_wu_w 0111 00000011 11110 ..... ..... ..... @vvv
|
|
|
|
|
vaddwev_q_du_d 0111 00000011 11111 ..... ..... ..... @vvv
|
|
|
|
|
vaddwod_h_bu_b 0111 00000100 00000 ..... ..... ..... @vvv
|
|
|
|
|
vaddwod_w_hu_h 0111 00000100 00001 ..... ..... ..... @vvv
|
|
|
|
|
vaddwod_d_wu_w 0111 00000100 00010 ..... ..... ..... @vvv
|
|
|
|
|
vaddwod_q_du_d 0111 00000100 00011 ..... ..... ..... @vvv
|
2023-05-04 15:27:36 +03:00
|
|
|
|
|
|
|
|
vavg_b 0111 00000110 01000 ..... ..... ..... @vvv
|
|
|
|
|
vavg_h 0111 00000110 01001 ..... ..... ..... @vvv
|
|
|
|
|
vavg_w 0111 00000110 01010 ..... ..... ..... @vvv
|
|
|
|
|
vavg_d 0111 00000110 01011 ..... ..... ..... @vvv
|
|
|
|
|
vavg_bu 0111 00000110 01100 ..... ..... ..... @vvv
|
|
|
|
|
vavg_hu 0111 00000110 01101 ..... ..... ..... @vvv
|
|
|
|
|
vavg_wu 0111 00000110 01110 ..... ..... ..... @vvv
|
|
|
|
|
vavg_du 0111 00000110 01111 ..... ..... ..... @vvv
|
|
|
|
|
vavgr_b 0111 00000110 10000 ..... ..... ..... @vvv
|
|
|
|
|
vavgr_h 0111 00000110 10001 ..... ..... ..... @vvv
|
|
|
|
|
vavgr_w 0111 00000110 10010 ..... ..... ..... @vvv
|
|
|
|
|
vavgr_d 0111 00000110 10011 ..... ..... ..... @vvv
|
|
|
|
|
vavgr_bu 0111 00000110 10100 ..... ..... ..... @vvv
|
|
|
|
|
vavgr_hu 0111 00000110 10101 ..... ..... ..... @vvv
|
|
|
|
|
vavgr_wu 0111 00000110 10110 ..... ..... ..... @vvv
|
|
|
|
|
vavgr_du 0111 00000110 10111 ..... ..... ..... @vvv
|
2023-05-04 15:27:37 +03:00
|
|
|
|
|
|
|
|
vabsd_b 0111 00000110 00000 ..... ..... ..... @vvv
|
|
|
|
|
vabsd_h 0111 00000110 00001 ..... ..... ..... @vvv
|
|
|
|
|
vabsd_w 0111 00000110 00010 ..... ..... ..... @vvv
|
|
|
|
|
vabsd_d 0111 00000110 00011 ..... ..... ..... @vvv
|
|
|
|
|
vabsd_bu 0111 00000110 00100 ..... ..... ..... @vvv
|
|
|
|
|
vabsd_hu 0111 00000110 00101 ..... ..... ..... @vvv
|
|
|
|
|
vabsd_wu 0111 00000110 00110 ..... ..... ..... @vvv
|
|
|
|
|
vabsd_du 0111 00000110 00111 ..... ..... ..... @vvv
|
2023-05-04 15:27:38 +03:00
|
|
|
|
|
|
|
|
vadda_b 0111 00000101 11000 ..... ..... ..... @vvv
|
|
|
|
|
vadda_h 0111 00000101 11001 ..... ..... ..... @vvv
|
|
|
|
|
vadda_w 0111 00000101 11010 ..... ..... ..... @vvv
|
|
|
|
|
vadda_d 0111 00000101 11011 ..... ..... ..... @vvv
|
2023-05-04 15:27:39 +03:00
|
|
|
|
|
|
|
|
vmax_b 0111 00000111 00000 ..... ..... ..... @vvv
|
|
|
|
|
vmax_h 0111 00000111 00001 ..... ..... ..... @vvv
|
|
|
|
|
vmax_w 0111 00000111 00010 ..... ..... ..... @vvv
|
|
|
|
|
vmax_d 0111 00000111 00011 ..... ..... ..... @vvv
|
|
|
|
|
vmaxi_b 0111 00101001 00000 ..... ..... ..... @vv_i5
|
|
|
|
|
vmaxi_h 0111 00101001 00001 ..... ..... ..... @vv_i5
|
|
|
|
|
vmaxi_w 0111 00101001 00010 ..... ..... ..... @vv_i5
|
|
|
|
|
vmaxi_d 0111 00101001 00011 ..... ..... ..... @vv_i5
|
|
|
|
|
vmax_bu 0111 00000111 01000 ..... ..... ..... @vvv
|
|
|
|
|
vmax_hu 0111 00000111 01001 ..... ..... ..... @vvv
|
|
|
|
|
vmax_wu 0111 00000111 01010 ..... ..... ..... @vvv
|
|
|
|
|
vmax_du 0111 00000111 01011 ..... ..... ..... @vvv
|
|
|
|
|
vmaxi_bu 0111 00101001 01000 ..... ..... ..... @vv_ui5
|
|
|
|
|
vmaxi_hu 0111 00101001 01001 ..... ..... ..... @vv_ui5
|
|
|
|
|
vmaxi_wu 0111 00101001 01010 ..... ..... ..... @vv_ui5
|
|
|
|
|
vmaxi_du 0111 00101001 01011 ..... ..... ..... @vv_ui5
|
|
|
|
|
|
|
|
|
|
vmin_b 0111 00000111 00100 ..... ..... ..... @vvv
|
|
|
|
|
vmin_h 0111 00000111 00101 ..... ..... ..... @vvv
|
|
|
|
|
vmin_w 0111 00000111 00110 ..... ..... ..... @vvv
|
|
|
|
|
vmin_d 0111 00000111 00111 ..... ..... ..... @vvv
|
|
|
|
|
vmini_b 0111 00101001 00100 ..... ..... ..... @vv_i5
|
|
|
|
|
vmini_h 0111 00101001 00101 ..... ..... ..... @vv_i5
|
|
|
|
|
vmini_w 0111 00101001 00110 ..... ..... ..... @vv_i5
|
|
|
|
|
vmini_d 0111 00101001 00111 ..... ..... ..... @vv_i5
|
|
|
|
|
vmin_bu 0111 00000111 01100 ..... ..... ..... @vvv
|
|
|
|
|
vmin_hu 0111 00000111 01101 ..... ..... ..... @vvv
|
|
|
|
|
vmin_wu 0111 00000111 01110 ..... ..... ..... @vvv
|
|
|
|
|
vmin_du 0111 00000111 01111 ..... ..... ..... @vvv
|
|
|
|
|
vmini_bu 0111 00101001 01100 ..... ..... ..... @vv_ui5
|
|
|
|
|
vmini_hu 0111 00101001 01101 ..... ..... ..... @vv_ui5
|
|
|
|
|
vmini_wu 0111 00101001 01110 ..... ..... ..... @vv_ui5
|
|
|
|
|
vmini_du 0111 00101001 01111 ..... ..... ..... @vv_ui5
|
2023-05-04 15:27:40 +03:00
|
|
|
|
|
|
|
|
vmul_b 0111 00001000 01000 ..... ..... ..... @vvv
|
|
|
|
|
vmul_h 0111 00001000 01001 ..... ..... ..... @vvv
|
|
|
|
|
vmul_w 0111 00001000 01010 ..... ..... ..... @vvv
|
|
|
|
|
vmul_d 0111 00001000 01011 ..... ..... ..... @vvv
|
|
|
|
|
vmuh_b 0111 00001000 01100 ..... ..... ..... @vvv
|
|
|
|
|
vmuh_h 0111 00001000 01101 ..... ..... ..... @vvv
|
|
|
|
|
vmuh_w 0111 00001000 01110 ..... ..... ..... @vvv
|
|
|
|
|
vmuh_d 0111 00001000 01111 ..... ..... ..... @vvv
|
|
|
|
|
vmuh_bu 0111 00001000 10000 ..... ..... ..... @vvv
|
|
|
|
|
vmuh_hu 0111 00001000 10001 ..... ..... ..... @vvv
|
|
|
|
|
vmuh_wu 0111 00001000 10010 ..... ..... ..... @vvv
|
|
|
|
|
vmuh_du 0111 00001000 10011 ..... ..... ..... @vvv
|
|
|
|
|
|
|
|
|
|
vmulwev_h_b 0111 00001001 00000 ..... ..... ..... @vvv
|
|
|
|
|
vmulwev_w_h 0111 00001001 00001 ..... ..... ..... @vvv
|
|
|
|
|
vmulwev_d_w 0111 00001001 00010 ..... ..... ..... @vvv
|
|
|
|
|
vmulwev_q_d 0111 00001001 00011 ..... ..... ..... @vvv
|
|
|
|
|
vmulwod_h_b 0111 00001001 00100 ..... ..... ..... @vvv
|
|
|
|
|
vmulwod_w_h 0111 00001001 00101 ..... ..... ..... @vvv
|
|
|
|
|
vmulwod_d_w 0111 00001001 00110 ..... ..... ..... @vvv
|
|
|
|
|
vmulwod_q_d 0111 00001001 00111 ..... ..... ..... @vvv
|
|
|
|
|
vmulwev_h_bu 0111 00001001 10000 ..... ..... ..... @vvv
|
|
|
|
|
vmulwev_w_hu 0111 00001001 10001 ..... ..... ..... @vvv
|
|
|
|
|
vmulwev_d_wu 0111 00001001 10010 ..... ..... ..... @vvv
|
|
|
|
|
vmulwev_q_du 0111 00001001 10011 ..... ..... ..... @vvv
|
|
|
|
|
vmulwod_h_bu 0111 00001001 10100 ..... ..... ..... @vvv
|
|
|
|
|
vmulwod_w_hu 0111 00001001 10101 ..... ..... ..... @vvv
|
|
|
|
|
vmulwod_d_wu 0111 00001001 10110 ..... ..... ..... @vvv
|
|
|
|
|
vmulwod_q_du 0111 00001001 10111 ..... ..... ..... @vvv
|
|
|
|
|
vmulwev_h_bu_b 0111 00001010 00000 ..... ..... ..... @vvv
|
|
|
|
|
vmulwev_w_hu_h 0111 00001010 00001 ..... ..... ..... @vvv
|
|
|
|
|
vmulwev_d_wu_w 0111 00001010 00010 ..... ..... ..... @vvv
|
|
|
|
|
vmulwev_q_du_d 0111 00001010 00011 ..... ..... ..... @vvv
|
|
|
|
|
vmulwod_h_bu_b 0111 00001010 00100 ..... ..... ..... @vvv
|
|
|
|
|
vmulwod_w_hu_h 0111 00001010 00101 ..... ..... ..... @vvv
|
|
|
|
|
vmulwod_d_wu_w 0111 00001010 00110 ..... ..... ..... @vvv
|
|
|
|
|
vmulwod_q_du_d 0111 00001010 00111 ..... ..... ..... @vvv
|
2023-05-04 15:27:41 +03:00
|
|
|
|
|
|
|
|
vmadd_b 0111 00001010 10000 ..... ..... ..... @vvv
|
|
|
|
|
vmadd_h 0111 00001010 10001 ..... ..... ..... @vvv
|
|
|
|
|
vmadd_w 0111 00001010 10010 ..... ..... ..... @vvv
|
|
|
|
|
vmadd_d 0111 00001010 10011 ..... ..... ..... @vvv
|
|
|
|
|
vmsub_b 0111 00001010 10100 ..... ..... ..... @vvv
|
|
|
|
|
vmsub_h 0111 00001010 10101 ..... ..... ..... @vvv
|
|
|
|
|
vmsub_w 0111 00001010 10110 ..... ..... ..... @vvv
|
|
|
|
|
vmsub_d 0111 00001010 10111 ..... ..... ..... @vvv
|
|
|
|
|
|
|
|
|
|
vmaddwev_h_b 0111 00001010 11000 ..... ..... ..... @vvv
|
|
|
|
|
vmaddwev_w_h 0111 00001010 11001 ..... ..... ..... @vvv
|
|
|
|
|
vmaddwev_d_w 0111 00001010 11010 ..... ..... ..... @vvv
|
|
|
|
|
vmaddwev_q_d 0111 00001010 11011 ..... ..... ..... @vvv
|
|
|
|
|
vmaddwod_h_b 0111 00001010 11100 ..... ..... ..... @vvv
|
|
|
|
|
vmaddwod_w_h 0111 00001010 11101 ..... ..... ..... @vvv
|
|
|
|
|
vmaddwod_d_w 0111 00001010 11110 ..... ..... ..... @vvv
|
|
|
|
|
vmaddwod_q_d 0111 00001010 11111 ..... ..... ..... @vvv
|
|
|
|
|
vmaddwev_h_bu 0111 00001011 01000 ..... ..... ..... @vvv
|
|
|
|
|
vmaddwev_w_hu 0111 00001011 01001 ..... ..... ..... @vvv
|
|
|
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vmaddwev_d_wu 0111 00001011 01010 ..... ..... ..... @vvv
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vmaddwev_q_du 0111 00001011 01011 ..... ..... ..... @vvv
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vmaddwod_h_bu 0111 00001011 01100 ..... ..... ..... @vvv
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vmaddwod_w_hu 0111 00001011 01101 ..... ..... ..... @vvv
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vmaddwod_d_wu 0111 00001011 01110 ..... ..... ..... @vvv
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vmaddwod_q_du 0111 00001011 01111 ..... ..... ..... @vvv
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vmaddwev_h_bu_b 0111 00001011 11000 ..... ..... ..... @vvv
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vmaddwev_w_hu_h 0111 00001011 11001 ..... ..... ..... @vvv
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vmaddwev_d_wu_w 0111 00001011 11010 ..... ..... ..... @vvv
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vmaddwev_q_du_d 0111 00001011 11011 ..... ..... ..... @vvv
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vmaddwod_h_bu_b 0111 00001011 11100 ..... ..... ..... @vvv
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vmaddwod_w_hu_h 0111 00001011 11101 ..... ..... ..... @vvv
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vmaddwod_d_wu_w 0111 00001011 11110 ..... ..... ..... @vvv
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vmaddwod_q_du_d 0111 00001011 11111 ..... ..... ..... @vvv
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2023-05-04 15:27:42 +03:00
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vdiv_b 0111 00001110 00000 ..... ..... ..... @vvv
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vdiv_h 0111 00001110 00001 ..... ..... ..... @vvv
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vdiv_w 0111 00001110 00010 ..... ..... ..... @vvv
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vdiv_d 0111 00001110 00011 ..... ..... ..... @vvv
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vdiv_bu 0111 00001110 01000 ..... ..... ..... @vvv
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vdiv_hu 0111 00001110 01001 ..... ..... ..... @vvv
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vdiv_wu 0111 00001110 01010 ..... ..... ..... @vvv
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vdiv_du 0111 00001110 01011 ..... ..... ..... @vvv
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vmod_b 0111 00001110 00100 ..... ..... ..... @vvv
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vmod_h 0111 00001110 00101 ..... ..... ..... @vvv
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vmod_w 0111 00001110 00110 ..... ..... ..... @vvv
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vmod_d 0111 00001110 00111 ..... ..... ..... @vvv
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vmod_bu 0111 00001110 01100 ..... ..... ..... @vvv
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vmod_hu 0111 00001110 01101 ..... ..... ..... @vvv
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vmod_wu 0111 00001110 01110 ..... ..... ..... @vvv
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vmod_du 0111 00001110 01111 ..... ..... ..... @vvv
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2023-05-04 15:27:43 +03:00
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vsat_b 0111 00110010 01000 01 ... ..... ..... @vv_ui3
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vsat_h 0111 00110010 01000 1 .... ..... ..... @vv_ui4
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vsat_w 0111 00110010 01001 ..... ..... ..... @vv_ui5
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vsat_d 0111 00110010 0101 ...... ..... ..... @vv_ui6
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vsat_bu 0111 00110010 10000 01 ... ..... ..... @vv_ui3
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vsat_hu 0111 00110010 10000 1 .... ..... ..... @vv_ui4
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vsat_wu 0111 00110010 10001 ..... ..... ..... @vv_ui5
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vsat_du 0111 00110010 1001 ...... ..... ..... @vv_ui6
|
2023-05-04 15:27:44 +03:00
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vexth_h_b 0111 00101001 11101 11000 ..... ..... @vv
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vexth_w_h 0111 00101001 11101 11001 ..... ..... @vv
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vexth_d_w 0111 00101001 11101 11010 ..... ..... @vv
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vexth_q_d 0111 00101001 11101 11011 ..... ..... @vv
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vexth_hu_bu 0111 00101001 11101 11100 ..... ..... @vv
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vexth_wu_hu 0111 00101001 11101 11101 ..... ..... @vv
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vexth_du_wu 0111 00101001 11101 11110 ..... ..... @vv
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vexth_qu_du 0111 00101001 11101 11111 ..... ..... @vv
|
2023-05-04 15:27:45 +03:00
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vsigncov_b 0111 00010010 11100 ..... ..... ..... @vvv
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vsigncov_h 0111 00010010 11101 ..... ..... ..... @vvv
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vsigncov_w 0111 00010010 11110 ..... ..... ..... @vvv
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vsigncov_d 0111 00010010 11111 ..... ..... ..... @vvv
|
2023-05-04 15:27:46 +03:00
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vmskltz_b 0111 00101001 11000 10000 ..... ..... @vv
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vmskltz_h 0111 00101001 11000 10001 ..... ..... @vv
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vmskltz_w 0111 00101001 11000 10010 ..... ..... @vv
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vmskltz_d 0111 00101001 11000 10011 ..... ..... @vv
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vmskgez_b 0111 00101001 11000 10100 ..... ..... @vv
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vmsknz_b 0111 00101001 11000 11000 ..... ..... @vv
|
2023-05-04 15:27:47 +03:00
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2023-05-04 15:28:08 +03:00
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vldi 0111 00111110 00 ............. ..... @v_i13
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2023-05-04 15:27:47 +03:00
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vand_v 0111 00010010 01100 ..... ..... ..... @vvv
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vor_v 0111 00010010 01101 ..... ..... ..... @vvv
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vxor_v 0111 00010010 01110 ..... ..... ..... @vvv
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vnor_v 0111 00010010 01111 ..... ..... ..... @vvv
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vandn_v 0111 00010010 10000 ..... ..... ..... @vvv
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vorn_v 0111 00010010 10001 ..... ..... ..... @vvv
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vandi_b 0111 00111101 00 ........ ..... ..... @vv_ui8
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vori_b 0111 00111101 01 ........ ..... ..... @vv_ui8
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vxori_b 0111 00111101 10 ........ ..... ..... @vv_ui8
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vnori_b 0111 00111101 11 ........ ..... ..... @vv_ui8
|
2023-05-04 15:27:48 +03:00
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vsll_b 0111 00001110 10000 ..... ..... ..... @vvv
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vsll_h 0111 00001110 10001 ..... ..... ..... @vvv
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vsll_w 0111 00001110 10010 ..... ..... ..... @vvv
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vsll_d 0111 00001110 10011 ..... ..... ..... @vvv
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vslli_b 0111 00110010 11000 01 ... ..... ..... @vv_ui3
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vslli_h 0111 00110010 11000 1 .... ..... ..... @vv_ui4
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vslli_w 0111 00110010 11001 ..... ..... ..... @vv_ui5
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vslli_d 0111 00110010 1101 ...... ..... ..... @vv_ui6
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vsrl_b 0111 00001110 10100 ..... ..... ..... @vvv
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vsrl_h 0111 00001110 10101 ..... ..... ..... @vvv
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vsrl_w 0111 00001110 10110 ..... ..... ..... @vvv
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vsrl_d 0111 00001110 10111 ..... ..... ..... @vvv
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vsrli_b 0111 00110011 00000 01 ... ..... ..... @vv_ui3
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vsrli_h 0111 00110011 00000 1 .... ..... ..... @vv_ui4
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vsrli_w 0111 00110011 00001 ..... ..... ..... @vv_ui5
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vsrli_d 0111 00110011 0001 ...... ..... ..... @vv_ui6
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vsra_b 0111 00001110 11000 ..... ..... ..... @vvv
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vsra_h 0111 00001110 11001 ..... ..... ..... @vvv
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vsra_w 0111 00001110 11010 ..... ..... ..... @vvv
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vsra_d 0111 00001110 11011 ..... ..... ..... @vvv
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vsrai_b 0111 00110011 01000 01 ... ..... ..... @vv_ui3
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vsrai_h 0111 00110011 01000 1 .... ..... ..... @vv_ui4
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vsrai_w 0111 00110011 01001 ..... ..... ..... @vv_ui5
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vsrai_d 0111 00110011 0101 ...... ..... ..... @vv_ui6
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vrotr_b 0111 00001110 11100 ..... ..... ..... @vvv
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vrotr_h 0111 00001110 11101 ..... ..... ..... @vvv
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vrotr_w 0111 00001110 11110 ..... ..... ..... @vvv
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vrotr_d 0111 00001110 11111 ..... ..... ..... @vvv
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vrotri_b 0111 00101010 00000 01 ... ..... ..... @vv_ui3
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vrotri_h 0111 00101010 00000 1 .... ..... ..... @vv_ui4
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vrotri_w 0111 00101010 00001 ..... ..... ..... @vv_ui5
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vrotri_d 0111 00101010 0001 ...... ..... ..... @vv_ui6
|
2023-05-04 15:27:49 +03:00
|
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vsllwil_h_b 0111 00110000 10000 01 ... ..... ..... @vv_ui3
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vsllwil_w_h 0111 00110000 10000 1 .... ..... ..... @vv_ui4
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vsllwil_d_w 0111 00110000 10001 ..... ..... ..... @vv_ui5
|
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vextl_q_d 0111 00110000 10010 00000 ..... ..... @vv
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vsllwil_hu_bu 0111 00110000 11000 01 ... ..... ..... @vv_ui3
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vsllwil_wu_hu 0111 00110000 11000 1 .... ..... ..... @vv_ui4
|
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vsllwil_du_wu 0111 00110000 11001 ..... ..... ..... @vv_ui5
|
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vextl_qu_du 0111 00110000 11010 00000 ..... ..... @vv
|
2023-05-04 15:27:50 +03:00
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vsrlr_b 0111 00001111 00000 ..... ..... ..... @vvv
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vsrlr_h 0111 00001111 00001 ..... ..... ..... @vvv
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vsrlr_w 0111 00001111 00010 ..... ..... ..... @vvv
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vsrlr_d 0111 00001111 00011 ..... ..... ..... @vvv
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vsrlri_b 0111 00101010 01000 01 ... ..... ..... @vv_ui3
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vsrlri_h 0111 00101010 01000 1 .... ..... ..... @vv_ui4
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vsrlri_w 0111 00101010 01001 ..... ..... ..... @vv_ui5
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vsrlri_d 0111 00101010 0101 ...... ..... ..... @vv_ui6
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vsrar_b 0111 00001111 00100 ..... ..... ..... @vvv
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vsrar_h 0111 00001111 00101 ..... ..... ..... @vvv
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vsrar_w 0111 00001111 00110 ..... ..... ..... @vvv
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vsrar_d 0111 00001111 00111 ..... ..... ..... @vvv
|
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vsrari_b 0111 00101010 10000 01 ... ..... ..... @vv_ui3
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vsrari_h 0111 00101010 10000 1 .... ..... ..... @vv_ui4
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vsrari_w 0111 00101010 10001 ..... ..... ..... @vv_ui5
|
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vsrari_d 0111 00101010 1001 ...... ..... ..... @vv_ui6
|
2023-05-04 15:27:51 +03:00
|
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vsrln_b_h 0111 00001111 01001 ..... ..... ..... @vvv
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vsrln_h_w 0111 00001111 01010 ..... ..... ..... @vvv
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vsrln_w_d 0111 00001111 01011 ..... ..... ..... @vvv
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vsran_b_h 0111 00001111 01101 ..... ..... ..... @vvv
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vsran_h_w 0111 00001111 01110 ..... ..... ..... @vvv
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vsran_w_d 0111 00001111 01111 ..... ..... ..... @vvv
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vsrlni_b_h 0111 00110100 00000 1 .... ..... ..... @vv_ui4
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vsrlni_h_w 0111 00110100 00001 ..... ..... ..... @vv_ui5
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vsrlni_w_d 0111 00110100 0001 ...... ..... ..... @vv_ui6
|
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vsrlni_d_q 0111 00110100 001 ....... ..... ..... @vv_ui7
|
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vsrani_b_h 0111 00110101 10000 1 .... ..... ..... @vv_ui4
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vsrani_h_w 0111 00110101 10001 ..... ..... ..... @vv_ui5
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vsrani_w_d 0111 00110101 1001 ...... ..... ..... @vv_ui6
|
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vsrani_d_q 0111 00110101 101 ....... ..... ..... @vv_ui7
|
2023-05-04 15:27:52 +03:00
|
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vsrlrn_b_h 0111 00001111 10001 ..... ..... ..... @vvv
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vsrlrn_h_w 0111 00001111 10010 ..... ..... ..... @vvv
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vsrlrn_w_d 0111 00001111 10011 ..... ..... ..... @vvv
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vsrarn_b_h 0111 00001111 10101 ..... ..... ..... @vvv
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vsrarn_h_w 0111 00001111 10110 ..... ..... ..... @vvv
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vsrarn_w_d 0111 00001111 10111 ..... ..... ..... @vvv
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vsrlrni_b_h 0111 00110100 01000 1 .... ..... ..... @vv_ui4
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vsrlrni_h_w 0111 00110100 01001 ..... ..... ..... @vv_ui5
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vsrlrni_w_d 0111 00110100 0101 ...... ..... ..... @vv_ui6
|
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vsrlrni_d_q 0111 00110100 011 ....... ..... ..... @vv_ui7
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vsrarni_b_h 0111 00110101 11000 1 .... ..... ..... @vv_ui4
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vsrarni_h_w 0111 00110101 11001 ..... ..... ..... @vv_ui5
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vsrarni_w_d 0111 00110101 1101 ...... ..... ..... @vv_ui6
|
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vsrarni_d_q 0111 00110101 111 ....... ..... ..... @vv_ui7
|
2023-05-04 15:27:53 +03:00
|
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vssrln_b_h 0111 00001111 11001 ..... ..... ..... @vvv
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vssrln_h_w 0111 00001111 11010 ..... ..... ..... @vvv
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vssrln_w_d 0111 00001111 11011 ..... ..... ..... @vvv
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vssran_b_h 0111 00001111 11101 ..... ..... ..... @vvv
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vssran_h_w 0111 00001111 11110 ..... ..... ..... @vvv
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vssran_w_d 0111 00001111 11111 ..... ..... ..... @vvv
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vssrln_bu_h 0111 00010000 01001 ..... ..... ..... @vvv
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vssrln_hu_w 0111 00010000 01010 ..... ..... ..... @vvv
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vssrln_wu_d 0111 00010000 01011 ..... ..... ..... @vvv
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vssran_bu_h 0111 00010000 01101 ..... ..... ..... @vvv
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vssran_hu_w 0111 00010000 01110 ..... ..... ..... @vvv
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vssran_wu_d 0111 00010000 01111 ..... ..... ..... @vvv
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vssrlni_b_h 0111 00110100 10000 1 .... ..... ..... @vv_ui4
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vssrlni_h_w 0111 00110100 10001 ..... ..... ..... @vv_ui5
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vssrlni_w_d 0111 00110100 1001 ...... ..... ..... @vv_ui6
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vssrlni_d_q 0111 00110100 101 ....... ..... ..... @vv_ui7
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vssrani_b_h 0111 00110110 00000 1 .... ..... ..... @vv_ui4
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vssrani_h_w 0111 00110110 00001 ..... ..... ..... @vv_ui5
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vssrani_w_d 0111 00110110 0001 ...... ..... ..... @vv_ui6
|
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vssrani_d_q 0111 00110110 001 ....... ..... ..... @vv_ui7
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vssrlni_bu_h 0111 00110100 11000 1 .... ..... ..... @vv_ui4
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vssrlni_hu_w 0111 00110100 11001 ..... ..... ..... @vv_ui5
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vssrlni_wu_d 0111 00110100 1101 ...... ..... ..... @vv_ui6
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vssrlni_du_q 0111 00110100 111 ....... ..... ..... @vv_ui7
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vssrani_bu_h 0111 00110110 01000 1 .... ..... ..... @vv_ui4
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vssrani_hu_w 0111 00110110 01001 ..... ..... ..... @vv_ui5
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vssrani_wu_d 0111 00110110 0101 ...... ..... ..... @vv_ui6
|
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vssrani_du_q 0111 00110110 011 ....... ..... ..... @vv_ui7
|
2023-05-04 15:27:54 +03:00
|
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vssrlrn_b_h 0111 00010000 00001 ..... ..... ..... @vvv
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vssrlrn_h_w 0111 00010000 00010 ..... ..... ..... @vvv
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vssrlrn_w_d 0111 00010000 00011 ..... ..... ..... @vvv
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vssrarn_b_h 0111 00010000 00101 ..... ..... ..... @vvv
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vssrarn_h_w 0111 00010000 00110 ..... ..... ..... @vvv
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vssrarn_w_d 0111 00010000 00111 ..... ..... ..... @vvv
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vssrlrn_bu_h 0111 00010000 10001 ..... ..... ..... @vvv
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vssrlrn_hu_w 0111 00010000 10010 ..... ..... ..... @vvv
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vssrlrn_wu_d 0111 00010000 10011 ..... ..... ..... @vvv
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vssrarn_bu_h 0111 00010000 10101 ..... ..... ..... @vvv
|
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vssrarn_hu_w 0111 00010000 10110 ..... ..... ..... @vvv
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vssrarn_wu_d 0111 00010000 10111 ..... ..... ..... @vvv
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vssrlrni_b_h 0111 00110101 00000 1 .... ..... ..... @vv_ui4
|
|
|
|
|
vssrlrni_h_w 0111 00110101 00001 ..... ..... ..... @vv_ui5
|
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|
vssrlrni_w_d 0111 00110101 0001 ...... ..... ..... @vv_ui6
|
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|
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|
vssrlrni_d_q 0111 00110101 001 ....... ..... ..... @vv_ui7
|
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|
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|
vssrarni_b_h 0111 00110110 10000 1 .... ..... ..... @vv_ui4
|
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|
|
|
vssrarni_h_w 0111 00110110 10001 ..... ..... ..... @vv_ui5
|
|
|
|
|
vssrarni_w_d 0111 00110110 1001 ...... ..... ..... @vv_ui6
|
|
|
|
|
vssrarni_d_q 0111 00110110 101 ....... ..... ..... @vv_ui7
|
|
|
|
|
vssrlrni_bu_h 0111 00110101 01000 1 .... ..... ..... @vv_ui4
|
|
|
|
|
vssrlrni_hu_w 0111 00110101 01001 ..... ..... ..... @vv_ui5
|
|
|
|
|
vssrlrni_wu_d 0111 00110101 0101 ...... ..... ..... @vv_ui6
|
|
|
|
|
vssrlrni_du_q 0111 00110101 011 ....... ..... ..... @vv_ui7
|
|
|
|
|
vssrarni_bu_h 0111 00110110 11000 1 .... ..... ..... @vv_ui4
|
|
|
|
|
vssrarni_hu_w 0111 00110110 11001 ..... ..... ..... @vv_ui5
|
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|
|
|
vssrarni_wu_d 0111 00110110 1101 ...... ..... ..... @vv_ui6
|
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|
|
|
vssrarni_du_q 0111 00110110 111 ....... ..... ..... @vv_ui7
|
2023-05-04 15:27:55 +03:00
|
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|
vclo_b 0111 00101001 11000 00000 ..... ..... @vv
|
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vclo_h 0111 00101001 11000 00001 ..... ..... @vv
|
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|
vclo_w 0111 00101001 11000 00010 ..... ..... @vv
|
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vclo_d 0111 00101001 11000 00011 ..... ..... @vv
|
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vclz_b 0111 00101001 11000 00100 ..... ..... @vv
|
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vclz_h 0111 00101001 11000 00101 ..... ..... @vv
|
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vclz_w 0111 00101001 11000 00110 ..... ..... @vv
|
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vclz_d 0111 00101001 11000 00111 ..... ..... @vv
|
2023-05-04 15:27:56 +03:00
|
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|
vpcnt_b 0111 00101001 11000 01000 ..... ..... @vv
|
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vpcnt_h 0111 00101001 11000 01001 ..... ..... @vv
|
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vpcnt_w 0111 00101001 11000 01010 ..... ..... @vv
|
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vpcnt_d 0111 00101001 11000 01011 ..... ..... @vv
|
2023-05-04 15:27:57 +03:00
|
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vbitclr_b 0111 00010000 11000 ..... ..... ..... @vvv
|
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vbitclr_h 0111 00010000 11001 ..... ..... ..... @vvv
|
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vbitclr_w 0111 00010000 11010 ..... ..... ..... @vvv
|
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vbitclr_d 0111 00010000 11011 ..... ..... ..... @vvv
|
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|
vbitclri_b 0111 00110001 00000 01 ... ..... ..... @vv_ui3
|
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|
|
|
vbitclri_h 0111 00110001 00000 1 .... ..... ..... @vv_ui4
|
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|
|
|
vbitclri_w 0111 00110001 00001 ..... ..... ..... @vv_ui5
|
|
|
|
|
vbitclri_d 0111 00110001 0001 ...... ..... ..... @vv_ui6
|
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|
|
vbitset_b 0111 00010000 11100 ..... ..... ..... @vvv
|
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|
vbitset_h 0111 00010000 11101 ..... ..... ..... @vvv
|
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|
vbitset_w 0111 00010000 11110 ..... ..... ..... @vvv
|
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|
vbitset_d 0111 00010000 11111 ..... ..... ..... @vvv
|
|
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|
|
vbitseti_b 0111 00110001 01000 01 ... ..... ..... @vv_ui3
|
|
|
|
|
vbitseti_h 0111 00110001 01000 1 .... ..... ..... @vv_ui4
|
|
|
|
|
vbitseti_w 0111 00110001 01001 ..... ..... ..... @vv_ui5
|
|
|
|
|
vbitseti_d 0111 00110001 0101 ...... ..... ..... @vv_ui6
|
|
|
|
|
vbitrev_b 0111 00010001 00000 ..... ..... ..... @vvv
|
|
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|
|
vbitrev_h 0111 00010001 00001 ..... ..... ..... @vvv
|
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|
vbitrev_w 0111 00010001 00010 ..... ..... ..... @vvv
|
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|
|
vbitrev_d 0111 00010001 00011 ..... ..... ..... @vvv
|
|
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|
|
vbitrevi_b 0111 00110001 10000 01 ... ..... ..... @vv_ui3
|
|
|
|
|
vbitrevi_h 0111 00110001 10000 1 .... ..... ..... @vv_ui4
|
|
|
|
|
vbitrevi_w 0111 00110001 10001 ..... ..... ..... @vv_ui5
|
|
|
|
|
vbitrevi_d 0111 00110001 1001 ...... ..... ..... @vv_ui6
|
2023-05-04 15:27:58 +03:00
|
|
|
|
|
|
|
|
vfrstp_b 0111 00010010 10110 ..... ..... ..... @vvv
|
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|
vfrstp_h 0111 00010010 10111 ..... ..... ..... @vvv
|
|
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|
|
vfrstpi_b 0111 00101001 10100 ..... ..... ..... @vv_ui5
|
|
|
|
|
vfrstpi_h 0111 00101001 10101 ..... ..... ..... @vv_ui5
|
2023-05-04 15:27:59 +03:00
|
|
|
|
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|
|
|
vfadd_s 0111 00010011 00001 ..... ..... ..... @vvv
|
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|
vfadd_d 0111 00010011 00010 ..... ..... ..... @vvv
|
|
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|
|
vfsub_s 0111 00010011 00101 ..... ..... ..... @vvv
|
|
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|
|
vfsub_d 0111 00010011 00110 ..... ..... ..... @vvv
|
|
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|
|
vfmul_s 0111 00010011 10001 ..... ..... ..... @vvv
|
|
|
|
|
vfmul_d 0111 00010011 10010 ..... ..... ..... @vvv
|
|
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|
|
vfdiv_s 0111 00010011 10101 ..... ..... ..... @vvv
|
|
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|
|
vfdiv_d 0111 00010011 10110 ..... ..... ..... @vvv
|
|
|
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|
|
|
|
|
|
vfmadd_s 0000 10010001 ..... ..... ..... ..... @vvvv
|
|
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|
|
vfmadd_d 0000 10010010 ..... ..... ..... ..... @vvvv
|
|
|
|
|
vfmsub_s 0000 10010101 ..... ..... ..... ..... @vvvv
|
|
|
|
|
vfmsub_d 0000 10010110 ..... ..... ..... ..... @vvvv
|
|
|
|
|
vfnmadd_s 0000 10011001 ..... ..... ..... ..... @vvvv
|
|
|
|
|
vfnmadd_d 0000 10011010 ..... ..... ..... ..... @vvvv
|
|
|
|
|
vfnmsub_s 0000 10011101 ..... ..... ..... ..... @vvvv
|
|
|
|
|
vfnmsub_d 0000 10011110 ..... ..... ..... ..... @vvvv
|
|
|
|
|
|
|
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|
|
vfmax_s 0111 00010011 11001 ..... ..... ..... @vvv
|
|
|
|
|
vfmax_d 0111 00010011 11010 ..... ..... ..... @vvv
|
|
|
|
|
vfmin_s 0111 00010011 11101 ..... ..... ..... @vvv
|
|
|
|
|
vfmin_d 0111 00010011 11110 ..... ..... ..... @vvv
|
|
|
|
|
|
|
|
|
|
vfmaxa_s 0111 00010100 00001 ..... ..... ..... @vvv
|
|
|
|
|
vfmaxa_d 0111 00010100 00010 ..... ..... ..... @vvv
|
|
|
|
|
vfmina_s 0111 00010100 00101 ..... ..... ..... @vvv
|
|
|
|
|
vfmina_d 0111 00010100 00110 ..... ..... ..... @vvv
|
|
|
|
|
|
|
|
|
|
vflogb_s 0111 00101001 11001 10001 ..... ..... @vv
|
|
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|
|
vflogb_d 0111 00101001 11001 10010 ..... ..... @vv
|
|
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|
|
|
|
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|
|
vfclass_s 0111 00101001 11001 10101 ..... ..... @vv
|
|
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|
|
vfclass_d 0111 00101001 11001 10110 ..... ..... @vv
|
|
|
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|
|
|
|
|
|
vfsqrt_s 0111 00101001 11001 11001 ..... ..... @vv
|
|
|
|
|
vfsqrt_d 0111 00101001 11001 11010 ..... ..... @vv
|
|
|
|
|
vfrecip_s 0111 00101001 11001 11101 ..... ..... @vv
|
|
|
|
|
vfrecip_d 0111 00101001 11001 11110 ..... ..... @vv
|
|
|
|
|
vfrsqrt_s 0111 00101001 11010 00001 ..... ..... @vv
|
|
|
|
|
vfrsqrt_d 0111 00101001 11010 00010 ..... ..... @vv
|
2023-05-04 15:28:00 +03:00
|
|
|
|
|
|
|
|
vfcvtl_s_h 0111 00101001 11011 11010 ..... ..... @vv
|
|
|
|
|
vfcvth_s_h 0111 00101001 11011 11011 ..... ..... @vv
|
|
|
|
|
vfcvtl_d_s 0111 00101001 11011 11100 ..... ..... @vv
|
|
|
|
|
vfcvth_d_s 0111 00101001 11011 11101 ..... ..... @vv
|
|
|
|
|
vfcvt_h_s 0111 00010100 01100 ..... ..... ..... @vvv
|
|
|
|
|
vfcvt_s_d 0111 00010100 01101 ..... ..... ..... @vvv
|
|
|
|
|
|
|
|
|
|
vfrint_s 0111 00101001 11010 01101 ..... ..... @vv
|
|
|
|
|
vfrint_d 0111 00101001 11010 01110 ..... ..... @vv
|
|
|
|
|
vfrintrm_s 0111 00101001 11010 10001 ..... ..... @vv
|
|
|
|
|
vfrintrm_d 0111 00101001 11010 10010 ..... ..... @vv
|
|
|
|
|
vfrintrp_s 0111 00101001 11010 10101 ..... ..... @vv
|
|
|
|
|
vfrintrp_d 0111 00101001 11010 10110 ..... ..... @vv
|
|
|
|
|
vfrintrz_s 0111 00101001 11010 11001 ..... ..... @vv
|
|
|
|
|
vfrintrz_d 0111 00101001 11010 11010 ..... ..... @vv
|
|
|
|
|
vfrintrne_s 0111 00101001 11010 11101 ..... ..... @vv
|
|
|
|
|
vfrintrne_d 0111 00101001 11010 11110 ..... ..... @vv
|
|
|
|
|
|
|
|
|
|
vftint_w_s 0111 00101001 11100 01100 ..... ..... @vv
|
|
|
|
|
vftint_l_d 0111 00101001 11100 01101 ..... ..... @vv
|
|
|
|
|
vftintrm_w_s 0111 00101001 11100 01110 ..... ..... @vv
|
|
|
|
|
vftintrm_l_d 0111 00101001 11100 01111 ..... ..... @vv
|
|
|
|
|
vftintrp_w_s 0111 00101001 11100 10000 ..... ..... @vv
|
|
|
|
|
vftintrp_l_d 0111 00101001 11100 10001 ..... ..... @vv
|
|
|
|
|
vftintrz_w_s 0111 00101001 11100 10010 ..... ..... @vv
|
|
|
|
|
vftintrz_l_d 0111 00101001 11100 10011 ..... ..... @vv
|
|
|
|
|
vftintrne_w_s 0111 00101001 11100 10100 ..... ..... @vv
|
|
|
|
|
vftintrne_l_d 0111 00101001 11100 10101 ..... ..... @vv
|
|
|
|
|
vftint_wu_s 0111 00101001 11100 10110 ..... ..... @vv
|
|
|
|
|
vftint_lu_d 0111 00101001 11100 10111 ..... ..... @vv
|
|
|
|
|
vftintrz_wu_s 0111 00101001 11100 11100 ..... ..... @vv
|
|
|
|
|
vftintrz_lu_d 0111 00101001 11100 11101 ..... ..... @vv
|
|
|
|
|
vftint_w_d 0111 00010100 10011 ..... ..... ..... @vvv
|
|
|
|
|
vftintrm_w_d 0111 00010100 10100 ..... ..... ..... @vvv
|
|
|
|
|
vftintrp_w_d 0111 00010100 10101 ..... ..... ..... @vvv
|
|
|
|
|
vftintrz_w_d 0111 00010100 10110 ..... ..... ..... @vvv
|
|
|
|
|
vftintrne_w_d 0111 00010100 10111 ..... ..... ..... @vvv
|
|
|
|
|
vftintl_l_s 0111 00101001 11101 00000 ..... ..... @vv
|
|
|
|
|
vftinth_l_s 0111 00101001 11101 00001 ..... ..... @vv
|
|
|
|
|
vftintrml_l_s 0111 00101001 11101 00010 ..... ..... @vv
|
|
|
|
|
vftintrmh_l_s 0111 00101001 11101 00011 ..... ..... @vv
|
|
|
|
|
vftintrpl_l_s 0111 00101001 11101 00100 ..... ..... @vv
|
|
|
|
|
vftintrph_l_s 0111 00101001 11101 00101 ..... ..... @vv
|
|
|
|
|
vftintrzl_l_s 0111 00101001 11101 00110 ..... ..... @vv
|
|
|
|
|
vftintrzh_l_s 0111 00101001 11101 00111 ..... ..... @vv
|
|
|
|
|
vftintrnel_l_s 0111 00101001 11101 01000 ..... ..... @vv
|
|
|
|
|
vftintrneh_l_s 0111 00101001 11101 01001 ..... ..... @vv
|
|
|
|
|
|
|
|
|
|
vffint_s_w 0111 00101001 11100 00000 ..... ..... @vv
|
|
|
|
|
vffint_s_wu 0111 00101001 11100 00001 ..... ..... @vv
|
|
|
|
|
vffint_d_l 0111 00101001 11100 00010 ..... ..... @vv
|
|
|
|
|
vffint_d_lu 0111 00101001 11100 00011 ..... ..... @vv
|
|
|
|
|
vffintl_d_w 0111 00101001 11100 00100 ..... ..... @vv
|
|
|
|
|
vffinth_d_w 0111 00101001 11100 00101 ..... ..... @vv
|
|
|
|
|
vffint_s_l 0111 00010100 10000 ..... ..... ..... @vvv
|
2023-05-04 15:28:01 +03:00
|
|
|
|
|
|
|
|
vseq_b 0111 00000000 00000 ..... ..... ..... @vvv
|
|
|
|
|
vseq_h 0111 00000000 00001 ..... ..... ..... @vvv
|
|
|
|
|
vseq_w 0111 00000000 00010 ..... ..... ..... @vvv
|
|
|
|
|
vseq_d 0111 00000000 00011 ..... ..... ..... @vvv
|
|
|
|
|
vseqi_b 0111 00101000 00000 ..... ..... ..... @vv_i5
|
|
|
|
|
vseqi_h 0111 00101000 00001 ..... ..... ..... @vv_i5
|
|
|
|
|
vseqi_w 0111 00101000 00010 ..... ..... ..... @vv_i5
|
|
|
|
|
vseqi_d 0111 00101000 00011 ..... ..... ..... @vv_i5
|
|
|
|
|
|
|
|
|
|
vsle_b 0111 00000000 00100 ..... ..... ..... @vvv
|
|
|
|
|
vsle_h 0111 00000000 00101 ..... ..... ..... @vvv
|
|
|
|
|
vsle_w 0111 00000000 00110 ..... ..... ..... @vvv
|
|
|
|
|
vsle_d 0111 00000000 00111 ..... ..... ..... @vvv
|
|
|
|
|
vslei_b 0111 00101000 00100 ..... ..... ..... @vv_i5
|
|
|
|
|
vslei_h 0111 00101000 00101 ..... ..... ..... @vv_i5
|
|
|
|
|
vslei_w 0111 00101000 00110 ..... ..... ..... @vv_i5
|
|
|
|
|
vslei_d 0111 00101000 00111 ..... ..... ..... @vv_i5
|
|
|
|
|
vsle_bu 0111 00000000 01000 ..... ..... ..... @vvv
|
|
|
|
|
vsle_hu 0111 00000000 01001 ..... ..... ..... @vvv
|
|
|
|
|
vsle_wu 0111 00000000 01010 ..... ..... ..... @vvv
|
|
|
|
|
vsle_du 0111 00000000 01011 ..... ..... ..... @vvv
|
|
|
|
|
vslei_bu 0111 00101000 01000 ..... ..... ..... @vv_ui5
|
|
|
|
|
vslei_hu 0111 00101000 01001 ..... ..... ..... @vv_ui5
|
|
|
|
|
vslei_wu 0111 00101000 01010 ..... ..... ..... @vv_ui5
|
|
|
|
|
vslei_du 0111 00101000 01011 ..... ..... ..... @vv_ui5
|
|
|
|
|
|
|
|
|
|
vslt_b 0111 00000000 01100 ..... ..... ..... @vvv
|
|
|
|
|
vslt_h 0111 00000000 01101 ..... ..... ..... @vvv
|
|
|
|
|
vslt_w 0111 00000000 01110 ..... ..... ..... @vvv
|
|
|
|
|
vslt_d 0111 00000000 01111 ..... ..... ..... @vvv
|
|
|
|
|
vslti_b 0111 00101000 01100 ..... ..... ..... @vv_i5
|
|
|
|
|
vslti_h 0111 00101000 01101 ..... ..... ..... @vv_i5
|
|
|
|
|
vslti_w 0111 00101000 01110 ..... ..... ..... @vv_i5
|
|
|
|
|
vslti_d 0111 00101000 01111 ..... ..... ..... @vv_i5
|
|
|
|
|
vslt_bu 0111 00000000 10000 ..... ..... ..... @vvv
|
|
|
|
|
vslt_hu 0111 00000000 10001 ..... ..... ..... @vvv
|
|
|
|
|
vslt_wu 0111 00000000 10010 ..... ..... ..... @vvv
|
|
|
|
|
vslt_du 0111 00000000 10011 ..... ..... ..... @vvv
|
|
|
|
|
vslti_bu 0111 00101000 10000 ..... ..... ..... @vv_ui5
|
|
|
|
|
vslti_hu 0111 00101000 10001 ..... ..... ..... @vv_ui5
|
|
|
|
|
vslti_wu 0111 00101000 10010 ..... ..... ..... @vv_ui5
|
|
|
|
|
vslti_du 0111 00101000 10011 ..... ..... ..... @vv_ui5
|
2023-05-04 15:28:02 +03:00
|
|
|
|
|
|
|
|
vfcmp_cond_s 0000 11000101 ..... ..... ..... ..... @vvv_fcond
|
|
|
|
|
vfcmp_cond_d 0000 11000110 ..... ..... ..... ..... @vvv_fcond
|
2023-05-04 15:28:03 +03:00
|
|
|
|
|
|
|
|
vbitsel_v 0000 11010001 ..... ..... ..... ..... @vvvv
|
|
|
|
|
|
|
|
|
|
vbitseli_b 0111 00111100 01 ........ ..... ..... @vv_ui8
|
|
|
|
|
|
|
|
|
|
vseteqz_v 0111 00101001 11001 00110 ..... 00 ... @cv
|
|
|
|
|
vsetnez_v 0111 00101001 11001 00111 ..... 00 ... @cv
|
|
|
|
|
vsetanyeqz_b 0111 00101001 11001 01000 ..... 00 ... @cv
|
|
|
|
|
vsetanyeqz_h 0111 00101001 11001 01001 ..... 00 ... @cv
|
|
|
|
|
vsetanyeqz_w 0111 00101001 11001 01010 ..... 00 ... @cv
|
|
|
|
|
vsetanyeqz_d 0111 00101001 11001 01011 ..... 00 ... @cv
|
|
|
|
|
vsetallnez_b 0111 00101001 11001 01100 ..... 00 ... @cv
|
|
|
|
|
vsetallnez_h 0111 00101001 11001 01101 ..... 00 ... @cv
|
|
|
|
|
vsetallnez_w 0111 00101001 11001 01110 ..... 00 ... @cv
|
|
|
|
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vsetallnez_d 0111 00101001 11001 01111 ..... 00 ... @cv
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2023-05-04 15:28:04 +03:00
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vinsgr2vr_b 0111 00101110 10111 0 .... ..... ..... @vr_ui4
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vinsgr2vr_h 0111 00101110 10111 10 ... ..... ..... @vr_ui3
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vinsgr2vr_w 0111 00101110 10111 110 .. ..... ..... @vr_ui2
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vinsgr2vr_d 0111 00101110 10111 1110 . ..... ..... @vr_ui1
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vpickve2gr_b 0111 00101110 11111 0 .... ..... ..... @rv_ui4
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vpickve2gr_h 0111 00101110 11111 10 ... ..... ..... @rv_ui3
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vpickve2gr_w 0111 00101110 11111 110 .. ..... ..... @rv_ui2
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vpickve2gr_d 0111 00101110 11111 1110 . ..... ..... @rv_ui1
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vpickve2gr_bu 0111 00101111 00111 0 .... ..... ..... @rv_ui4
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vpickve2gr_hu 0111 00101111 00111 10 ... ..... ..... @rv_ui3
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vpickve2gr_wu 0111 00101111 00111 110 .. ..... ..... @rv_ui2
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vpickve2gr_du 0111 00101111 00111 1110 . ..... ..... @rv_ui1
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vreplgr2vr_b 0111 00101001 11110 00000 ..... ..... @vr
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vreplgr2vr_h 0111 00101001 11110 00001 ..... ..... @vr
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vreplgr2vr_w 0111 00101001 11110 00010 ..... ..... @vr
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vreplgr2vr_d 0111 00101001 11110 00011 ..... ..... @vr
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2023-05-04 15:28:05 +03:00
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vreplve_b 0111 00010010 00100 ..... ..... ..... @vvr
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vreplve_h 0111 00010010 00101 ..... ..... ..... @vvr
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vreplve_w 0111 00010010 00110 ..... ..... ..... @vvr
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vreplve_d 0111 00010010 00111 ..... ..... ..... @vvr
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vreplvei_b 0111 00101111 01111 0 .... ..... ..... @vv_ui4
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vreplvei_h 0111 00101111 01111 10 ... ..... ..... @vv_ui3
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vreplvei_w 0111 00101111 01111 110 .. ..... ..... @vv_ui2
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vreplvei_d 0111 00101111 01111 1110 . ..... ..... @vv_ui1
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vbsll_v 0111 00101000 11100 ..... ..... ..... @vv_ui5
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vbsrl_v 0111 00101000 11101 ..... ..... ..... @vv_ui5
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vpackev_b 0111 00010001 01100 ..... ..... ..... @vvv
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vpackev_h 0111 00010001 01101 ..... ..... ..... @vvv
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vpackev_w 0111 00010001 01110 ..... ..... ..... @vvv
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vpackev_d 0111 00010001 01111 ..... ..... ..... @vvv
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vpackod_b 0111 00010001 10000 ..... ..... ..... @vvv
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vpackod_h 0111 00010001 10001 ..... ..... ..... @vvv
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vpackod_w 0111 00010001 10010 ..... ..... ..... @vvv
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vpackod_d 0111 00010001 10011 ..... ..... ..... @vvv
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vpickev_b 0111 00010001 11100 ..... ..... ..... @vvv
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vpickev_h 0111 00010001 11101 ..... ..... ..... @vvv
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vpickev_w 0111 00010001 11110 ..... ..... ..... @vvv
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vpickev_d 0111 00010001 11111 ..... ..... ..... @vvv
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vpickod_b 0111 00010010 00000 ..... ..... ..... @vvv
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vpickod_h 0111 00010010 00001 ..... ..... ..... @vvv
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vpickod_w 0111 00010010 00010 ..... ..... ..... @vvv
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vpickod_d 0111 00010010 00011 ..... ..... ..... @vvv
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2023-05-04 15:28:06 +03:00
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vilvl_b 0111 00010001 10100 ..... ..... ..... @vvv
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vilvl_h 0111 00010001 10101 ..... ..... ..... @vvv
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vilvl_w 0111 00010001 10110 ..... ..... ..... @vvv
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vilvl_d 0111 00010001 10111 ..... ..... ..... @vvv
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vilvh_b 0111 00010001 11000 ..... ..... ..... @vvv
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vilvh_h 0111 00010001 11001 ..... ..... ..... @vvv
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vilvh_w 0111 00010001 11010 ..... ..... ..... @vvv
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vilvh_d 0111 00010001 11011 ..... ..... ..... @vvv
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vshuf_b 0000 11010101 ..... ..... ..... ..... @vvvv
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vshuf_h 0111 00010111 10101 ..... ..... ..... @vvv
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vshuf_w 0111 00010111 10110 ..... ..... ..... @vvv
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vshuf_d 0111 00010111 10111 ..... ..... ..... @vvv
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vshuf4i_b 0111 00111001 00 ........ ..... ..... @vv_ui8
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vshuf4i_h 0111 00111001 01 ........ ..... ..... @vv_ui8
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vshuf4i_w 0111 00111001 10 ........ ..... ..... @vv_ui8
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vshuf4i_d 0111 00111001 11 ........ ..... ..... @vv_ui8
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vpermi_w 0111 00111110 01 ........ ..... ..... @vv_ui8
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vextrins_d 0111 00111000 00 ........ ..... ..... @vv_ui8
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vextrins_w 0111 00111000 01 ........ ..... ..... @vv_ui8
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vextrins_h 0111 00111000 10 ........ ..... ..... @vv_ui8
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vextrins_b 0111 00111000 11 ........ ..... ..... @vv_ui8
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2023-05-04 15:28:07 +03:00
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vld 0010 110000 ............ ..... ..... @vr_i12
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vst 0010 110001 ............ ..... ..... @vr_i12
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vldx 0011 10000100 00000 ..... ..... ..... @vrr
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vstx 0011 10000100 01000 ..... ..... ..... @vrr
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vldrepl_d 0011 00000001 0 ......... ..... ..... @vr_i9
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vldrepl_w 0011 00000010 .......... ..... ..... @vr_i10
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vldrepl_h 0011 0000010 ........... ..... ..... @vr_i11
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vldrepl_b 0011 000010 ............ ..... ..... @vr_i12
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vstelm_d 0011 00010001 0 . ........ ..... ..... @vr_i8i1
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vstelm_w 0011 00010010 .. ........ ..... ..... @vr_i8i2
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vstelm_h 0011 0001010 ... ........ ..... ..... @vr_i8i3
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vstelm_b 0011 000110 .... ........ ..... ..... @vr_i8i4
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