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target/loongarch: Implement vaddi/vsubi

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This patch includes:
- VADDI.{B/H/W/D}U;
- VSUBI.{B/H/W/D}U.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-6-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-05-04 20:27:31 +08:00
parent 57b4f1ac18
commit d8be64c1c5
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
3 changed files with 62 additions and 0 deletions
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14
target/loongarch/disas.c
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@ -797,6 +797,11 @@ static void output_vvv(DisasContext *ctx, arg_vvv *a, const char *mnemonic)
output(ctx, mnemonic, "v%d, v%d, v%d", a->vd, a->vj, a->vk);
}
static void output_vv_i(DisasContext *ctx, arg_vv_i *a, const char *mnemonic)
{
output(ctx, mnemonic, "v%d, v%d, 0x%x", a->vd, a->vj, a->imm);
}
INSN_LSX(vadd_b, vvv)
INSN_LSX(vadd_h, vvv)
INSN_LSX(vadd_w, vvv)
@ -807,3 +812,12 @@ INSN_LSX(vsub_h, vvv)
INSN_LSX(vsub_w, vvv)
INSN_LSX(vsub_d, vvv)
INSN_LSX(vsub_q, vvv)
INSN_LSX(vaddi_bu, vv_i)
INSN_LSX(vaddi_hu, vv_i)
INSN_LSX(vaddi_wu, vv_i)
INSN_LSX(vaddi_du, vv_i)
INSN_LSX(vsubi_bu, vv_i)
INSN_LSX(vsubi_hu, vv_i)
INSN_LSX(vsubi_wu, vv_i)
INSN_LSX(vsubi_du, vv_i)

37
target/loongarch/insn_trans/trans_lsx.c.inc
View File

@ -44,6 +44,34 @@ static bool gvec_vvv(DisasContext *ctx, arg_vvv *a, MemOp mop,
return true;
}
static bool gvec_vv_i(DisasContext *ctx, arg_vv_i *a, MemOp mop,
void (*func)(unsigned, uint32_t, uint32_t,
int64_t, uint32_t, uint32_t))
{
uint32_t vd_ofs, vj_ofs;
CHECK_SXE;
vd_ofs = vec_full_offset(a->vd);
vj_ofs = vec_full_offset(a->vj);
func(mop, vd_ofs, vj_ofs, a->imm , 16, ctx->vl/8);
return true;
}
static bool gvec_subi(DisasContext *ctx, arg_vv_i *a, MemOp mop)
{
uint32_t vd_ofs, vj_ofs;
CHECK_SXE;
vd_ofs = vec_full_offset(a->vd);
vj_ofs = vec_full_offset(a->vj);
tcg_gen_gvec_addi(mop, vd_ofs, vj_ofs, -a->imm, 16, ctx->vl/8);
return true;
}
TRANS(vadd_b, gvec_vvv, MO_8, tcg_gen_gvec_add)
TRANS(vadd_h, gvec_vvv, MO_16, tcg_gen_gvec_add)
TRANS(vadd_w, gvec_vvv, MO_32, tcg_gen_gvec_add)
@ -83,3 +111,12 @@ TRANS(vsub_b, gvec_vvv, MO_8, tcg_gen_gvec_sub)
TRANS(vsub_h, gvec_vvv, MO_16, tcg_gen_gvec_sub)
TRANS(vsub_w, gvec_vvv, MO_32, tcg_gen_gvec_sub)
TRANS(vsub_d, gvec_vvv, MO_64, tcg_gen_gvec_sub)
TRANS(vaddi_bu, gvec_vv_i, MO_8, tcg_gen_gvec_addi)
TRANS(vaddi_hu, gvec_vv_i, MO_16, tcg_gen_gvec_addi)
TRANS(vaddi_wu, gvec_vv_i, MO_32, tcg_gen_gvec_addi)
TRANS(vaddi_du, gvec_vv_i, MO_64, tcg_gen_gvec_addi)
TRANS(vsubi_bu, gvec_subi, MO_8)
TRANS(vsubi_hu, gvec_subi, MO_16)
TRANS(vsubi_wu, gvec_subi, MO_32)
TRANS(vsubi_du, gvec_subi, MO_64)

11
target/loongarch/insns.decode
View File

@ -491,11 +491,13 @@ dbcl 0000 00000010 10101 ............... @i15
#
&vvv vd vj vk
&vv_i vd vj imm
#
# LSX Formats
#
@vvv .... ........ ..... vk:5 vj:5 vd:5 &vvv
@vv_ui5 .... ........ ..... imm:5 vj:5 vd:5 &vv_i
vadd_b 0111 00000000 10100 ..... ..... ..... @vvv
vadd_h 0111 00000000 10101 ..... ..... ..... @vvv
@ -507,3 +509,12 @@ vsub_h 0111 00000000 11001 ..... ..... ..... @vvv
vsub_w 0111 00000000 11010 ..... ..... ..... @vvv
vsub_d 0111 00000000 11011 ..... ..... ..... @vvv
vsub_q 0111 00010010 11011 ..... ..... ..... @vvv
vaddi_bu 0111 00101000 10100 ..... ..... ..... @vv_ui5
vaddi_hu 0111 00101000 10101 ..... ..... ..... @vv_ui5
vaddi_wu 0111 00101000 10110 ..... ..... ..... @vv_ui5
vaddi_du 0111 00101000 10111 ..... ..... ..... @vv_ui5
vsubi_bu 0111 00101000 11000 ..... ..... ..... @vv_ui5
vsubi_hu 0111 00101000 11001 ..... ..... ..... @vv_ui5
vsubi_wu 0111 00101000 11010 ..... ..... ..... @vv_ui5
vsubi_du 0111 00101000 11011 ..... ..... ..... @vv_ui5