2018-03-02 15:31:13 +03:00
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/*
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* QEMU RISC-V Spike Board
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This provides a RISC-V Board with the following devices:
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*
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* 0) HTIF Console and Poweroff
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* 1) CLINT (Timer and IPI)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/spike.h"
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2019-06-25 01:11:49 +03:00
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#include "hw/riscv/boot.h"
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hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
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#include "hw/riscv/numa.h"
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2020-09-03 13:40:18 +03:00
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#include "hw/char/riscv_htif.h"
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2021-08-31 14:06:00 +03:00
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#include "hw/intc/riscv_aclint.h"
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2018-03-02 15:31:13 +03:00
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#include "chardev/char.h"
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#include "sysemu/device_tree.h"
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2019-08-12 08:23:57 +03:00
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#include "sysemu/sysemu.h"
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2018-03-04 01:52:13 +03:00
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2022-09-26 20:38:54 +03:00
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#include <libfdt.h>
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2021-02-20 17:48:04 +03:00
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static const MemMapEntry spike_memmap[] = {
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2020-07-09 13:05:43 +03:00
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[SPIKE_MROM] = { 0x1000, 0xf000 },
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2022-01-13 17:50:39 +03:00
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[SPIKE_HTIF] = { 0x1000000, 0x1000 },
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2018-03-02 15:31:13 +03:00
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[SPIKE_CLINT] = { 0x2000000, 0x10000 },
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[SPIKE_DRAM] = { 0x80000000, 0x0 },
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};
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2021-02-20 17:48:04 +03:00
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static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
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2022-12-29 13:31:23 +03:00
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bool is_32_bit, bool htif_custom_base)
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2018-03-02 15:31:13 +03:00
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{
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void *fdt;
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2023-01-02 14:52:32 +03:00
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int fdt_size;
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hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
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uint64_t addr, size;
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unsigned long clint_addr;
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int cpu, socket;
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2023-01-25 00:22:34 +03:00
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MachineState *ms = MACHINE(s);
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hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
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uint32_t *clint_cells;
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uint32_t cpu_phandle, intc_phandle, phandle = 1;
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target/riscv: support new isa extension detection devicetree properties
A few months ago I submitted a patch to various lists, deprecating
"riscv,isa" with a lengthy commit message [0] that is now commit
aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") in the Linux
kernel tree. Primarily, the goal was to replace "riscv,isa" with a new
set of properties that allowed for strictly defining the meaning of
various extensions, where "riscv,isa" was tied to whatever definitions
inflicted upon us by the ISA manual, which have seen some variance over
time.
Two new properties were introduced: "riscv,isa-base" and
"riscv,isa-extensions". The former is a simple string to communicate the
base ISA implemented by a hart and the latter an array of strings used
to communicate the set of ISA extensions supported, per the definitions
of each substring in extensions.yaml [1]. A beneficial side effect was
also the ability to define vendor extensions in a more "official" way,
as the ISA manual and other RVI specifications only covered the format
for vendor extensions in the ISA string, but not the meaning of vendor
extensions, for obvious reasons.
Add support for setting these two new properties in the devicetrees for
the various devicetree platforms supported by QEMU for RISC-V. The Linux
kernel already supports parsing ISA extensions from these new
properties, and documenting them in the dt-binding is a requirement for
new extension detection being added to the kernel.
A side effect of the implementation is that the meaning for elements in
"riscv,isa" and in "riscv,isa-extensions" are now tied together as they
are constructed from the same source. The same applies to the ISA string
provided in ACPI tables, but there does not appear to be any strict
definitions of meanings in ACPI land either.
Link: https://lore.kernel.org/qemu-riscv/20230702-eats-scorebook-c951f170d29f@spud/ [0]
Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/extensions.yaml [1]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240124-unvarying-foothold-9dde2aaf95d4@spud>
[ Changes by AF:
- Rebase on recent changes
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-01-24 15:55:50 +03:00
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char *mem_name, *clint_name, *clust_name;
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hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
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char *core_name, *cpu_name, *intc_name;
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2021-04-30 10:12:57 +03:00
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static const char * const clint_compat[2] = {
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"sifive,clint0", "riscv,clint0"
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};
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2018-03-02 15:31:13 +03:00
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2023-01-25 00:22:34 +03:00
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fdt = ms->fdt = create_device_tree(&fdt_size);
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2018-03-02 15:31:13 +03:00
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
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qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
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qemu_fdt_add_subnode(fdt, "/htif");
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qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
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2022-12-29 13:31:23 +03:00
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if (htif_custom_base) {
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2022-01-13 17:50:39 +03:00
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qemu_fdt_setprop_cells(fdt, "/htif", "reg",
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0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
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}
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2018-03-02 15:31:13 +03:00
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qemu_fdt_add_subnode(fdt, "/soc");
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qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
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2018-08-21 01:21:11 +03:00
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qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
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2018-03-02 15:31:13 +03:00
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qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
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qemu_fdt_add_subnode(fdt, "/cpus");
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2018-03-03 04:30:07 +03:00
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
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2021-08-31 14:06:01 +03:00
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RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
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2018-03-02 15:31:13 +03:00
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
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qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
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2023-01-25 00:22:34 +03:00
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for (socket = (riscv_socket_count(ms) - 1); socket >= 0; socket--) {
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hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
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clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
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qemu_fdt_add_subnode(fdt, clust_name);
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clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
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2018-03-02 15:31:13 +03:00
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hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
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for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
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cpu_phandle = phandle++;
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cpu_name = g_strdup_printf("/cpus/cpu@%d",
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s->soc[socket].hartid_base + cpu);
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qemu_fdt_add_subnode(fdt, cpu_name);
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2020-12-16 21:22:43 +03:00
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if (is_32_bit) {
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qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
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} else {
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qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
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}
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target/riscv: support new isa extension detection devicetree properties
A few months ago I submitted a patch to various lists, deprecating
"riscv,isa" with a lengthy commit message [0] that is now commit
aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") in the Linux
kernel tree. Primarily, the goal was to replace "riscv,isa" with a new
set of properties that allowed for strictly defining the meaning of
various extensions, where "riscv,isa" was tied to whatever definitions
inflicted upon us by the ISA manual, which have seen some variance over
time.
Two new properties were introduced: "riscv,isa-base" and
"riscv,isa-extensions". The former is a simple string to communicate the
base ISA implemented by a hart and the latter an array of strings used
to communicate the set of ISA extensions supported, per the definitions
of each substring in extensions.yaml [1]. A beneficial side effect was
also the ability to define vendor extensions in a more "official" way,
as the ISA manual and other RVI specifications only covered the format
for vendor extensions in the ISA string, but not the meaning of vendor
extensions, for obvious reasons.
Add support for setting these two new properties in the devicetrees for
the various devicetree platforms supported by QEMU for RISC-V. The Linux
kernel already supports parsing ISA extensions from these new
properties, and documenting them in the dt-binding is a requirement for
new extension detection being added to the kernel.
A side effect of the implementation is that the meaning for elements in
"riscv,isa" and in "riscv,isa-extensions" are now tied together as they
are constructed from the same source. The same applies to the ISA string
provided in ACPI tables, but there does not appear to be any strict
definitions of meanings in ACPI land either.
Link: https://lore.kernel.org/qemu-riscv/20230702-eats-scorebook-c951f170d29f@spud/ [0]
Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/extensions.yaml [1]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240124-unvarying-foothold-9dde2aaf95d4@spud>
[ Changes by AF:
- Rebase on recent changes
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-01-24 15:55:50 +03:00
|
|
|
riscv_isa_write_fdt(&s->soc[socket].harts[cpu], fdt, cpu_name);
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
|
|
|
|
|
qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
|
|
|
|
|
qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
|
|
|
|
|
s->soc[socket].hartid_base + cpu);
|
|
|
|
|
qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
|
2023-01-25 00:22:34 +03:00
|
|
|
riscv_socket_fdt_write_id(ms, cpu_name, socket);
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
|
2018-03-02 15:31:13 +03:00
|
|
|
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
|
|
|
|
|
qemu_fdt_add_subnode(fdt, intc_name);
|
|
|
|
|
intc_phandle = phandle++;
|
|
|
|
|
qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
|
|
|
|
|
qemu_fdt_setprop_string(fdt, intc_name, "compatible",
|
|
|
|
|
"riscv,cpu-intc");
|
|
|
|
|
qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
|
|
|
|
|
qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
|
|
|
|
|
|
|
|
|
|
clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
|
|
|
|
|
clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
|
|
|
|
|
clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
|
|
|
|
|
clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
|
|
|
|
|
|
|
|
|
|
core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
|
|
|
|
|
qemu_fdt_add_subnode(fdt, core_name);
|
|
|
|
|
qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
|
|
|
|
|
|
|
|
|
|
g_free(core_name);
|
|
|
|
|
g_free(intc_name);
|
|
|
|
|
g_free(cpu_name);
|
|
|
|
|
}
|
|
|
|
|
|
2023-01-25 00:22:34 +03:00
|
|
|
addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, socket);
|
|
|
|
|
size = riscv_socket_mem_size(ms, socket);
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
mem_name = g_strdup_printf("/memory@%lx", (long)addr);
|
|
|
|
|
qemu_fdt_add_subnode(fdt, mem_name);
|
|
|
|
|
qemu_fdt_setprop_cells(fdt, mem_name, "reg",
|
|
|
|
|
addr >> 32, addr, size >> 32, size);
|
|
|
|
|
qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
|
2023-01-25 00:22:34 +03:00
|
|
|
riscv_socket_fdt_write_id(ms, mem_name, socket);
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
g_free(mem_name);
|
|
|
|
|
|
|
|
|
|
clint_addr = memmap[SPIKE_CLINT].base +
|
|
|
|
|
(memmap[SPIKE_CLINT].size * socket);
|
|
|
|
|
clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
|
|
|
|
|
qemu_fdt_add_subnode(fdt, clint_name);
|
2021-04-30 10:12:57 +03:00
|
|
|
qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
|
|
|
|
|
(char **)&clint_compat, ARRAY_SIZE(clint_compat));
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
qemu_fdt_setprop_cells(fdt, clint_name, "reg",
|
|
|
|
|
0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
|
|
|
|
|
qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
|
|
|
|
|
clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
|
2023-01-25 00:22:34 +03:00
|
|
|
riscv_socket_fdt_write_id(ms, clint_name, socket);
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
|
|
|
|
|
g_free(clint_name);
|
|
|
|
|
g_free(clint_cells);
|
|
|
|
|
g_free(clust_name);
|
2018-03-02 15:31:13 +03:00
|
|
|
}
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
|
2023-01-25 00:22:34 +03:00
|
|
|
riscv_socket_fdt_write_distance_matrix(ms);
|
2018-03-02 15:31:13 +03:00
|
|
|
|
2022-04-21 08:56:28 +03:00
|
|
|
qemu_fdt_add_subnode(fdt, "/chosen");
|
|
|
|
|
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
|
2019-04-20 05:24:26 +03:00
|
|
|
}
|
|
|
|
|
|
2022-12-29 13:31:23 +03:00
|
|
|
static bool spike_test_elf_image(char *filename)
|
|
|
|
|
{
|
|
|
|
|
Error *err = NULL;
|
|
|
|
|
|
|
|
|
|
load_elf_hdr(filename, NULL, NULL, &err);
|
|
|
|
|
if (err) {
|
|
|
|
|
error_free(err);
|
|
|
|
|
return false;
|
|
|
|
|
} else {
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2019-04-20 05:24:26 +03:00
|
|
|
static void spike_board_init(MachineState *machine)
|
|
|
|
|
{
|
2021-02-20 17:48:04 +03:00
|
|
|
const MemMapEntry *memmap = spike_memmap;
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
SpikeState *s = SPIKE_MACHINE(machine);
|
2019-04-20 05:24:26 +03:00
|
|
|
MemoryRegion *system_memory = get_system_memory();
|
|
|
|
|
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
|
2022-12-29 13:31:23 +03:00
|
|
|
target_ulong firmware_end_addr = memmap[SPIKE_DRAM].base;
|
2024-08-17 03:25:02 +03:00
|
|
|
hwaddr firmware_load_addr = memmap[SPIKE_DRAM].base;
|
2022-12-29 13:31:23 +03:00
|
|
|
target_ulong kernel_start_addr;
|
|
|
|
|
char *firmware_name;
|
2020-07-01 21:39:47 +03:00
|
|
|
uint32_t fdt_load_addr;
|
2020-07-01 21:39:48 +03:00
|
|
|
uint64_t kernel_entry;
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
char *soc_name;
|
|
|
|
|
int i, base_hartid, hart_count;
|
2022-12-29 13:31:23 +03:00
|
|
|
bool htif_custom_base = false;
|
2019-04-20 05:24:26 +03:00
|
|
|
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
/* Check socket count limit */
|
|
|
|
|
if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
|
|
|
|
|
error_report("number of sockets/nodes should be less than %d",
|
|
|
|
|
SPIKE_SOCKETS_MAX);
|
|
|
|
|
exit(1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Initialize sockets */
|
|
|
|
|
for (i = 0; i < riscv_socket_count(machine); i++) {
|
|
|
|
|
if (!riscv_socket_check_hartids(machine, i)) {
|
|
|
|
|
error_report("discontinuous hartids in socket%d", i);
|
|
|
|
|
exit(1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
base_hartid = riscv_socket_first_hartid(machine, i);
|
|
|
|
|
if (base_hartid < 0) {
|
|
|
|
|
error_report("can't find hartid base for socket%d", i);
|
|
|
|
|
exit(1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
hart_count = riscv_socket_hart_count(machine, i);
|
|
|
|
|
if (hart_count < 0) {
|
|
|
|
|
error_report("can't find hart count for socket%d", i);
|
|
|
|
|
exit(1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
soc_name = g_strdup_printf("soc%d", i);
|
|
|
|
|
object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
|
|
|
|
|
TYPE_RISCV_HART_ARRAY);
|
|
|
|
|
g_free(soc_name);
|
|
|
|
|
object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
|
|
|
|
|
machine->cpu_type, &error_abort);
|
|
|
|
|
object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
|
|
|
|
|
base_hartid, &error_abort);
|
|
|
|
|
object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
|
|
|
|
|
hart_count, &error_abort);
|
2022-05-14 09:29:40 +03:00
|
|
|
sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
|
|
|
|
|
/* Core Local Interruptor (timer and IPI) for each socket */
|
2021-08-31 14:06:01 +03:00
|
|
|
riscv_aclint_swi_create(
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
|
2021-08-31 14:06:01 +03:00
|
|
|
base_hartid, hart_count, false);
|
|
|
|
|
riscv_aclint_mtimer_create(
|
|
|
|
|
memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size +
|
|
|
|
|
RISCV_ACLINT_SWI_SIZE,
|
|
|
|
|
RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
|
|
|
|
|
RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
|
|
|
|
|
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
}
|
2019-04-20 05:24:26 +03:00
|
|
|
|
|
|
|
|
/* register system main memory (actual RAM) */
|
|
|
|
|
memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
|
2021-10-20 04:41:12 +03:00
|
|
|
machine->ram);
|
2019-04-20 05:24:26 +03:00
|
|
|
|
|
|
|
|
/* boot rom */
|
|
|
|
|
memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
|
|
|
|
|
memmap[SPIKE_MROM].size, &error_fatal);
|
|
|
|
|
memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
|
|
|
|
|
mask_rom);
|
|
|
|
|
|
2022-12-29 13:31:23 +03:00
|
|
|
/* Find firmware */
|
|
|
|
|
firmware_name = riscv_find_firmware(machine->firmware,
|
|
|
|
|
riscv_default_firmware_name(&s->soc[0]));
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Test the given firmware or kernel file to see if it is an ELF image.
|
|
|
|
|
* If it is an ELF, we assume it contains the symbols required for
|
|
|
|
|
* the HTIF console, otherwise we fall back to use the custom base
|
|
|
|
|
* passed from device tree for the HTIF console.
|
|
|
|
|
*/
|
|
|
|
|
if (!firmware_name && !machine->kernel_filename) {
|
|
|
|
|
htif_custom_base = true;
|
|
|
|
|
} else {
|
|
|
|
|
if (firmware_name) {
|
|
|
|
|
htif_custom_base = !spike_test_elf_image(firmware_name);
|
|
|
|
|
}
|
|
|
|
|
if (!htif_custom_base && machine->kernel_filename) {
|
|
|
|
|
htif_custom_base = !spike_test_elf_image(machine->kernel_filename);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Load firmware */
|
|
|
|
|
if (firmware_name) {
|
|
|
|
|
firmware_end_addr = riscv_load_firmware(firmware_name,
|
2024-08-17 03:25:02 +03:00
|
|
|
&firmware_load_addr,
|
2022-12-29 13:31:23 +03:00
|
|
|
htif_symbol_callback);
|
|
|
|
|
g_free(firmware_name);
|
|
|
|
|
}
|
2020-04-27 11:06:43 +03:00
|
|
|
|
2023-01-02 14:52:35 +03:00
|
|
|
/* Create device tree */
|
2023-01-11 20:09:39 +03:00
|
|
|
create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base);
|
2023-01-02 14:52:35 +03:00
|
|
|
|
2022-01-13 17:50:39 +03:00
|
|
|
/* Load kernel */
|
2019-04-20 05:24:26 +03:00
|
|
|
if (machine->kernel_filename) {
|
2021-01-16 02:00:27 +03:00
|
|
|
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
|
2020-10-14 03:17:33 +03:00
|
|
|
firmware_end_addr);
|
|
|
|
|
|
2023-02-06 17:00:20 +03:00
|
|
|
kernel_entry = riscv_load_kernel(machine, &s->soc[0],
|
|
|
|
|
kernel_start_addr,
|
2023-02-06 17:00:21 +03:00
|
|
|
true, htif_symbol_callback);
|
2020-07-01 21:39:48 +03:00
|
|
|
} else {
|
|
|
|
|
/*
|
|
|
|
|
* If dynamic firmware is used, it doesn't know where is the next mode
|
|
|
|
|
* if kernel argument is not set.
|
|
|
|
|
*/
|
|
|
|
|
kernel_entry = 0;
|
2019-04-20 05:24:26 +03:00
|
|
|
}
|
|
|
|
|
|
2023-02-01 20:12:11 +03:00
|
|
|
fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base,
|
hw/riscv: change riscv_compute_fdt_addr() semantics
As it is now, riscv_compute_fdt_addr() is receiving a dram_base, a
mem_size (which is defaulted to MachineState::ram_size in all boards)
and the FDT pointer. And it makes a very important assumption: the DRAM
interval dram_base + mem_size is contiguous. This is indeed the case for
most boards that use a FDT.
The Icicle Kit board works with 2 distinct RAM banks that are separated
by a gap. We have a lower bank with 1GiB size, a gap follows, then at
64GiB the high memory starts. MachineClass::default_ram_size for this
board is set to 1.5Gb, and machine_init() is enforcing it as minimal RAM
size, meaning that there we'll always have at least 512 MiB in the Hi
RAM area.
Using riscv_compute_fdt_addr() in this board is weird because not only
the board has sparse RAM, and it's calling it using the base address of
the Lo RAM area, but it's also using a mem_size that we have guarantees
that it will go up to the Hi RAM. All the function assumptions doesn't
work for this board.
In fact, what makes the function works at all in this case is a
coincidence. Commit 1a475d39ef54 introduced a 3GB boundary for the FDT,
down from 4Gb, that is enforced if dram_base is lower than 3072 MiB. For
the Icicle Kit board, memmap[MICROCHIP_PFSOC_DRAM_LO].base is 0x80000000
(2 Gb) and it has a 1Gb size, so it will fall in the conditions to put
the FDT under a 3Gb address, which happens to be exactly at the end of
DRAM_LO. If the base address of the Lo area started later than 3Gb this
function would be unusable by the board. Changing any assumptions inside
riscv_compute_fdt_addr() can also break it by accident as well.
Let's change riscv_compute_fdt_addr() semantics to be appropriate to the
Icicle Kit board and for future boards that might have sparse RAM
topologies to worry about:
- relieve the condition that the dram_base + mem_size area is contiguous,
since this is already not the case today;
- receive an extra 'dram_size' size attribute that refers to a contiguous
RAM block that the board wants the FDT to reside on.
Together with 'mem_size' and 'fdt', which are now now being consumed by a
MachineState pointer, we're able to make clear assumptions based on the
DRAM block and total mem_size available to ensure that the FDT will be put
in a valid RAM address.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230201171212.1219375-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-02-01 20:12:12 +03:00
|
|
|
memmap[SPIKE_DRAM].size,
|
|
|
|
|
machine);
|
2023-02-01 20:12:11 +03:00
|
|
|
riscv_load_fdt(fdt_load_addr, machine->fdt);
|
2022-09-26 20:38:54 +03:00
|
|
|
|
2020-07-01 21:39:46 +03:00
|
|
|
/* load the reset vector */
|
2024-08-17 03:25:02 +03:00
|
|
|
riscv_setup_rom_reset_vec(machine, &s->soc[0], firmware_load_addr,
|
2020-12-16 21:22:37 +03:00
|
|
|
memmap[SPIKE_MROM].base,
|
2020-07-01 21:39:48 +03:00
|
|
|
memmap[SPIKE_MROM].size, kernel_entry,
|
2022-07-28 21:19:26 +03:00
|
|
|
fdt_load_addr);
|
2019-04-20 05:24:26 +03:00
|
|
|
|
|
|
|
|
/* initialize HTIF using symbols found in load_kernel */
|
2022-12-29 13:31:23 +03:00
|
|
|
htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base,
|
|
|
|
|
htif_custom_base);
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
}
|
2019-04-20 05:24:26 +03:00
|
|
|
|
2023-04-05 12:57:20 +03:00
|
|
|
static void spike_set_signature(Object *obj, const char *val, Error **errp)
|
|
|
|
|
{
|
|
|
|
|
sig_file = g_strdup(val);
|
|
|
|
|
}
|
|
|
|
|
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
static void spike_machine_instance_init(Object *obj)
|
|
|
|
|
{
|
2019-04-20 05:24:26 +03:00
|
|
|
}
|
2018-03-02 15:31:13 +03:00
|
|
|
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
static void spike_machine_class_init(ObjectClass *oc, void *data)
|
2019-04-20 05:24:26 +03:00
|
|
|
{
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
|
|
mc->desc = "RISC-V Spike board";
|
2019-04-20 05:24:26 +03:00
|
|
|
mc->init = spike_board_init;
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
mc->max_cpus = SPIKE_CPUS_MAX;
|
2020-02-07 19:19:47 +03:00
|
|
|
mc->is_default = true;
|
2020-12-16 21:22:32 +03:00
|
|
|
mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
|
|
|
|
|
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
|
|
|
|
|
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
|
|
|
|
|
mc->numa_mem_supported = true;
|
2023-05-09 03:27:39 +03:00
|
|
|
/* platform instead of architectural choice */
|
|
|
|
|
mc->cpu_cluster_has_numa_boundary = true;
|
2021-10-20 04:41:12 +03:00
|
|
|
mc->default_ram_id = "riscv.spike.ram";
|
2023-04-05 12:57:20 +03:00
|
|
|
object_class_property_add_str(oc, "signature", NULL, spike_set_signature);
|
|
|
|
|
object_class_property_set_description(oc, "signature",
|
|
|
|
|
"File to write ACT test signature");
|
|
|
|
|
object_class_property_add_uint8_ptr(oc, "signature-granularity",
|
|
|
|
|
&line_size, OBJ_PROP_FLAG_WRITE);
|
|
|
|
|
object_class_property_set_description(oc, "signature-granularity",
|
|
|
|
|
"Size of each line in ACT signature "
|
|
|
|
|
"file");
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const TypeInfo spike_machine_typeinfo = {
|
|
|
|
|
.name = MACHINE_TYPE_NAME("spike"),
|
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
|
.class_init = spike_machine_class_init,
|
|
|
|
|
.instance_init = spike_machine_instance_init,
|
|
|
|
|
.instance_size = sizeof(SpikeState),
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void spike_machine_init_register_types(void)
|
|
|
|
|
{
|
|
|
|
|
type_register_static(&spike_machine_typeinfo);
|
2018-03-02 15:31:13 +03:00
|
|
|
}
|
|
|
|
|
|
hw/riscv: spike: Allow creating multiple NUMA sockets
We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.
By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.
Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"
Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"
The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-14 14:09:43 +03:00
|
|
|
type_init(spike_machine_init_register_types)
|