Also, remove the no_temperature var to keep only the enable_temperature flag
Older Atom still have the enable_temperature flag hard-coded to false until further tests are done
Read the memory controller configuration (instead of just relying on SPD data) to get the actual live settings.
Currently supported platforms:
* Intel SNB to RPL (Core 2nd Gen to Core 13th Gen) - Desktop only (no Server nor Mobile)
* AMD SMR to RPL (Zen to Zen4) - Desktop only (no Server, Mobile nor APU).
Individual commits below for archival:
* First functions skeleton for reading IMC/ECC Registers
* Change directory name from 'chipsets' to 'mch' (Memory Controller Hub)
* Add Intel HSW and fix new files encoding
* First Intel HSW IMC implementation
* Add an option to disable MCH registers polling
* Remove old include from Makefiles
* Better Makefile and padding fixes
* Statically init 'imc' struct to generate string relocation record
* Small typos & code fixes
* Add IMC support for Intel Core 6/7/8/9th Gen (SKL/KBL/CFL/CML) This is a bit more complex than Haswell and below because MMIO switched to 64-bit with Skylake (lot of) betatesting needed
* Add IMC read support for Intel SNB/IVB (2nd/3rd gen Core)
* Fix hard-lock on Intel SNB/IVB due to wrong access type on MCHBAR pointer
* Move AMD SMN Registers & offsets to a specific header file
* Add IMC Read support for AMD Zen/Zen2 CPUs
* Change 'IMC' to 'MCH' in Makefiles to match actual mch/ directory
* Add IMC Reading support for Intel ADL&RPL CPUs (Core Gen12&13)
* Add support for Intel Rocket Lake (Core 11th Gen) and AMD Vermeer
* Add IMC reading for AMD Zen4 'Raphael' AM5 CPUs
* Various Cleanup #1
Change terminology from Intel-based 'MCH' (Memory Controller Hub) to more universal 'IMC' (Integrated Memory Controller) Integrate imc_type var into imc struct. Remove previously created AMD SNM header file
* Various Cleanup 2
* Change DDR5 display format for IMC specs
DDR5 Freq can be > 10000 and timings up to 63-127-127-127, which overwflow the available space.
This commit remove the raw frequency on DDR5 (which may be incorrect due to Gear mechanism) and leave a bit of space to display the Gear engaged in the future
* BadRAM: Rename pattern -> patterns
* BadRAM: Refactor COMBINE_MASK and add clarifying comment
* BadRAM: Extract DEFAULT_MASK into variable
* BadRAM: Add is_covered() for checking if pattern is already covered by one of the existing patterns
* BadRAM: Initialize patterns to 0
* BadRAM: Change how addr/masks are merged to minimize number of addresses covered by badram
Prior to this patch, a list of up to MAX_PATTERNS (=10) addr/mask tuples
(aka. pattern) were maintained, adding failing addresses one by one to
the list until it was full. When full, space was created by forcing a
merge of the new address with the existing pattern that would grow the
least (with regards to number of addresses covered by the pattern) by
merging it with the new address. This can lead to a great imbalance in
the number of addresses covered by the patterns. Consider the following:
MAX_PATTERNS=4 (for illustrative purposes).
The following addresses are faulted and added to patterns:
0x00, 0x10, 0x20, 0x68, 0xa0, 0xb0, 0xc0, 0xd0
This is the end result with the implementation prior to this commit:
patterns = [
(0x00, 0xe8),
(0x00, 0x18),
(0x68, 0xf8),
(0x90, 0x98)
]
Total addresses covered: 120.
This commit changes how the merges are done, not only considering a
merge between the new address and existing patterns, but also between
existing patterns. It keeps the patterns in ascending order (by .addr)
in patterns, and a new address is always inserted into patterns (even if
num_patterns == MAX_PATTERNS, patterns is of MAX_PATTERNS+1 size). Then,
if num_patterns > MAX_PATTERNS, we find the pair of patterns (only
considering neighbours, assuming for any pattern i, i-1 or i+1 will
be the best candidate for a merge) that would be the cheapest to
merge (using the same metric as prior to this patch), and merge those.
With this commit, this is the result of the exact same sequence of
addresses as above:
[
(0x00, 0xe0),
(0x68, 0xf8),
(0xa0, 0xe8),
(0xc0, 0xe8)
]
Total addresses covered: 72.
A drawback of the current implementation (as compared to the prior)
is that it does not make any attempt at merging patterns until
num_patterns == MAX_PATTERNS, which can lead to having several patterns
that could've been merged into one at no additional cost. I.e.:
patterns = [
(0x00, 0xf8),
(0x08, 0xf8)
]
can appear, even if
patterns = [
(0x00, 0xf0)
]
represents the exact same addresses with one pattern instead of two.
* fixup! BadRAM: Change how addr/masks are merged to minimize number of addresses covered by badram
Co-authored-by: Anders Wenhaug <anders.wenhaug@solutionseeker.no>
smp_init() used to be called after the startup dialogue, so F2 only
needed to change the enable_smp flag. Now smp_init() is called earlier,
we also need to reset num_available_cpus.
By default, don't re-display FAIL banner after it has been discarded (#130 & #173)
Add an option to re-display FAIL banner even if previously discarded
* Avoid FAIL banner being partially overwriten by new errors
* Remove beta on main title
* Remove v6 Beta Disclaimer & some README.me changes for release
* [DDR5] Fix rounding errors on SPD Timings
* [DDR5] Add a rounding factor of ~0.3% according to JEDEC to solve the last rounding issue found on NETAC Modules
* [DDR5] Add missing package ranks per channel parameter in total module capacity algorithm
* [DDR4] Fix rounding issues in SPD timings & frequency
* [DDR3] Fix rounding issues in SPD timings & frequency decoding. Check XMP Profile #2. Add a quirk for Kingston based on very early XMP 1.0 specs
* [DDR2] Fix CAS detection & rounding issues in SPD timings w/ EPP
* [DDR] Correct SPD timings rounding issues & add support for x.5 CAS latencies
* [SDR] Correct SPD Timings decoding due to rounding errors
* Add various JEP106 Manufacturers found while debugging
* Update timings display function to handle x.5 CAS
Most legacy BIOSs will support USB legacy keyboard emulation. Using that
will avoid having to reserve memory for the USB drivers, and should
improve the chance of having a working keyboard without having to work
around various USB device quirks.
* Add new heap manager.
* Convert OHCI driver to use new heap manager.
* Convert UHCI driver to use new heap manager.
* Convert EHCI driver to use new heap manager.
* Convert XHCI driver to use new heap manager.
* Convert SMP to use new heap manager.
* Add a "usbinit" boot option to handle various buggy USB devices.
This replaces the "keyboard=buggy-usb" option, and adds a second
workaround to handle the problem seen in issue #107.
Add AP Enumeration to distinguish E-Core from P-Core on Intel Hybrid CPUs, and exclude them from the selected cores by default. Including E-Cores slows down some tests and takes longer to catch memory errors.
A new exclude_ecores flag has been added in config.c to include E-Cores if needed.
- Enable VGA/FB to output box drawing characters while maintaining VT100
character set for serial. Shorten and simplify the screen setup code.
- Track the background color to decide if the serial output needs to be
inverted. Remove no longer needed logic for known areas of the screen that
need to be inverted. As a bonus - popup menu can now be also inverted on
serial.
- Reduce the amount of data sent to serial by using CR+LF when possible
instead of always relying on absolute positioning. Add tty_print()
for positioning the cursor, remove no longer needed tty_print().
- Remove no longer needed "LF -> LF+CR" logic from serial_echo_print().
Before (gcc-11.3.0-x86_64):
text data bss total filename
929 357 64 1350 system/serial.o
3517 1356 54 4927 app/display.o
After (gcc-11.3.0-x86_64):
text data bss total filename
907 336 64 1307 system/serial.o
3442 1242 54 4738 app/display.o
Co-authored-by: Sam Demeulemeester <38105886+x86fr@users.noreply.github.com>
When USB keyboard detection is enabled, physical memory pages are reserved
for use by the USB drivers. The physical memory map exposed by pmem.h does
not indicate where the ACPI tables reside, so we may end up using pages
that contain ACPI tables (or for that matter, the boot parameters and boot
command line). So rather than introduce a more complicated memory allocation
scheme, make sure we have finished with all the data passed to us by the
BIOS and/or boot loader before we start probing for USB devices.
The only downside to this is that it is no longer possible to interactively
disable parsing of the ACPI tables - that can now only be done by using the
"nosmp" boot option.
* Improve abstraction in vmem.h and limit memory benchmarking to first 2GB.
The third GB may get used for remapping memory regions that are only
accessed during startup, so it's not safe to use it for the memory
speed tests.
* Fix calculation of end limit for locating memory benchmark workspace.
* Document vmem.h.
* Use window number, not current start address, to detect first window.
* Increase the program low-load range from 1MB to 4MB and make more robust.
If the BIOS has reserved some parts of low memory, there may not be
enough contiguous space left to load the program there (issue #49).
So increase the low-load range to include the first 3MB of high
memory. Also guard against the program being initially loaded
straddling the new boundary.
Co-authored-by: Martin Whitaker <memtest@martin-whitaker.me.uk>
If the usbdebug option is present, pause at the end of the USB scan until
a key is pressed. Otherwise, if the keyboard=usb option is present and no
USB keyboards were discovered, pause for 10 seconds. Otherwise don't pause.
Lionel Debroux