Commit Graph

18 Commits

Author SHA1 Message Date
Sam Demeulemeester 262aac4f85
[SMBUS] Add support for ALi M1533/1535/1543C (#273)
Closes #126
2023-02-20 18:31:33 +01:00
Sam Demeulemeester 66bd82f12a
[SMBus] Add support for ALi M1563 Southbridge (#272) 2023-02-19 17:29:56 +01:00
Sam Demeulemeester 10e8435604 Add SPD support for legacy VIA Southbridges (VT82C686A/B & VT8235)
(From PR #236)

Author: Corentin Labbe clabbe.montjoie@gmail.com
Co-developed-by: Lionel Debroux lionel_debroux@yahoo.fr
2023-01-23 15:01:48 +01:00
Lionel Debroux 1c4d7f4089
Document PCI vendor and device IDs for several SMBus controller models from SiS, EFAR and ALi; move the PCI vendor ID defines from system/smbus.h to system/pci.h and add several vendor IDs; use the defines from system/pci.h in system/hwquirks.c. (#154)
Inspired by #126.
2022-09-14 18:57:10 +02:00
01e3 43b0f64ddb smbus: refactor SPD SKU (part number) handling
Replace SPD SKU reading code repeated multiple times across
all the parse_spd_* functions with a dedicated read_sku function.

Convert spd_infos.sku from len+data into classic NULL-terminated C-string.
Takes the same space, but simplifies handling. Also, use char instead of
uint8_t so no conversion is needed when printing.

Change the way how the end of part number is handled. Stop on the first
non-ASCII character and then trim all trailing spaces. This allows SKUs
with two (or more) spaces inside the name to be handled properly.

Finally, fix incorrect / inconsistent part number length handling, with
the following end result:
 - parse_spd_sdram: 18 [73-90] (no change)
 - parse_spd_rdram: 18 [73-90] (no change)
 - parse_spd_ddr:   18 [73-90] (no change)
 - parse_spd_ddr2:  18 [73-90] (no change)
 - parse_spd_ddr3:  20+1=21 -> 18 [128-145]
 - parse_spd_ddr4:  20+1=21 -> 20 [329-348]
 - parse_spd_ddr5:  29+1=30 -> 30 [521-550] (technicaly no change)

Before:
      text       data        bss      total filename
     13143       3795         18      16956 build32/system/smbus.o
     11735       4359         18      16112 build64/system/smbus.o

     81705      51133      13088     145926 build32/memtest_shared
     79686      58109     294432     432227 build64/memtest_shared

After:
      text       data        bss      total filename
     10784       3887         18      14689 build32/system/smbus.o
     10486       4399         18      14903 build64/system/smbus.o

     79353      51101      13088     143542 build32/memtest_shared
     78438      58077     294432     430947 build64/memtest_shared

gcc-11.3.0.
2022-08-28 18:14:41 +02:00
Sam Demeulemeester 0f8981412c
Various fixes on SPD decoding algorithms (#152)
* [DDR5] Fix rounding errors on SPD Timings

* [DDR5] Add a rounding factor of ~0.3% according to JEDEC to solve the last rounding issue found on NETAC Modules

* [DDR5] Add missing package ranks per channel parameter in total module capacity algorithm

* [DDR4] Fix rounding issues in SPD timings & frequency

* [DDR3] Fix rounding issues in SPD timings & frequency decoding. Check XMP Profile #2. Add a quirk for Kingston based on very early XMP 1.0 specs

* [DDR2] Fix CAS detection & rounding issues in SPD timings w/ EPP

* [DDR] Correct SPD timings rounding issues & add support for x.5 CAS latencies

* [SDR] Correct SPD Timings decoding due to rounding errors

* Add various JEP106 Manufacturers found while debugging

* Update timings display function to handle x.5 CAS
2022-08-26 21:56:12 +02:00
a1346054 9660eead4e
Simple maintenance improvements (#145)
* Fix typos

* Add missing final newline

* Trim trailing whitespace
2022-08-15 17:51:48 +02:00
Lionel Debroux e86b04a14a Perform major simplification in smbus.c to reduce code size while keeping the functions readable, removing several unused strings and unnecessary arguments passed to several functions.
Add a bunch of PCI device IDs and driver indications for other SMBus controllers, so as to avoid other persons having to do that work again.
Add support for two PIIX4 devices: the standard PIIX4 PCI device ID, and the ServerWorks CSB5, which has a slight twist.

Co-authored-by: Lionel Debroux <lionel_debroux@yahoo.fr>
Co-authored-by: Sam Demeulemeester <sam@x86.fr>
2022-06-06 22:24:09 +02:00
Sam Demeulemeester 69aeda1c27 Discard Memory SKU when filled with 0xFF. Remove a debug function forgotten there 2022-05-24 01:13:37 +02:00
Sam Demeulemeester 7c969db4da Add support for nVidia nForce2 MCP (#86) 2022-05-24 01:00:52 +02:00
Sam Demeulemeester 3bc72c1fd4 Remove unused strings and useless smb_idx argument in get_spd() 2022-05-20 19:10:00 +02:00
Sam Demeulemeester e0cee8e2c3 Add SMBUS support for Intel 82371AB (PIIX4) and AMD Bulldozer/Kabini (SB800/900) 2022-05-20 18:07:22 +02:00
Lionel Debroux caa07482a0 Reorganize struct spd_infos for better alignment (#2), fix left shifts of count > width of type, fix whitespace, improve comments. 2022-05-19 18:45:13 +02:00
Sam Demeulemeester 6fca9bedc9 Rework Line 9. Add DDR1->DDR5 Timing Detection to display on this line 2022-04-16 13:31:28 +02:00
Sam Demeulemeester a4f1ba37b3 Add support for AMD Ryzen FCH (#21) 2022-03-27 23:47:57 +02:00
Sam Demeulemeester b22c032b5a Add support for DDR5 in smbus.c. Major rework of various related functions (#2) 2022-03-24 21:49:56 +01:00
Sam DEMEULEMEESTER f9690813ca New code base for SMBUS / SPD access (#2) - WIP 2022-03-24 21:49:56 +01:00
Sam DEMEULEMEESTER 2266151fe6 Early SMBUS functions (#2) & EFI Reset (#17) 2022-03-24 21:49:56 +01:00