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verilog syntax: added IEEE1364-2005 missing keywords

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Signed-off-by: Andrew Borodin <aborodin@vmail.ru>
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Purdea Andrei 2020-06-01 21:00:25 +03:00 committed by Andrew Borodin
parent b0927b0627
commit 0cdb39d76f
1 changed files with 3 additions and 0 deletions
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misc/syntax/verilog.syntax
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@ -166,6 +166,9 @@ context default
keyword whole unsigned yellow
keyword whole use yellow
#Reserved Keywords IEEE1364-2005
keyword whole uwire yellow
#Reserved Keywords 2
keyword whole $bitstoreal yellow