diff --git a/misc/syntax/verilog.syntax b/misc/syntax/verilog.syntax
index c1b5b6a03..46fc96179 100644
--- a/misc/syntax/verilog.syntax
+++ b/misc/syntax/verilog.syntax
@@ -166,6 +166,9 @@ context default
     keyword  whole  unsigned yellow
     keyword  whole  use yellow
 
+#Reserved Keywords IEEE1364-2005
+    keyword  whole  uwire yellow
+
 #Reserved Keywords 2
 
     keyword  whole  $bitstoreal yellow