From 0cdb39d76f2034732c3503a855be960f52d799db Mon Sep 17 00:00:00 2001
From: Purdea Andrei <andrei.purdea@intel.com>
Date: Mon, 1 Jun 2020 21:00:25 +0300
Subject: [PATCH] verilog syntax: added IEEE1364-2005 missing keywords

Signed-off-by: Andrew Borodin <aborodin@vmail.ru>
---
 misc/syntax/verilog.syntax | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/misc/syntax/verilog.syntax b/misc/syntax/verilog.syntax
index c1b5b6a03..46fc96179 100644
--- a/misc/syntax/verilog.syntax
+++ b/misc/syntax/verilog.syntax
@@ -166,6 +166,9 @@ context default
     keyword  whole  unsigned yellow
     keyword  whole  use yellow
 
+#Reserved Keywords IEEE1364-2005
+    keyword  whole  uwire yellow
+
 #Reserved Keywords 2
 
     keyword  whole  $bitstoreal yellow