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Bochs/bochs/cpu/cpudb
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Stanislav Shwartsman c74f590077 implemented TSC-Deadline APIC timer mode
2011-11-21 12:51:50 +00:00
..
amd_k6_2_chomper.cc
Supply real VMX capabilities together with the CPU MODEL .bochsrc option.
2011-09-26 12:31:40 +00:00
amd_k6_2_chomper.h
support more than 32-bit cpu features vector
2011-09-14 20:22:24 +00:00
amd_k6_2_chomper.txt
- Fixed compilation issue with cpu-level=5
2011-08-30 22:00:27 +00:00
athlon64_clawhammer.cc
Supply real VMX capabilities together with the CPU MODEL .bochsrc option.
2011-09-26 12:31:40 +00:00
athlon64_clawhammer.h
support more than 32-bit cpu features vector
2011-09-14 20:22:24 +00:00
athlon64_clawhammer.txt
Added another CPU to CPUDB: p4_willamette (one more without x86-64 support).
2011-07-31 18:43:46 +00:00
atom_n270.cc
added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch
2011-10-07 19:32:44 +00:00
atom_n270.h
added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch
2011-10-07 19:32:44 +00:00
atom_n270.txt
dos2unix
2011-08-03 17:50:23 +00:00
core2_penryn_t9600.cc
added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch
2011-10-07 19:32:44 +00:00
core2_penryn_t9600.h
added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch
2011-10-07 19:32:44 +00:00
core2_penryn_t9600.txt
dos2unix for generic_cpuid.cc
2011-08-08 18:20:29 +00:00
core_duo_t2400_yonah.cc
added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch
2011-10-07 19:32:44 +00:00
core_duo_t2400_yonah.h
added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch
2011-10-07 19:32:44 +00:00
core_duo_t2400_yonah.txt
added yonah CPUID to cpudb. remove bxversion.h from dep files
2011-08-16 19:58:56 +00:00
corei5_arrandale_m520.cc
- Implemented VM Functions support and EPTP-Switching VM Functions
2011-11-05 07:31:51 +00:00
corei5_arrandale_m520.h
fixed compilation w/o AVX
2011-10-09 13:56:39 +00:00
corei5_arrandale_m520.txt
added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch
2011-10-07 19:32:44 +00:00
corei7_sandy_bridge_2600K.cc
implemented TSC-Deadline APIC timer mode
2011-11-21 12:51:50 +00:00
corei7_sandy_bridge_2600K.h
added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch
2011-10-07 19:32:44 +00:00
corei7_sandy_bridge_2600K.txt
Added another CPU to CPUDB: p4_willamette (one more without x86-64 support).
2011-07-31 18:43:46 +00:00
Makefile.in
added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch
2011-10-07 19:32:44 +00:00
p2_klamath.cc
- Now you could disable x86-64 from .bochsrc so now it is possible to emulate
2011-09-25 17:36:20 +00:00
p2_klamath.h
- Now you could disable x86-64 from .bochsrc so now it is possible to emulate
2011-09-25 17:36:20 +00:00
p2_klamath.txt
Added P2 Klamath CPUID + some code reorg again
2011-08-11 18:06:09 +00:00
p3_katmai.cc
- Now you could disable x86-64 from .bochsrc so now it is possible to emulate
2011-09-25 17:36:20 +00:00
p3_katmai.h
- Now you could disable x86-64 from .bochsrc so now it is possible to emulate
2011-09-25 17:36:20 +00:00
p3_katmai.txt
Added another CPU to CPUDB: p4_willamette (one more without x86-64 support).
2011-07-31 18:43:46 +00:00
p4_prescott_celeron_336.cc
- Now you could disable x86-64 from .bochsrc so now it is possible to emulate
2011-09-25 17:36:20 +00:00
p4_prescott_celeron_336.h
support more than 32-bit cpu features vector
2011-09-14 20:22:24 +00:00
p4_prescott_celeron_336.txt
Added another CPU to CPUDB: p4_willamette (one more without x86-64 support).
2011-07-31 18:43:46 +00:00
p4_willamette.cc
- Now you could disable x86-64 from .bochsrc so now it is possible to emulate
2011-09-25 17:36:20 +00:00
p4_willamette.h
- Now you could disable x86-64 from .bochsrc so now it is possible to emulate
2011-09-25 17:36:20 +00:00
p4_willamette.txt
Added another CPU to CPUDB: p4_willamette (one more without x86-64 support).
2011-07-31 18:43:46 +00:00
pentium_mmx.cc
- Now you could disable x86-64 from .bochsrc so now it is possible to emulate
2011-09-25 17:36:20 +00:00
pentium_mmx.h
support more than 32-bit cpu features vector
2011-09-14 20:22:24 +00:00
pentium_mmx.txt
added pentium mmx to cpudb. for now only can be enabled when cpu-level=5
2011-08-16 19:04:36 +00:00