13 Commits

Author SHA1 Message Date
Stanislav Shwartsman
9f57e70d5f Rewritten handling of supported CPUID features to be able to handle large amount of CPU extensions
Now enable support for up to 128 CPU extensions and could easily extend it more
Also reduce memory footprint for bx_ia_opcodes.h arrays
2014-08-31 18:39:18 +00:00
Stanislav Shwartsman
378e7e16eb fixed major code duplication in CPUDB classes 2014-03-15 19:24:42 +00:00
Stanislav Shwartsman
720a9b2fb7 fixed 64-bit segment print from internal debugger 2012-06-14 18:56:47 +00:00
Stanislav Shwartsman
708fc666c8 Added Corei7 ivyBridge configuration to CPUDB 2012-05-07 12:31:22 +00:00
Stanislav Shwartsman
bb7a648d91 Major commit !
------------

Implemented SVN nested paging support - the Virtual Box boots perfectly with Nested Paging guest !
A lot of code duplication was added for now - major cleanup will follow later.

! Added AMD Phenom X3 8650 (Toliman) configuration to the CPUDB - this configuration has Nested Paging enabled.

Some CPUID modules rework done to enable Toliman configuration.

Ckean up 'executable' attribute from all CPU source files.
2012-02-13 23:29:01 +00:00
Stanislav Shwartsman
7defa74261 cleaned up code duplication in CPUDB classes 2012-01-07 17:06:03 +00:00
Stanislav Shwartsman
8ada4ce5e4 added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch 2011-10-07 19:32:44 +00:00
Stanislav Shwartsman
62d0c8abf7 - Now you could disable x86-64 from .bochsrc so now it is possible to emulate
32-bit CPU using Bochs binary compiled with x86-64 support.

The commit also fixes some init.cc issues with initialization of SYSCALL/SYSRET MSR in AMD hosts and also includes code reorg.
2011-09-25 17:36:20 +00:00
Stanislav Shwartsman
e2f0880f1c support more than 32-bit cpu features vector 2011-09-14 20:22:24 +00:00
Stanislav Shwartsman
1b27438146 cleanups + small code reorg 2011-08-10 20:31:29 +00:00
Stanislav Shwartsman
360481b391 infastructure for RDMSR/WRMSR control for cpuid class
now the order is going to be:

1. MSRs emulated in Bochs (msr.cc)
2. MSRs emulated in model specific derivative class of cpuid_t
3. MSR can be loaded from msrs.def file
4. MSR is not found. We can fault or ignore based on ignore_bad_msrs option
2011-08-09 22:11:56 +00:00
Stanislav Shwartsman
1068b4bd8c cleanup 2011-08-03 21:46:46 +00:00
Stanislav Shwartsman
075db389a9 added atom n270 cpuid + small fixes 2011-08-03 17:49:49 +00:00