Stanislav Shwartsman
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b891789c3d
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implemented (experimental) TSC Adjust MSR
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2020-05-21 19:58:16 +00:00 |
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Stanislav Shwartsman
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dd3849b9e0
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extract Bit128 arithmetic to separate wide_int.cc/wide_int.h compiled independently of long mode emulation
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2020-05-19 16:01:23 +00:00 |
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Stanislav Shwartsman
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e50a3f8169
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fixup code duplication in apic code
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2020-05-17 19:32:14 +00:00 |
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Stanislav Shwartsman
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f97b20ddce
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deactivate apic timer when globally disabled
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2020-05-17 19:03:39 +00:00 |
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Stanislav Shwartsman
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da169c0044
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when apic is globally disabled - reset some fields to defaults
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2020-05-17 18:57:27 +00:00 |
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Stanislav Shwartsman
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7a5fef764b
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fix for effcetive TSC compute when TSC multiplier is enabled
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2020-05-17 18:39:52 +00:00 |
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Stanislav Shwartsman
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6ae26b39b3
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fixed Sub-Page-Protection EPT violation (was triggered exactly opposite that excpected due to typo)
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2020-05-17 14:12:29 +00:00 |
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Stanislav Shwartsman
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8e4a29fb0e
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reorg vmcs fields enabling based on their numeric order
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2020-05-15 19:27:45 +00:00 |
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Stanislav Shwartsman
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499b138227
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enable access to XSS_EXITING_BITMAP VMCS field
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2020-05-15 19:05:41 +00:00 |
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Stanislav Shwartsman
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355c06e396
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add defines for CPUID bits recently announced
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2020-04-01 06:15:54 +00:00 |
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Stanislav Shwartsman
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81edc636d4
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remove duplicate opcodes from decoder definitions
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2020-03-28 14:36:27 +00:00 |
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Stanislav Shwartsman
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b686c8d423
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add into ia_opcodes.def disasm field for every instruction
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2020-03-28 14:23:54 +00:00 |
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Stanislav Shwartsman
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7d989b34a3
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fixed recent segoverride assignment bug in SVN
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2020-02-28 15:03:52 +00:00 |
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Stanislav Shwartsman
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6e2541daa6
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CET: DS Seg override is kept for CET Endranch suppress hint even if overridden by other prefixes later
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2020-02-21 19:38:23 +00:00 |
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Stanislav Shwartsman
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086f2779f5
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fixed compilation with avx but without EVEX
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2020-02-20 05:29:13 +00:00 |
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Stanislav Shwartsman
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1b208b0e93
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fixed compilation under Visual Studio
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2020-02-02 07:25:00 +00:00 |
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Stanislav Shwartsman
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6b691257dd
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fixed compilation with VMX off
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2020-01-17 11:55:59 +00:00 |
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Stanislav Shwartsman
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a24b562e32
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now when bios knows to set msr ia32_feature_ctrl, no need to initialize from reset code
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2020-01-15 17:18:10 +00:00 |
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Stanislav Shwartsman
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5620a4968b
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set msr IA32_FEATURE_CTRL lock bit to ensure VMX is enabled - normally this should be done in Bios but init.cc can w/a
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2020-01-11 07:04:44 +00:00 |
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Stanislav Shwartsman
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902ff1ef52
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Part of the SF patch #548: Support Windows Hyper-V in Bochs by Xinyang
When BX_SUPPORT_SMP is not defined, clear the bit in CPUID.[EAX=1].Bit[28] to indicate Hyper-Threading is unavailable.
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2020-01-11 06:18:13 +00:00 |
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Stanislav Shwartsman
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50bde4a38c
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flush TLBs on CR4.CET change
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2020-01-10 20:04:22 +00:00 |
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Stanislav Shwartsman
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72dffd320d
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fixed CET fault on task switch when SSP is not 8-byte aligned. Bochs did #GP whiel SDM says #TS
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2020-01-07 18:17:34 +00:00 |
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Stanislav Shwartsman
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694112732b
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use default base CPUID class method to detemine values of 0x80000008 leaf for IceLake CPUID
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2020-01-03 19:53:20 +00:00 |
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Stanislav Shwartsman
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b69f2b052a
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extract calculation of MSR_IA32_XSS supported bits to a function
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2020-01-03 19:33:16 +00:00 |
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Stanislav Shwartsman
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45a25a2b67
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CET: make sure enbranch64 and enbranch32 do the right thing when mode mismatch
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2020-01-03 18:55:17 +00:00 |
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Stanislav Shwartsman
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495206650b
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fixed CET wrmsr reserved bit checking
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2020-01-03 18:44:15 +00:00 |
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Stanislav Shwartsman
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ea6b0c766c
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added more VMX reasons to enum according to Intel SDM
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2020-01-03 17:35:02 +00:00 |
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Stanislav Shwartsman
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bac9104f73
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fixed compilation of init.cc for old CPU models
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2020-01-03 05:29:45 +00:00 |
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Stanislav Shwartsman
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9a35c6de79
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fix and simplify combined_access handling in EPT page walk
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2019-12-29 21:00:35 +00:00 |
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Stanislav Shwartsman
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016aa349e5
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handle supervisor-shadow-stack protection feature in the EPT
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2019-12-29 20:40:18 +00:00 |
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Stanislav Shwartsman
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4f7aa4bd76
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fixed compilation issue
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2019-12-28 15:20:38 +00:00 |
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Stanislav Shwartsman
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f56e1aab86
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VMX: save CET state to VMCS only if CET is supported
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2019-12-28 15:18:55 +00:00 |
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Stanislav Shwartsman
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bcafd5bb7a
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fix non-printable characters and add more verbose error messages
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2019-12-28 15:08:53 +00:00 |
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Stanislav Shwartsman
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d091e3bda6
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simplify XRSTOR* code
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2019-12-28 14:03:54 +00:00 |
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Stanislav Shwartsman
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126ae0d0b4
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more verbose debug print
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2019-12-28 13:36:43 +00:00 |
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Stanislav Shwartsman
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9458e25486
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reverting commit 13737 and doing correct fix
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2019-12-28 13:11:13 +00:00 |
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Stanislav Shwartsman
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5d7c6d46b0
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fixed compilation after prev commit
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2019-12-28 13:02:02 +00:00 |
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Stanislav Shwartsman
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7f72252223
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fixes in XSAVE/XRSTOR handling
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2019-12-28 12:57:31 +00:00 |
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Stanislav Shwartsman
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b09126aa34
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use enums for assign_srcs error output - help with debugging unexpected #UD cases
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2019-12-27 19:34:32 +00:00 |
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Stanislav Shwartsman
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6879feebf5
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SHA: SHA instructions in 128-bit memory operand require to be explicitly aligned
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2019-12-27 14:24:43 +00:00 |
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Stanislav Shwartsman
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5c45f6b324
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AVX512: EVEX.Z is forbidden for any vector instruction using opmask as source or destination (should cause #UD)
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2019-12-27 14:23:53 +00:00 |
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Stanislav Shwartsman
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8bd5272591
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correctly handle CET Enbranch override prefix 0x3E in 64-bit mode
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2019-12-27 13:44:57 +00:00 |
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Stanislav Shwartsman
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596c197cea
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fix decoder: SHA1RNDS4 instruction should be with no SSE prefix
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2019-12-27 13:08:20 +00:00 |
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Stanislav Shwartsman
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a2be16873c
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VMX: save guest CET state to VMCS on vmexit
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2019-12-27 13:02:30 +00:00 |
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Stanislav Shwartsman
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8e2391c44b
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fixed compilation when compiling without EVEX
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2019-12-26 20:12:40 +00:00 |
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Stanislav Shwartsman
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ff167d0f65
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change a bit more defines to const with type
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2019-12-26 16:48:33 +00:00 |
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Stanislav Shwartsman
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d6c3dcf033
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revert for full vector read until figured out the right behavior for VPSHUFBITQMB
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2019-12-24 20:08:33 +00:00 |
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Stanislav Shwartsman
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edcdce927c
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added ability to configure hidden VMCS field mapping through CPUID
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2019-12-22 18:53:07 +00:00 |
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Stanislav Shwartsman
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fc1dbe68bc
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update dependencies in Mafefile.in
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2019-12-21 21:42:35 +00:00 |
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Stanislav Shwartsman
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e593bb0084
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CPUDB: Allow Icelake-U CPU model to exists without EVEX
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2019-12-21 21:06:34 +00:00 |
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