Stanislav Shwartsman
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f0245b5f2b
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introduce special handlers for zero-idiom instructions - ~1% speedup to simulation. infra for fast string emulation in 64-bit mode
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2019-10-14 06:40:19 +00:00 |
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Stanislav Shwartsman
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4d10852c04
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impemented recently published VP2INTERSECTD/Q instructions
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2019-05-25 19:07:09 +00:00 |
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Stanislav Shwartsman
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54bdb24e4b
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remove MOVDIRI opcode extension for now until fugured out how nicely do MOVDIR64B, they better to be both done with same CPUID feature name
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2019-02-22 19:15:53 +00:00 |
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Stanislav Shwartsman
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4f625b23e0
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enable yet another Bochs new decoder. It is a bit slower than old one but it is much more extendable so adding new opcode won't be nightmare anymore
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2019-02-16 15:23:24 +00:00 |
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Stanislav Shwartsman
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f8ec18acd5
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fix decode/disasm of AVX512-VBMI2 VPSH*D* opcodes
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2019-01-27 18:52:03 +00:00 |
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Stanislav Shwartsman
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6dc5cfe80b
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fixed typo in opcode name
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2019-01-24 20:10:46 +00:00 |
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Stanislav Shwartsman
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fcd9ce1634
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fix compilation without x86_64
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2018-04-15 14:22:16 +00:00 |
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Stanislav Shwartsman
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d000e21001
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added MOVDIRI opcode implementation
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2018-04-06 05:06:36 +00:00 |
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Stanislav Shwartsman
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6566cab8aa
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fixed new disasm for avx2 opcodes
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2017-12-30 18:45:21 +00:00 |
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Stanislav Shwartsman
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4c03fe3e2c
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fixed disasm of vcvtps2ph/ph2ps opcodes
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2017-12-28 19:59:42 +00:00 |
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Stanislav Shwartsman
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ca034f0642
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fixed disasm of sse insertps instruction
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2017-12-21 18:18:10 +00:00 |
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Stanislav Shwartsman
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59c542fb06
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fix disasm of FISTTP opcodes
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2017-12-19 20:36:55 +00:00 |
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Stanislav Shwartsman
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15187110ef
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implement disasm of implicit memory reference for maskmovdqu/maskmovq opcodes. fix vmaskmovdqu disasm for legacy disasm as well
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2017-12-19 19:45:30 +00:00 |
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Stanislav Shwartsman
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e086f7ba19
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split INSERTPS opcode to reg and mem forms
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2017-12-19 19:25:40 +00:00 |
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Stanislav Shwartsman
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5dc5e01a12
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disasm fixes and reorg of pinsr* opcodes
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2017-12-16 18:34:20 +00:00 |
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Stanislav Shwartsman
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6a4e8ff2f1
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fixed typo in prev commit
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2017-12-13 21:08:10 +00:00 |
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Stanislav Shwartsman
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f362f34ed6
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correctly decode PINSRQ instruction
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2017-12-13 20:59:41 +00:00 |
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Stanislav Shwartsman
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50a799ea11
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split handlers for PINSRD/Q opcodes. fix disasm for MULX instruction
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2017-12-13 20:18:59 +00:00 |
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Stanislav Shwartsman
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8a311515dd
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correctly decode VPEXTRB/W/D/Q - these opcodes allowed to be with VEX.L=0 only
fixed disasm module compilation with no AVX enabled
remove duplicate opcode handlers
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2017-12-13 19:51:25 +00:00 |
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Stanislav Shwartsman
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2f3c9d3c8c
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correct disasm for movsxd opcode
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2017-12-13 18:44:13 +00:00 |
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Stanislav Shwartsman
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fd953421f4
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new disasm: add correct memaccess size for FLDCW
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2017-12-11 19:58:09 +00:00 |
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Stanislav Shwartsman
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a84d9cf1c7
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disasm: fix crc32 operand description
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2017-12-11 19:45:50 +00:00 |
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Stanislav Shwartsman
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8261a91ce9
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implemented GFNI instructions
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2017-10-21 19:57:12 +00:00 |
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Stanislav Shwartsman
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b7f62a291c
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fixed compressed displ form for more avx512 instructions
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2017-10-20 19:41:32 +00:00 |
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Stanislav Shwartsman
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da8d6e793f
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fixed compilation issues
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2017-10-20 19:24:10 +00:00 |
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Stanislav Shwartsman
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bca076889b
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decode all the vbmi2 opcodes, fix vpcompress/vpexpand instruction handler names (affects disasm)
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2017-10-20 18:50:10 +00:00 |
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Stanislav Shwartsman
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77a62a4dcd
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implemented (experimental, still untested) AVX512 VBMI2 extensions
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2017-10-20 18:38:15 +00:00 |
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Stanislav Shwartsman
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5439647254
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small change to extract ia_opcodes.h from instr.h to dedicated file. this would remove compilation dep of all files on ia_opcodes.h (now called ia_opcdes.def). regenerating dep ober all files in Makefiles.in
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2017-10-19 21:27:25 +00:00 |
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