Bochs

Author	SHA1	Message	Date
Stanislav Shwartsman	3012e7c361	Fixed representation and aligment of FPU/MMX register(s). Description/justification: Endian Host byte order Guest (x86) byte order ====================================================== Little FFFFFFFFEEAAAAAA FFFFFFFFEEAAAAAA Big AAAAAAEEFFFFFFFF FFFFFFFFEEAAAAAA F - fraction/mmx E - exponent A - aligment	2002-11-30 17:15:59 +00:00
Stanislav Shwartsman	57fd94744d	Implemented MOVQ2DQ/MOVDQ2Q instructions Small fixes with MMX environment	2002-11-30 14:42:41 +00:00
Stanislav Shwartsman	194952a53d	Merged BOCHS-SSE branch	2002-10-16 17:37:35 +00:00
Kevin Lawton	66452e9898	Replaced tabs in cpu/*.{cc,h} files with spaces.	2002-10-04 17:04:33 +00:00
Bryce Denney	ac4e5bb6cf	- add sanity checks - don't allow MMX on cpu level < 5. - require FPU support on cpu level >= 55 - don't allow MMX support without FPU support (moved this check from cpu/i387.h to config.h)	2002-09-22 16:11:12 +00:00
Stanislav Shwartsman	a08834b7f7	MMX cannot be compiled without FPU	2002-09-21 17:24:24 +00:00
Bryce Denney	be659a09b3	- check in Stanislav Shwartsman's patch "bochs-mmx.patch-endian-support". He writes: Detailed description: MMX instruction set support. Also supports BIG_ENDIAN systems. Tested on Solaris and HP1100. - modified files: configure.in cpu/Makefile.in cpu/cpu.h cpu/fetchdecode.cc cpu/proc_ctrl.cc fpu/fpu_system.h fpu/wmFPUemu_glue.cc - added files: cpu/i387.h cpu/mmx.cc	2002-09-09 16:11:25 +00:00