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47b05e55e1
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4002 Commits

Author SHA1 Message Date
Stanislav Shwartsman
47b05e55e1 revert lock handling change 
after checking agains Intel reference decoder (Xed) it shown few mismatches.
The mismatches are not functionally important - some very long instructions with lock prefix would cause #UD (due to badly placed lock prefix) insetad of #GP due to excessive opcode length
Seems like Xed evaluates entire instruction to the end and only then converts it to #UD due to lock prefix
 2024-10-30 06:18:46 +02:00
Stanislav Shwartsman
42e7c31e93 fixed typo 2024-10-29 07:31:27 +02:00
Stanislav Shwartsman
94df2e8694 change the way lock prefix is handled in Bochs decoder 
this solves issue with ALT_MOV_CR0 AMD's feature (where lock mov cr0 is treated as mov cr8)
and also speeds up decoding a bit
 2024-10-28 23:00:17 +02:00
Stanislav Shwartsman
ce839132ab rename all EVEX opcodes from BX_IA_V512_* to BX_IA_EVEX_* 
they are EVEX not necessary V512
 2024-10-28 20:28:53 +02:00
Stanislav Shwartsman
dc7de097b8 simplify code for AVX-512 masked merges 2024-10-26 23:49:04 +03:00
Stanislav Shwartsman
884d8983eb rename/simplify names of BF16 instruction handlers 2024-10-26 22:26:13 +03:00
Stanislav Shwartsman
8d1f2e1731 simplify prepare_ne_softfloat_status_helper function 2024-10-26 18:33:55 +03:00
Stanislav Shwartsman
2a9ff9e959 opcode naming style fix 2024-10-26 14:40:27 +03:00
Stanislav Shwartsman
056e1c52bf fixed disasm of VDPBF16PS instruction 2024-10-26 14:25:08 +03:00
Stanislav Shwartsman
a80bcba55d VDBPSADBW must be encoded with EVEX.W0 2024-10-26 14:11:00 +03:00
Stanislav Shwartsman
747f703bd8 fixed decoding of AVX-VNNI-INT8 instructions 
instructions VPDPBSSDS and VPDPBSUDS were swapped in decoder tables
 2024-10-26 10:16:11 +03:00
Stanislav Shwartsman
50c505224f unify handlers for VCOMISH and VUCOMISH instructions 2024-10-26 09:25:27 +03:00
Stanislav Shwartsman
b3bd4a7eca simplify AMD CPUDB definitions reusing generic function for leaf 0x80000001.ECX 
remove specialized function from bx_generic cpuid
add some basics cpuid sanity checks from bx_generic
next step: to remove entire bx_generic cpuid
 2024-10-24 21:39:57 +03:00
Stanislav Shwartsman
80019a34c0 Support for disabling of one of more CPU feature from CPUID configuration (see "exclude_features" in bochsrc sample and documentation) 2024-10-24 20:48:53 +03:00
Stanislav Shwartsman
556f64b8e7 extract EVEX opcodes definitions to separate file ia_opcodes_evex.def 2024-10-23 21:34:03 +03:00
Stanislav Shwartsman
c015c8168c fixed TPAUSE implementation and close issue #366 2024-10-23 15:02:54 +03:00
Stanislav Shwartsman
93a07982d5 rewritten LASS implementation to fix failures under ArrowLake model 
biggest issue was:
A supervisor-mode data access causes a LASS violation only if supervisor-mode access protection is enabled
(CR4.SMAP = 1) and RFLAGS.AC = 0 or the access implicitly accesses a system data structure
 2024-10-23 14:30:44 +03:00
Stanislav Shwartsman
a4c47d9559 added helper function to stringify EFLAGS as well and reuse it in Bochs debugger 2024-10-23 12:43:50 +03:00
Stanislav Shwartsman
2dfdd98ccf improve debug print after simulation finishes 
add detailed print for CR0, CR4, XCR0 and EFER extensions
 2024-10-23 12:15:02 +03:00
Stanislav Shwartsman
36b9cd93cf enable more bits in MSR IA32_SPEC_CTRL to support Win11 boot in Sapphire Rapids and Arrow Lake CPU models 2024-10-23 11:14:23 +03:00
Stanislav Shwartsman
d69acea2c0 fix name of the processor in the warning message 2024-10-23 10:48:24 +03:00
Stanislav Shwartsman
f90201b603 added ArrowLake CPU definition 
features: AVX-VNNI, AVX-IFMA, AVX-VNNI-INT8, AVX-VNNI-INT16, AVX_NE_CONVERT, GFNI, VAES/VPCLMULQDQ, SHA512, SM3/SM4, CMPCCXADD, LASS, SERIALIZE, UINTR
update CHANGES
 2024-10-23 10:20:23 +03:00
Stanislav Shwartsman
5c81b532a2 opcodes with EVEX.LLIG could come with any VL value and still will be allowed on AVX10.VL256 only machine 2024-10-22 23:27:00 +03:00
Stanislav Shwartsman
1f6436499d add AVX10.256 emulation VMX control 2024-10-22 22:15:41 +03:00
Stanislav Shwartsman
6717e8255d add XSAVE/XRSTOR support for AVX10.256 2024-10-22 21:43:57 +03:00
Stanislav Shwartsman
8469fcade1 make assignHandler member function for cleaner code 2024-10-22 21:09:16 +03:00
Stanislav Shwartsman
5bff389409 fix complation with minimalistic configuration which has no CPUID yet 2024-10-22 20:55:33 +03:00
Stanislav Shwartsman
60f8ab2a36 add preliminary AVX10.1 handling 
AVX10.1 includes the following AVX extensions:
	x86_feature(BX_ISA_AVX512, "avx512")                                    /* AVX-512 instruction */
	x86_feature(BX_ISA_AVX512_DQ, "avx512dq")                               /* AVX-512DQ instruction */
	x86_feature(BX_ISA_AVX512_BW, "avx512bw")                               /* AVX-512 Byte/Word instruction */
	x86_feature(BX_ISA_AVX512_CD, "avx512cd")                               /* AVX-512 Conflict Detection instruction */
	x86_feature(BX_ISA_AVX512_VBMI, "avx512vbmi")                           /* AVX-512 VBMI : Vector Bit Manipulation Instructions */
	x86_feature(BX_ISA_AVX512_VBMI2, "avx512vbmi2")                         /* AVX-512 VBMI2 : Vector Bit Manipulation Instructions */
	x86_feature(BX_ISA_AVX512_IFMA52, "avx512ifma52")                       /* AVX-512 IFMA52 Instructions */
	x86_feature(BX_ISA_AVX512_VPOPCNTDQ, "avx512vpopcnt")                   /* AVX-512 VPOPCNTD/VPOPCNTQ Instructions */
	x86_feature(BX_ISA_AVX512_VNNI, "avx512vnni")                           /* AVX-512 VNNI Instructions */
	x86_feature(BX_ISA_AVX512_BITALG, "avx512bitalg")                       /* AVX-512 BITALG Instructions */
	x86_feature(BX_ISA_AVX512_BF16, "avx512bf16")                           /* AVX-512 BF16 Instructions */
	x86_feature(BX_ISA_AVX512_FP16, "avx512fp16")                           /* AVX-512 FP16 Instructions */

And it could be handling 256-bit only, in this case avx10_1 will be enabled but avx10_vl512 will not.
Bochs will support all relevant instructions but without 512 bit mode in this case, attemp to encode VL512 in EVEX will result in #UD
also added support for AVX10 CPUID leaf 0x24

TODO: VMX support
 2024-10-22 20:44:46 +03:00
Stanislav Shwartsman
3db8404a03 correctly report CPUID leafs 0x19-0x1c as reserved on Sappire Rapids CPUID with AMX enabled 2024-10-22 12:51:14 +03:00
Stanislav Shwartsman
8c053ca361 added initial code for AMX_MOVRS instructions 2024-10-20 11:08:58 +03:00
Stanislav Shwartsman
3de88be5ac comment out avx512pf and avx512er ISA extensions which not supported by Bochs 2024-10-20 10:49:29 +03:00
Stanislav Shwartsman
4ceb60f12b better code formating 2024-10-19 20:17:07 +03:00
Stanislav Shwartsman
e8d5f983fb replace long_mul function in wide_int.cc with much faster code from softfloat3e 2024-10-19 18:26:07 +03:00
Stanislav Shwartsman
987e205fb0 implement AMX_TF32 extension 2024-10-19 10:15:38 +03:00
Stanislav Shwartsman
de7862a3f9 updates to CPUID definitions published in Intel ISA extensions rev54 doc 2024-10-18 17:37:54 +03:00
Stanislav Shwartsman
67a9bffb42 updates for CPUID definitions 2024-10-12 18:07:28 +03:00
Stanislav Shwartsman
b5665c39da CMPCCXADD instructions can be executed only in 64-bit mode 
configure and compile them only for 64-bit mode as well
 2024-10-12 17:22:14 +03:00
Stanislav Shwartsman
5d2d4220b7 fixed err message format string 2024-09-01 22:33:11 +03:00
Stanislav Shwartsman
de278480fa XSAVEC/XSAVES: Fixed corruption of MXCSR/x87 state by SSE state save in XSAVEC/XSAVES instructions (bug introduced in release 2.8) 
added explicit BX_ERROR message into bochs log when MXCSR restore error occur
 2024-09-01 21:34:01 +03:00
Stanislav Shwartsman
67b83db1d2 fixed implementation of SHA1RNDS4 instruction 2024-08-31 17:29:10 +03:00
Stanislav Shwartsman
a05f9c85d3 rename: 
float16_t -> float16
  float32_t -> float32
  float64_t -> float64
to fix compilation issues under Android as mentioned in issue #300

also fix bug f16_getExp method
 2024-08-22 08:55:56 +03:00
simoc
9264301293
Fixed spelling of word "destination" in log message (#324) 
Fixed spelling of word "destination" in log message.
 2024-05-31 14:54:13 +02:00
Stanislav Shwartsman
f199d64170 reduce further f128 computation precision to get closer to real x87 hw 
truncate on 80 bit now
 2024-05-01 07:28:05 +03:00
Stanislav Shwartsman
a3fd1fef26 fix for double overflow 2024-04-28 16:25:20 +03:00
Stanislav Shwartsman
2059854e04 rewrite floatx80 bias unmasked overflow handling 2024-04-28 10:16:39 +03:00
Stanislav Shwartsman
632d8780de rewrite code for biasing unmasked underflow for floatx80 in softfloat3e (from hack to clean code) 2024-04-28 06:41:47 +03:00
Stanislav Shwartsman
247aca0956 implement VMX SUPPORT FOR THE IA32_SPEC_CTRL MSR announced in 319433-052 
bugfix: "shadow stack prematurely busy" secondary vmexit control was wrongly mapped into bit2 insetad of bit3
 2024-04-27 09:44:48 +03:00
Stanislav Shwartsman
ab884f3dd4 fix compilation for AND Ryzen CPUID model 2024-04-26 22:15:34 +03:00
Stanislav Shwartsman
690bae9a12 add fields and bits for newly announced x86 features and vmx state 2024-04-26 22:13:08 +03:00
Stanislav Shwartsman
a565f9a754 implement Flexible UIRET (AKA UIRET_UIF) announced in 319433-052 2024-04-26 21:53:03 +03:00