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142 Commits

Author SHA1 Message Date
Volker Ruppert
ff93b11eb8 Removed SVN property "executable" from some files. 2021-02-21 09:25:33 +00:00
Stanislav Shwartsman
2ab50c7d66 solve code duplication between different cpudb models 2021-02-16 18:57:49 +00:00
Stanislav Shwartsman
1089e470e9 remove bochs-memory.h from bochs.h and include it only where required 2021-01-30 20:13:34 +00:00
Stanislav Shwartsman
7cc9cffeed remove siminterface.h from bochs.h and include it only where required 2021-01-30 19:40:18 +00:00
Stanislav Shwartsman
0b83259417 regen include dep lists for cpu and memory - need to regen for all others 2021-01-30 18:57:45 +00:00
Stanislav Shwartsman
f79d6df458 strip redundant info from tigerlake cpuid text file 2021-01-30 08:45:34 +00:00
Stanislav Shwartsman
1bf18b8aae ! CPUID: Added TigerLake CPU definition (features CET and CLWB support) 
- CPU code refactor, remove uses of bx_bool datatype and use C++ classic bool instead.
  This enable better compiler optimizations and reduce binary size
 2021-01-30 08:35:35 +00:00
Stanislav Shwartsman
e15012cfcf fix code duplication in <limiting max cpuid leaf to 0x02 for winnt> feature 2021-01-02 16:28:51 +00:00
Stanislav Shwartsman
b891789c3d implemented (experimental) TSC Adjust MSR 2020-05-21 19:58:16 +00:00
Stanislav Shwartsman
902ff1ef52 Part of the SF patch #548: Support Windows Hyper-V in Bochs by Xinyang 
When BX_SUPPORT_SMP is not defined, clear the bit in CPUID.[EAX=1].Bit[28] to indicate Hyper-Threading is unavailable.
 2020-01-11 06:18:13 +00:00
Stanislav Shwartsman
694112732b use default base CPUID class method to detemine values of 0x80000008 leaf for IceLake CPUID 2020-01-03 19:53:20 +00:00
Stanislav Shwartsman
8e2391c44b fixed compilation when compiling without EVEX 2019-12-26 20:12:40 +00:00
Stanislav Shwartsman
e593bb0084 CPUDB: Allow Icelake-U CPU model to exists without EVEX 2019-12-21 21:06:34 +00:00
Stanislav Shwartsman
134b23a809 enable AVX512_CD for Icelake configuration 2019-12-13 16:48:15 +00:00
Stanislav Shwartsman
d766cc8112 implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition 2019-10-26 20:09:30 +00:00
Stanislav Shwartsman
d6e08702e4 add Icelake-U model to CPUDB database. TODO: verify its VMX features 2019-09-24 20:26:14 +00:00
Stanislav Shwartsman
098791bf95 report MONITOR/MWAITX for Ryzen configuration in CPUID 2018-12-01 12:15:57 +00:00
Stanislav Shwartsman
e387876145 Enable PML VMX feature in Skylake-X 2018-10-26 19:54:22 +00:00
Stanislav Shwartsman
2e192372c0 fixes for CNL CPUID 2018-10-26 19:46:56 +00:00
Stanislav Shwartsman
a9aa1040c1 add Intel Cannonlake CPU model to CPUDB featuring AVF512FMA52 and SHA instructions 2018-10-26 09:23:58 +00:00
Stanislav Shwartsman
045a1cd637 XSAVEC/XSAVES should be supported in SKL-X CPUID 2017-11-11 12:04:26 +00:00
Stanislav Shwartsman
5439647254 small change to extract ia_opcodes.h from instr.h to dedicated file. this would remove compilation dep of all files on ia_opcodes.h (now called ia_opcdes.def). regenerating dep ober all files in Makefiles.in 2017-10-19 21:27:25 +00:00
Stanislav Shwartsman
7f4a9b4b08 skylake CPUID should compile also with no EVEX 2017-08-09 21:04:15 +00:00
Stanislav Shwartsman
7f01a7d9b6 remove obsolete comment 2017-08-09 20:37:43 +00:00
Stanislav Shwartsman
b2fdbd1274 added Skylake-X model to CPUDB -> with EVEX and AVX512 support 2017-08-09 20:36:17 +00:00
Stanislav Shwartsman
e5c64b3b56 cleanup of warning messages from cpuid code 2017-03-26 20:12:14 +00:00
Stanislav Shwartsman
2b79061127 Implemented MONITORX/MWAITX instructions (AMD), enabled in Ryzen CPU model 2017-03-26 19:14:15 +00:00
Volker Ruppert
dd2d03ec0a The 'del' command doesn't like forward slashes, so the MSVC nmake 'clean' 
target skipped files in subfolders. Updated cpu makefile dependencies.
 2017-03-26 15:55:57 +00:00
Stanislav Shwartsman
411ea954b4 implemented CLZERO instruction from AMD Ryzen CPU 2017-03-25 20:12:31 +00:00
Stanislav Shwartsman
6edf22e754 finally figured out what TCE means in AMD CPUID - and it has EFER.TCE bit related to it 2017-03-15 22:48:27 +00:00
Stanislav Shwartsman
ebbf8f9e0f adjustments in AMD Ryzen CPUID 2017-03-15 22:14:10 +00:00
Stanislav Shwartsman
3a033fa6db implemented xsaves/xrstors extensions (supported by Intel Skylake core and AMD Ryzen) 2017-03-15 21:44:15 +00:00
Volker Ruppert
8796abeea6 Some fixes in the build system. 
- Makefile: cleanup of the 'clean' target (adds missing 'bxhub').
- configure script: create cpudb subdirectories if necessary for building
  outside of the source tree.
- cpudb Makefile: clean object files from new location.
 2017-03-15 16:51:32 +00:00
Stanislav Shwartsman
c0701a6d42 fixup for Ryzen cpuid 2017-03-13 20:23:39 +00:00
Stanislav Shwartsman
402e2cfad0 move cpuid warning messages to base cpuid class - reduce code cleanup 2017-03-13 19:59:48 +00:00
Stanislav Shwartsman
07166f14b7 reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct) 2017-03-13 19:44:14 +00:00
Stanislav Shwartsman
980eaa7937 move cpuid leaf 80000008 to base bx_cpuid_t class to remove code dupolication 2017-03-09 21:25:18 +00:00
Volker Ruppert
cd68194269 Added Android host platform support to Bochs based on SF patch #534. 
- added Android case to the configure script.
- renamed file memory.h to memory-bochs.h to fix conflict with NDK.
- fixed Android issues in some files.
 2016-08-12 17:06:14 +00:00
Stanislav Shwartsman
7a34f00f99 extracted fetchdecode into separated folder under cpu and also out of BX_CPU_C class into stand-alone module. Next step: wrap it up nicely and define clear interace to CPU model to minimize dependencies. Ideally I need fetchdecode to not include CPU at all 2016-06-12 21:23:48 +00:00
Stanislav Shwartsman
793ceb0d8c fix massive code dupliction between disasm, debugger and cpu by introducing new cpu decoder.h header 2016-04-29 21:01:28 +00:00
Stanislav Shwartsman
be4b73c6d2 extracted tlb specific code to tlb.h; extracted xsave cpuid leaf function to base cpuid class 2015-09-21 13:16:17 +00:00
Stanislav Shwartsman
91086d0627 remove not relevant comments 2015-06-14 20:36:16 +00:00
Stanislav Shwartsman
a74e855185 added Broadwell ULT CPUID definition to CPUDB 2015-02-12 21:28:24 +00:00
Stanislav Shwartsman
901b7be1a8 code reorg 2015-02-12 20:18:35 +00:00
Stanislav Shwartsman
40312cec2d added pentium cpudb files 2015-02-11 21:44:24 +00:00
Stanislav Shwartsman
b60d7d3154 Cleanup of CPUDB modules, moved common functionality into bx_cpuid_t base class 
Added Pentium (P54C) AKA Pentium with no MMX to CPUDB
 2015-02-11 21:31:17 +00:00
Stanislav Shwartsman
5e6955c5e7 Major rewrite of memory access methods to avoid massive code duplication and enable inlining of memory access methods 2015-01-25 20:55:10 +00:00
Stanislav Shwartsman
f11b9a7f58 CPUID: "Yonah" and "Atom N-270" should report max virtual address as 32-bit in leaf 0x80000008 2014-10-22 19:53:23 +00:00
Stanislav Shwartsman
caab07e580 move common code (extended topology leaf) into base cpuid class to save code duplication 2014-10-15 14:25:08 +00:00
Stanislav Shwartsman
f8267ec3a7 rework in CPUID code (fixed code duplication). Re-enable perfmon reporting in CPUID because Win8/Win10 installation doesn't want to start without perfmon reported. TODO: implement basic perfmon support (at least only fixed counters) because win7-64 doesn't install with perfmon reported but not implemented 2014-10-15 08:04:38 +00:00