Volker Ruppert
ff93b11eb8
Removed SVN property "executable" from some files.
2021-02-21 09:25:33 +00:00
Stanislav Shwartsman
2ab50c7d66
solve code duplication between different cpudb models
2021-02-16 18:57:49 +00:00
Stanislav Shwartsman
7cc9cffeed
remove siminterface.h from bochs.h and include it only where required
2021-01-30 19:40:18 +00:00
Stanislav Shwartsman
f79d6df458
strip redundant info from tigerlake cpuid text file
2021-01-30 08:45:34 +00:00
Stanislav Shwartsman
1bf18b8aae
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
...
- CPU code refactor, remove uses of bx_bool datatype and use C++ classic bool instead.
This enable better compiler optimizations and reduce binary size
2021-01-30 08:35:35 +00:00
Stanislav Shwartsman
e15012cfcf
fix code duplication in <limiting max cpuid leaf to 0x02 for winnt> feature
2021-01-02 16:28:51 +00:00
Stanislav Shwartsman
b891789c3d
implemented (experimental) TSC Adjust MSR
2020-05-21 19:58:16 +00:00
Stanislav Shwartsman
902ff1ef52
Part of the SF patch #548 : Support Windows Hyper-V in Bochs by Xinyang
...
When BX_SUPPORT_SMP is not defined, clear the bit in CPUID.[EAX=1].Bit[28] to indicate Hyper-Threading is unavailable.
2020-01-11 06:18:13 +00:00
Stanislav Shwartsman
694112732b
use default base CPUID class method to detemine values of 0x80000008 leaf for IceLake CPUID
2020-01-03 19:53:20 +00:00
Stanislav Shwartsman
8e2391c44b
fixed compilation when compiling without EVEX
2019-12-26 20:12:40 +00:00
Stanislav Shwartsman
e593bb0084
CPUDB: Allow Icelake-U CPU model to exists without EVEX
2019-12-21 21:06:34 +00:00
Stanislav Shwartsman
134b23a809
enable AVX512_CD for Icelake configuration
2019-12-13 16:48:15 +00:00
Stanislav Shwartsman
d766cc8112
implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition
2019-10-26 20:09:30 +00:00
Stanislav Shwartsman
d6e08702e4
add Icelake-U model to CPUDB database. TODO: verify its VMX features
2019-09-24 20:26:14 +00:00
Stanislav Shwartsman
e387876145
Enable PML VMX feature in Skylake-X
2018-10-26 19:54:22 +00:00
Stanislav Shwartsman
2e192372c0
fixes for CNL CPUID
2018-10-26 19:46:56 +00:00
Stanislav Shwartsman
a9aa1040c1
add Intel Cannonlake CPU model to CPUDB featuring AVF512FMA52 and SHA instructions
2018-10-26 09:23:58 +00:00
Stanislav Shwartsman
045a1cd637
XSAVEC/XSAVES should be supported in SKL-X CPUID
2017-11-11 12:04:26 +00:00
Stanislav Shwartsman
7f4a9b4b08
skylake CPUID should compile also with no EVEX
2017-08-09 21:04:15 +00:00
Stanislav Shwartsman
7f01a7d9b6
remove obsolete comment
2017-08-09 20:37:43 +00:00
Stanislav Shwartsman
b2fdbd1274
added Skylake-X model to CPUDB -> with EVEX and AVX512 support
2017-08-09 20:36:17 +00:00
Stanislav Shwartsman
e5c64b3b56
cleanup of warning messages from cpuid code
2017-03-26 20:12:14 +00:00
Stanislav Shwartsman
402e2cfad0
move cpuid warning messages to base cpuid class - reduce code cleanup
2017-03-13 19:59:48 +00:00
Stanislav Shwartsman
07166f14b7
reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
2017-03-13 19:44:14 +00:00
