| .. |
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atom_n270.cc
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remove siminterface.h from bochs.h and include it only where required
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2021-01-30 19:40:18 +00:00 |
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atom_n270.h
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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atom_n270.txt
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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broadwell_ult.cc
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remove siminterface.h from bochs.h and include it only where required
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2021-01-30 19:40:18 +00:00 |
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broadwell_ult.h
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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broadwell_ult.txt
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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core2_penryn_t9600.cc
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remove siminterface.h from bochs.h and include it only where required
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2021-01-30 19:40:18 +00:00 |
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core2_penryn_t9600.h
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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core2_penryn_t9600.txt
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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core_duo_t2400_yonah.cc
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remove siminterface.h from bochs.h and include it only where required
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2021-01-30 19:40:18 +00:00 |
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core_duo_t2400_yonah.h
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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core_duo_t2400_yonah.txt
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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corei3_cnl.cc
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remove siminterface.h from bochs.h and include it only where required
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2021-01-30 19:40:18 +00:00 |
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corei3_cnl.h
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add Intel Cannonlake CPU model to CPUDB featuring AVF512FMA52 and SHA instructions
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2018-10-26 09:23:58 +00:00 |
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corei3_cnl.txt
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add Intel Cannonlake CPU model to CPUDB featuring AVF512FMA52 and SHA instructions
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2018-10-26 09:23:58 +00:00 |
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corei5_arrandale_m520.cc
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remove siminterface.h from bochs.h and include it only where required
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2021-01-30 19:40:18 +00:00 |
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corei5_arrandale_m520.h
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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corei5_arrandale_m520.txt
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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corei5_lynnfield_750.cc
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remove siminterface.h from bochs.h and include it only where required
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2021-01-30 19:40:18 +00:00 |
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corei5_lynnfield_750.h
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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corei5_lynnfield_750.txt
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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corei7_haswell_4770.cc
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remove siminterface.h from bochs.h and include it only where required
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2021-01-30 19:40:18 +00:00 |
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corei7_haswell_4770.h
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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corei7_haswell_4770.txt
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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corei7_icelake-u.cc
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remove siminterface.h from bochs.h and include it only where required
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2021-01-30 19:40:18 +00:00 |
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corei7_icelake-u.h
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use default base CPUID class method to detemine values of 0x80000008 leaf for IceLake CPUID
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2020-01-03 19:53:20 +00:00 |
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corei7_icelake-u.txt
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add Icelake-U model to CPUDB database. TODO: verify its VMX features
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2019-09-24 20:26:14 +00:00 |
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corei7_ivy_bridge_3770K.cc
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remove siminterface.h from bochs.h and include it only where required
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2021-01-30 19:40:18 +00:00 |
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corei7_ivy_bridge_3770K.h
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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corei7_ivy_bridge_3770K.txt
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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corei7_sandy_bridge_2600K.cc
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remove siminterface.h from bochs.h and include it only where required
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2021-01-30 19:40:18 +00:00 |
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corei7_sandy_bridge_2600K.h
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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corei7_sandy_bridge_2600K.txt
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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corei7_skylake-x.cc
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remove siminterface.h from bochs.h and include it only where required
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2021-01-30 19:40:18 +00:00 |
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corei7_skylake-x.h
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skylake CPUID should compile also with no EVEX
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2017-08-09 21:04:15 +00:00 |
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corei7_skylake-x.txt
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added Skylake-X model to CPUDB -> with EVEX and AVX512 support
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2017-08-09 20:36:17 +00:00 |
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p2_klamath.cc
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cleanup of warning messages from cpuid code
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2017-03-26 20:12:14 +00:00 |
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p2_klamath.h
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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p2_klamath.txt
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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p3_katmai.cc
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cleanup of warning messages from cpuid code
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2017-03-26 20:12:14 +00:00 |
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p3_katmai.h
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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p3_katmai.txt
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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p4_prescott_celeron_336.cc
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Part of the SF patch #548: Support Windows Hyper-V in Bochs by Xinyang
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2020-01-11 06:18:13 +00:00 |
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p4_prescott_celeron_336.h
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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p4_prescott_celeron_336.txt
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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p4_willamette.cc
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Part of the SF patch #548: Support Windows Hyper-V in Bochs by Xinyang
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2020-01-11 06:18:13 +00:00 |
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p4_willamette.h
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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p4_willamette.txt
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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pentium_mmx.cc
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cleanup of warning messages from cpuid code
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2017-03-26 20:12:14 +00:00 |
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pentium_mmx.h
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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pentium_mmx.txt
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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pentium.cc
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cleanup of warning messages from cpuid code
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2017-03-26 20:12:14 +00:00 |
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pentium.h
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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pentium.txt
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reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct)
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2017-03-13 19:44:14 +00:00 |
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tigerlake.cc
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remove siminterface.h from bochs.h and include it only where required
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2021-01-30 19:40:18 +00:00 |
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tigerlake.h
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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tigerlake.txt
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strip redundant info from tigerlake cpuid text file
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2021-01-30 08:45:34 +00:00 |
