mirror of https://github.com/bochs-emu/Bochs
Oops, had to fix a bunch of parentheses.
Why | has precedence under == (or is it =) I still don't understand.
This commit is contained in:
Gregory Alexander
parent
c1f363c7b5
commit
afdccad36c
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: access.cc,v 1.19 2002-09-06 14:58:55 yakovlev Exp $
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// $Id: access.cc,v 1.20 2002-09-06 16:29:49 yakovlev Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -280,7 +280,7 @@ accessOK:
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pageOffset = laddr & 0xfff;
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate) {
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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Bit32u accessBits;
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// See if the TLB entry privilege level allows us write access
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@ -333,7 +333,7 @@ accessOK:
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if (pageOffset <= 0xffe) { // Make sure access does not span 2 pages.
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate) {
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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Bit32u accessBits;
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// See if the TLB entry privilege level allows us write access
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@ -387,7 +387,7 @@ accessOK:
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if (pageOffset <= 0xffc) { // Make sure access does not span 2 pages.
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate) {
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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Bit32u accessBits;
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// See if the TLB entry privilege level allows us write access
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@ -440,7 +440,7 @@ accessOK:
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pageOffset = laddr & 0xfff;
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate) {
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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// See if the TLB entry privilege level allows us read access
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// from this CPL.
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Bit32u accessBits;
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@ -494,7 +494,7 @@ accessOK:
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Bit32u lpf, tlbIndex;
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate) {
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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// See if the TLB entry privilege level allows us read access
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// from this CPL.
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Bit32u accessBits;
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@ -549,7 +549,7 @@ accessOK:
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Bit32u lpf, tlbIndex;
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate) {
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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// See if the TLB entry privilege level allows us read access
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// from this CPL.
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Bit32u accessBits;
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@ -606,7 +606,7 @@ accessOK:
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pageOffset = laddr & 0xfff;
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate) {
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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Bit32u accessBits;
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// See if the TLB entry privilege level allows us write access
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@ -664,7 +664,7 @@ accessOK:
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if (pageOffset <= 0xffe) { // Make sure access does not span 2 pages.
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate) {
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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Bit32u accessBits;
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// See if the TLB entry privilege level allows us write access
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@ -720,7 +720,7 @@ accessOK:
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if (pageOffset <= 0xffc) { // Make sure access does not span 2 pages.
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate) {
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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Bit32u accessBits;
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// See if the TLB entry privilege level allows us write access
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@ -843,7 +843,7 @@ accessOK:
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if (pageOffset <= 0xff8) { // Make sure access does not span 2 pages.
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate) {
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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Bit32u accessBits;
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// See if the TLB entry privilege level allows us write access
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@ -898,7 +898,7 @@ accessOK:
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Bit32u lpf, tlbIndex;
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate) {
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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// See if the TLB entry privilege level allows us read access
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// from this CPL.
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Bit32u accessBits;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: paging.cc,v 1.16 2002-09-06 14:58:56 yakovlev Exp $
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// $Id: paging.cc,v 1.17 2002-09-06 16:29:49 yakovlev Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -533,7 +533,7 @@ BX_CPU_C::dtranslate_linear(Bit32u laddr, unsigned pl, unsigned rw)
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isWrite = (rw>=BX_WRITE); // write or r-m-w
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if (BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf == lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate) {
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if (BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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paddress = BX_CPU_THIS_PTR TLB.entry[TLB_index].ppf | poffset;
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accessBits = BX_CPU_THIS_PTR TLB.entry[TLB_index].accessBits;
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if (accessBits & (1 << ((isWrite<<1) | pl)) ) {
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@ -663,7 +663,7 @@ pageTableWalk:
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// Calculate physical memory address and fill in TLB cache entry
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paddress = ppf | poffset;
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BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate;
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BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate);
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BX_CPU_THIS_PTR TLB.entry[TLB_index].ppf = ppf;
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// 1 << ((W<<1) | U)
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@ -724,7 +724,7 @@ BX_CPU_C::itranslate_linear(Bit32u laddr, unsigned pl)
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TLB_index = BX_TLB_INDEX_OF(lpf);
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if (BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf == lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate) {
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if (BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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paddress = BX_CPU_THIS_PTR TLB.entry[TLB_index].ppf | poffset;
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accessBits = BX_CPU_THIS_PTR TLB.entry[TLB_index].accessBits;
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if (accessBits & (1 << pl) ) {
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@ -846,7 +846,7 @@ pageTableWalk:
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// Calculate physical memory address and fill in TLB cache entry
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paddress = ppf | poffset;
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BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate;
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BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate);
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BX_CPU_THIS_PTR TLB.entry[TLB_index].ppf = ppf;
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// 1 << ((W<<1) | U)
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@ -902,7 +902,7 @@ BX_CPU_C::dbg_xlate_linear2phy(Bit32u laddr, Bit32u *phy, Boolean *valid)
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TLB_index = BX_TLB_INDEX_OF(lpf);
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// see if page is in the TLB first
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if (BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf == lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate) {
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if (BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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paddress = BX_CPU_THIS_PTR TLB.entry[TLB_index].ppf | poffset;
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*phy = paddress;
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*valid = 1;
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@ -1085,13 +1085,13 @@ BX_CPU_C::access_linear(Bit32u laddr, unsigned length, unsigned pl,
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#if BX_SupportGuest2HostTLB
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate) {
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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BX_CPU_THIS_PTR mem->readPhysicalPage(this, laddr, length, data);
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return;
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}
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// We haven't seen this page, or it's been bumped before.
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BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf = lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate;
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BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf = (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate);
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BX_CPU_THIS_PTR TLB.entry[tlbIndex].ppf = lpf;
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// Request a direct write pointer so we can do either R or W.
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BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits = (Bit32u)
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@ -1123,13 +1123,13 @@ BX_CPU_C::access_linear(Bit32u laddr, unsigned length, unsigned pl,
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#if BX_SupportGuest2HostTLB
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate) {
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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BX_CPU_THIS_PTR mem->writePhysicalPage(this, laddr, length, data);
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return;
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}
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// We haven't seen this page, or it's been bumped before.
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BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf = lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate;
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BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf = (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate);
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BX_CPU_THIS_PTR TLB.entry[tlbIndex].ppf = lpf;
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// TLB.entry[tlbIndex].ppf field not used for PG==0.
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// Request a direct write pointer so we can do either R or W.
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: dbg_main.cc,v 1.52 2002-09-06 14:58:56 yakovlev Exp $
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// $Id: dbg_main.cc,v 1.53 2002-09-06 16:29:49 yakovlev Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -4527,7 +4527,7 @@ dbg_lin2phys(BX_CPU_C *cpu, Bit32u laddress, Bit32u *phy, Boolean *valid, Bit32u
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TLB_index = BX_TLB_INDEX_OF(lpf);
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// see if page is in the TLB first
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if (cpu->TLB.entry[TLB_index].lpf == lpf | cpu->TLB.tlb_invalidate) {
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if (cpu->TLB.entry[TLB_index].lpf == (lpf | cpu->TLB.tlb_invalidate)) {
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*tlb_phy = cpu->TLB.entry[TLB_index].ppf | poffset;
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*tlb_valid = 1;
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}
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