930 lines
29 KiB
C++
930 lines
29 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: access.cc,v 1.20 2002-09-06 16:29:49 yakovlev Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_USE_CPU_SMF
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#define this (BX_CPU(0))
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#endif
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void
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BX_CPU_C::write_virtual_checks(bx_segment_reg_t *seg, Bit32u offset,
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unsigned length)
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{
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Bit32u upper_limit;
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if ( protected_mode() ) {
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if ( seg->cache.valid==0 ) {
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BX_ERROR(("seg = %s", BX_CPU_THIS_PTR strseg(seg)));
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BX_ERROR(("seg->selector.value = %04x", (unsigned) seg->selector.value));
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BX_ERROR(("write_virtual_checks: valid bit = 0"));
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BX_ERROR(("CS: %04x", (unsigned) BX_CPU_THIS_PTR sregs[1].selector.value));
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BX_ERROR(("IP: %04x", (unsigned) BX_CPU_THIS_PTR prev_eip));
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exception(BX_GP_EXCEPTION, 0, 0);
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return;
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}
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if (seg->cache.p == 0) { /* not present */
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BX_INFO(("write_virtual_checks(): segment not present"));
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exception(int_number(seg), 0, 0);
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return;
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}
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switch ( seg->cache.type ) {
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case 0: case 1: // read only
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case 4: case 5: // read only, expand down
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case 8: case 9: // execute only
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case 10: case 11: // execute/read
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case 12: case 13: // execute only, conforming
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case 14: case 15: // execute/read-only, conforming
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BX_INFO(("write_virtual_checks(): no write access to seg"));
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exception(int_number(seg), 0, 0);
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return;
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case 2: case 3: /* read/write */
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if (offset > (seg->cache.u.segment.limit_scaled - length + 1)
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|| (length-1 > seg->cache.u.segment.limit_scaled)) {
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BX_INFO(("write_virtual_checks(): write beyond limit, r/w"));
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exception(int_number(seg), 0, 0);
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return;
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}
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if (seg->cache.u.segment.limit_scaled >= 7) {
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// Mark cache as being OK type for succeeding writes. The limit
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// checks still needs to be done though, but is more simple. We
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// could probably also optimize that out with a flag for the case
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// when limit is the maximum 32bit value. Limit should accomodate
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// at least a dword, since we subtract from it in the simple
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// limit check in other functions, and we don't want the value to roll.
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// Only normal segments (not expand down) are handled this way.
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seg->cache.valid |= SegAccessWOK;
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}
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break;
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case 6: case 7: /* read write, expand down */
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if (seg->cache.u.segment.d_b)
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upper_limit = 0xffffffff;
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else
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upper_limit = 0x0000ffff;
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if ( (offset <= seg->cache.u.segment.limit_scaled) ||
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(offset > upper_limit) ||
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((upper_limit - offset) < (length - 1)) ) {
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BX_INFO(("write_virtual_checks(): write beyond limit, r/w ED"));
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exception(int_number(seg), 0, 0);
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return;
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}
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break;
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}
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return;
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}
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else { /* real mode */
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if (offset > (seg->cache.u.segment.limit_scaled - length + 1)
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|| (length-1 > seg->cache.u.segment.limit_scaled)) {
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//BX_INFO(("write_virtual_checks() SEG EXCEPTION: %x:%x + %x",
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// (unsigned) seg->selector.value, (unsigned) offset, (unsigned) length));
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if (seg == & BX_CPU_THIS_PTR sregs[2]) exception(BX_SS_EXCEPTION, 0, 0);
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else exception(BX_GP_EXCEPTION, 0, 0);
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}
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if (seg->cache.u.segment.limit_scaled >= 7) {
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// Mark cache as being OK type for succeeding writes. See notes above.
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seg->cache.valid |= SegAccessWOK;
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}
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}
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}
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void
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BX_CPU_C::read_virtual_checks(bx_segment_reg_t *seg, Bit32u offset,
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unsigned length)
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{
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Bit32u upper_limit;
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if ( protected_mode() ) {
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if ( seg->cache.valid==0 ) {
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BX_ERROR(("seg = %s", BX_CPU_THIS_PTR strseg(seg)));
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BX_ERROR(("seg->selector.value = %04x", (unsigned) seg->selector.value));
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//BX_ERROR(("read_virtual_checks: valid bit = 0"));
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//BX_ERROR(("CS: %04x", (unsigned)
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// BX_CPU_THIS_PTR sregs[1].selector.value));
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//BX_ERROR(("IP: %04x", (unsigned) BX_CPU_THIS_PTR prev_eip));
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//debug(BX_CPU_THIS_PTR eip);
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exception(BX_GP_EXCEPTION, 0, 0);
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return;
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}
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if (seg->cache.p == 0) { /* not present */
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BX_INFO(("read_virtual_checks(): segment not present"));
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exception(int_number(seg), 0, 0);
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return;
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}
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switch ( seg->cache.type ) {
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case 0: case 1: /* read only */
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case 10: case 11: /* execute/read */
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case 14: case 15: /* execute/read-only, conforming */
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if (offset > (seg->cache.u.segment.limit_scaled - length + 1)
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|| (length-1 > seg->cache.u.segment.limit_scaled)) {
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BX_INFO(("read_virtual_checks(): write beyond limit"));
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exception(int_number(seg), 0, 0);
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return;
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}
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if (seg->cache.u.segment.limit_scaled >= 7) {
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// Mark cache as being OK type for succeeding writes. See notes for
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// write checks; similar code.
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seg->cache.valid |= SegAccessROK;
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}
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break;
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case 2: case 3: /* read/write */
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if (offset > (seg->cache.u.segment.limit_scaled - length + 1)
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|| (length-1 > seg->cache.u.segment.limit_scaled)) {
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BX_INFO(("read_virtual_checks(): write beyond limit"));
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exception(int_number(seg), 0, 0);
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return;
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}
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if (seg->cache.u.segment.limit_scaled >= 7) {
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// Mark cache as being OK type for succeeding writes. See notes for
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// write checks; similar code.
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seg->cache.valid |= SegAccessROK;
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}
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break;
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case 4: case 5: /* read only, expand down */
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if (seg->cache.u.segment.d_b)
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upper_limit = 0xffffffff;
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else
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upper_limit = 0x0000ffff;
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if ( (offset <= seg->cache.u.segment.limit_scaled) ||
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(offset > upper_limit) ||
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((upper_limit - offset) < (length - 1)) ) {
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BX_INFO(("read_virtual_checks(): write beyond limit"));
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exception(int_number(seg), 0, 0);
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return;
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}
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break;
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case 6: case 7: /* read write, expand down */
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if (seg->cache.u.segment.d_b)
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upper_limit = 0xffffffff;
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else
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upper_limit = 0x0000ffff;
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if ( (offset <= seg->cache.u.segment.limit_scaled) ||
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(offset > upper_limit) ||
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((upper_limit - offset) < (length - 1)) ) {
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BX_INFO(("read_virtual_checks(): write beyond limit"));
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exception(int_number(seg), 0, 0);
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return;
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}
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break;
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case 8: case 9: /* execute only */
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case 12: case 13: /* execute only, conforming */
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/* can't read or write an execute-only segment */
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BX_INFO(("read_virtual_checks(): execute only"));
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exception(int_number(seg), 0, 0);
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return;
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break;
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}
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return;
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}
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else { /* real mode */
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if (offset > (seg->cache.u.segment.limit_scaled - length + 1)
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|| (length-1 > seg->cache.u.segment.limit_scaled)) {
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//BX_ERROR(("read_virtual_checks() SEG EXCEPTION: %x:%x + %x",
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// (unsigned) seg->selector.value, (unsigned) offset, (unsigned) length));
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if (seg == & BX_CPU_THIS_PTR sregs[2]) exception(BX_SS_EXCEPTION, 0, 0);
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else exception(BX_GP_EXCEPTION, 0, 0);
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}
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if (seg->cache.u.segment.limit_scaled >= 7) {
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// Mark cache as being OK type for succeeding writes. See notes for
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// write checks; similar code.
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seg->cache.valid |= SegAccessROK;
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}
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return;
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}
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}
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char *
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BX_CPU_C::strseg(bx_segment_reg_t *seg)
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{
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if (seg == &BX_CPU_THIS_PTR sregs[0]) return("ES");
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else if (seg == & BX_CPU_THIS_PTR sregs[1]) return("CS");
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else if (seg == & BX_CPU_THIS_PTR sregs[2]) return("SS");
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else if (seg == &BX_CPU_THIS_PTR sregs[3]) return("DS");
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else if (seg == &BX_CPU_THIS_PTR sregs[4]) return("FS");
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else if (seg == &BX_CPU_THIS_PTR sregs[5]) return("GS");
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else {
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BX_ERROR(("undefined segment passed to strseg()!"));
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return("??");
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}
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}
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void
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BX_CPU_C::write_virtual_byte(unsigned s, Bit32u offset, Bit8u *data)
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{
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Bit32u laddr;
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bx_segment_reg_t *seg;
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seg = &BX_CPU_THIS_PTR sregs[s];
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if (seg->cache.valid & SegAccessWOK) {
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if (offset <= seg->cache.u.segment.limit_scaled) {
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unsigned pl;
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accessOK:
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laddr = seg->cache.u.segment.base + offset;
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BX_INSTR_MEM_DATA(laddr, 1, BX_WRITE);
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pl = (CPL==3);
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#if BX_SupportGuest2HostTLB
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{
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Bit32u lpf, tlbIndex, pageOffset;
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pageOffset = laddr & 0xfff;
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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Bit32u accessBits;
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// See if the TLB entry privilege level allows us write access
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// from this CPL.
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accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
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if ( accessBits & (1 << (2 | pl)) ) {
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// Current write access has privilege.
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Bit32u hostPageAddr;
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Bit8u *hostAddr;
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hostPageAddr = accessBits & 0xfffff000;
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if (hostPageAddr) {
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hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
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*hostAddr = *data;
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return;
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}
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}
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}
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}
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#endif // BX_SupportGuest2HostTLB
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// all checks OK
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access_linear(laddr, 1, pl, BX_WRITE, (void *) data);
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return;
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}
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}
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write_virtual_checks(seg, offset, 1);
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goto accessOK;
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}
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void
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BX_CPU_C::write_virtual_word(unsigned s, Bit32u offset, Bit16u *data)
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{
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Bit32u laddr;
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bx_segment_reg_t *seg;
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seg = &BX_CPU_THIS_PTR sregs[s];
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if (seg->cache.valid & SegAccessWOK) {
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if (offset < seg->cache.u.segment.limit_scaled) {
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unsigned pl;
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accessOK:
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laddr = seg->cache.u.segment.base + offset;
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BX_INSTR_MEM_DATA(laddr, 2, BX_WRITE);
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pl = (CPL==3);
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#if BX_SupportGuest2HostTLB
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{
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Bit32u lpf, tlbIndex, pageOffset;
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pageOffset = laddr & 0xfff;
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if (pageOffset <= 0xffe) { // Make sure access does not span 2 pages.
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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Bit32u accessBits;
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// See if the TLB entry privilege level allows us write access
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// from this CPL.
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accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
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if ( accessBits & (1 << (2 | pl)) ) {
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// Current write access has privilege.
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Bit32u hostPageAddr;
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Bit16u *hostAddr;
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hostPageAddr = accessBits & 0xfffff000;
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if (hostPageAddr) {
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hostAddr = (Bit16u*) (hostPageAddr | pageOffset);
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WriteHostWordToLittleEndian(hostAddr, *data);
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return;
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}
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}
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}
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}
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}
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#endif // BX_SupportGuest2HostTLB
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// all checks OK
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access_linear(laddr, 2, pl, BX_WRITE, (void *) data);
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return;
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}
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}
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write_virtual_checks(seg, offset, 2);
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goto accessOK;
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}
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void
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BX_CPU_C::write_virtual_dword(unsigned s, Bit32u offset, Bit32u *data)
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{
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Bit32u laddr;
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bx_segment_reg_t *seg;
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seg = &BX_CPU_THIS_PTR sregs[s];
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if (seg->cache.valid & SegAccessWOK) {
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if (offset < (seg->cache.u.segment.limit_scaled-2)) {
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unsigned pl;
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accessOK:
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laddr = seg->cache.u.segment.base + offset;
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BX_INSTR_MEM_DATA(laddr, 4, BX_WRITE);
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pl = (CPL==3);
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#if BX_SupportGuest2HostTLB
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{
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Bit32u lpf, tlbIndex, pageOffset;
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pageOffset = laddr & 0xfff;
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if (pageOffset <= 0xffc) { // Make sure access does not span 2 pages.
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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Bit32u accessBits;
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// See if the TLB entry privilege level allows us write access
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// from this CPL.
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accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
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if ( accessBits & (1 << (2 | pl)) ) {
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// Current write access has privilege.
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Bit32u hostPageAddr;
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Bit32u *hostAddr;
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hostPageAddr = accessBits & 0xfffff000;
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if (hostPageAddr) {
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hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
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WriteHostDWordToLittleEndian(hostAddr, *data);
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return;
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}
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}
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}
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}
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}
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#endif // BX_SupportGuest2HostTLB
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// all checks OK
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access_linear(laddr, 4, pl, BX_WRITE, (void *) data);
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return;
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}
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}
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write_virtual_checks(seg, offset, 4);
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goto accessOK;
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}
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void
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BX_CPU_C::read_virtual_byte(unsigned s, Bit32u offset, Bit8u *data)
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{
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Bit32u laddr;
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bx_segment_reg_t *seg;
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seg = &BX_CPU_THIS_PTR sregs[s];
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if (seg->cache.valid & SegAccessROK) {
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if (offset <= seg->cache.u.segment.limit_scaled) {
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unsigned pl;
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accessOK:
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laddr = seg->cache.u.segment.base + offset;
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BX_INSTR_MEM_DATA(laddr, 1, BX_READ);
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pl = (CPL==3);
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#if BX_SupportGuest2HostTLB
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{
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Bit32u lpf, tlbIndex, pageOffset;
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pageOffset = laddr & 0xfff;
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tlbIndex = BX_TLB_INDEX_OF(laddr);
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lpf = laddr & 0xfffff000;
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if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
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// See if the TLB entry privilege level allows us read access
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// from this CPL.
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Bit32u accessBits;
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accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
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if ( accessBits & (1<<pl) ) { // Read this pl OK.
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Bit32u hostPageAddr;
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Bit8u *hostAddr;
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hostPageAddr = accessBits & 0xfffff000;
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if (hostPageAddr) {
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hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
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*data = *hostAddr;
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return;
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}
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}
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}
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}
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#endif // BX_SupportGuest2HostTLB
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// all checks OK
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access_linear(laddr, 1, pl, BX_READ, (void *) data);
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return;
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}
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}
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read_virtual_checks(seg, offset, 1);
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goto accessOK;
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}
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void
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BX_CPU_C::read_virtual_word(unsigned s, Bit32u offset, Bit16u *data)
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{
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Bit32u laddr;
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bx_segment_reg_t *seg;
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seg = &BX_CPU_THIS_PTR sregs[s];
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if (seg->cache.valid & SegAccessROK) {
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if (offset < seg->cache.u.segment.limit_scaled) {
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unsigned pl;
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accessOK:
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laddr = seg->cache.u.segment.base + offset;
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BX_INSTR_MEM_DATA(laddr, 2, BX_READ);
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pl = (CPL==3);
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|
|
#if BX_SupportGuest2HostTLB
|
|
{
|
|
Bit32u pageOffset;
|
|
|
|
pageOffset = laddr & 0xfff;
|
|
if (pageOffset <= 0xffe) { // Make sure access does not span 2 pages.
|
|
Bit32u lpf, tlbIndex;
|
|
tlbIndex = BX_TLB_INDEX_OF(laddr);
|
|
lpf = laddr & 0xfffff000;
|
|
if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
|
|
// See if the TLB entry privilege level allows us read access
|
|
// from this CPL.
|
|
Bit32u accessBits;
|
|
|
|
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
|
|
if ( accessBits & (1<<pl) ) { // Read this pl OK.
|
|
Bit32u hostPageAddr;
|
|
Bit16u *hostAddr;
|
|
hostPageAddr = accessBits & 0xfffff000;
|
|
if (hostPageAddr) {
|
|
hostAddr = (Bit16u*) (hostPageAddr | pageOffset);
|
|
ReadHostWordFromLittleEndian(hostAddr, *data);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif // BX_SupportGuest2HostTLB
|
|
|
|
// all checks OK
|
|
access_linear(laddr, 2, pl, BX_READ, (void *) data);
|
|
return;
|
|
}
|
|
}
|
|
read_virtual_checks(seg, offset, 2);
|
|
goto accessOK;
|
|
}
|
|
|
|
|
|
void
|
|
BX_CPU_C::read_virtual_dword(unsigned s, Bit32u offset, Bit32u *data)
|
|
{
|
|
Bit32u laddr;
|
|
bx_segment_reg_t *seg;
|
|
|
|
seg = &BX_CPU_THIS_PTR sregs[s];
|
|
if (seg->cache.valid & SegAccessROK) {
|
|
if (offset < (seg->cache.u.segment.limit_scaled-2)) {
|
|
unsigned pl;
|
|
accessOK:
|
|
laddr = seg->cache.u.segment.base + offset;
|
|
BX_INSTR_MEM_DATA(laddr, 4, BX_READ);
|
|
pl = (CPL==3);
|
|
|
|
#if BX_SupportGuest2HostTLB
|
|
{
|
|
Bit32u pageOffset;
|
|
|
|
pageOffset = laddr & 0xfff;
|
|
if (pageOffset <= 0xffc) { // Make sure access does not span 2 pages.
|
|
Bit32u lpf, tlbIndex;
|
|
tlbIndex = BX_TLB_INDEX_OF(laddr);
|
|
lpf = laddr & 0xfffff000;
|
|
if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
|
|
// See if the TLB entry privilege level allows us read access
|
|
// from this CPL.
|
|
Bit32u accessBits;
|
|
|
|
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
|
|
if ( accessBits & (1<<pl) ) { // Read this pl OK.
|
|
Bit32u hostPageAddr;
|
|
Bit32u *hostAddr;
|
|
hostPageAddr = accessBits & 0xfffff000;
|
|
if (hostPageAddr) {
|
|
hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
|
|
ReadHostDWordFromLittleEndian(hostAddr, *data);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif // BX_SupportGuest2HostTLB
|
|
|
|
// all checks OK
|
|
access_linear(laddr, 4, pl, BX_READ, (void *) data);
|
|
return;
|
|
}
|
|
}
|
|
read_virtual_checks(seg, offset, 4);
|
|
goto accessOK;
|
|
}
|
|
|
|
//////////////////////////////////////////////////////////////
|
|
// special Read-Modify-Write operations //
|
|
// address translation info is kept across read/write calls //
|
|
//////////////////////////////////////////////////////////////
|
|
|
|
void
|
|
BX_CPU_C::read_RMW_virtual_byte(unsigned s, Bit32u offset, Bit8u *data)
|
|
{
|
|
Bit32u laddr;
|
|
bx_segment_reg_t *seg;
|
|
|
|
seg = &BX_CPU_THIS_PTR sregs[s];
|
|
if (seg->cache.valid & SegAccessWOK) {
|
|
if (offset <= seg->cache.u.segment.limit_scaled) {
|
|
unsigned pl;
|
|
accessOK:
|
|
laddr = seg->cache.u.segment.base + offset;
|
|
BX_INSTR_MEM_DATA(laddr, 1, BX_READ);
|
|
pl = (CPL==3);
|
|
|
|
#if BX_SupportGuest2HostTLB
|
|
{
|
|
Bit32u lpf, tlbIndex, pageOffset;
|
|
|
|
pageOffset = laddr & 0xfff;
|
|
tlbIndex = BX_TLB_INDEX_OF(laddr);
|
|
lpf = laddr & 0xfffff000;
|
|
if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
|
|
Bit32u accessBits;
|
|
|
|
// See if the TLB entry privilege level allows us write access
|
|
// from this CPL.
|
|
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
|
|
if ( accessBits & (1 << (2 | pl)) ) {
|
|
// Current write access has privilege.
|
|
Bit32u hostPageAddr;
|
|
Bit8u *hostAddr;
|
|
hostPageAddr = accessBits & 0xfffff000;
|
|
if (hostPageAddr) {
|
|
hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
|
|
*data = *hostAddr;
|
|
BX_CPU_THIS_PTR address_xlation.paddress1 =
|
|
BX_CPU_THIS_PTR TLB.entry[tlbIndex].ppf | pageOffset;
|
|
//BX_CPU_THIS_PTR address_xlation.pages = 1;
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif // BX_SupportGuest2HostTLB
|
|
|
|
// Accelerated attempt falls through to long path. Do it the
|
|
// old fashioned way...
|
|
access_linear(laddr, 1, pl, BX_RW, (void *) data);
|
|
return;
|
|
}
|
|
}
|
|
write_virtual_checks(seg, offset, 1);
|
|
goto accessOK;
|
|
}
|
|
|
|
|
|
void
|
|
BX_CPU_C::read_RMW_virtual_word(unsigned s, Bit32u offset, Bit16u *data)
|
|
{
|
|
Bit32u laddr;
|
|
bx_segment_reg_t *seg;
|
|
|
|
seg = &BX_CPU_THIS_PTR sregs[s];
|
|
if (seg->cache.valid & SegAccessWOK) {
|
|
if (offset < seg->cache.u.segment.limit_scaled) {
|
|
unsigned pl;
|
|
accessOK:
|
|
laddr = seg->cache.u.segment.base + offset;
|
|
BX_INSTR_MEM_DATA(laddr, 2, BX_READ);
|
|
pl = (CPL==3);
|
|
|
|
#if BX_SupportGuest2HostTLB
|
|
{
|
|
Bit32u lpf, tlbIndex, pageOffset;
|
|
|
|
pageOffset = laddr & 0xfff;
|
|
if (pageOffset <= 0xffe) { // Make sure access does not span 2 pages.
|
|
tlbIndex = BX_TLB_INDEX_OF(laddr);
|
|
lpf = laddr & 0xfffff000;
|
|
if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
|
|
Bit32u accessBits;
|
|
|
|
// See if the TLB entry privilege level allows us write access
|
|
// from this CPL.
|
|
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
|
|
if ( accessBits & (1 << (2 | pl)) ) {
|
|
// Current write access has privilege.
|
|
Bit32u hostPageAddr;
|
|
Bit16u *hostAddr;
|
|
hostPageAddr = accessBits & 0xfffff000;
|
|
if (hostPageAddr) {
|
|
hostAddr = (Bit16u*) (hostPageAddr | pageOffset);
|
|
ReadHostWordFromLittleEndian(hostAddr, *data);
|
|
BX_CPU_THIS_PTR address_xlation.paddress1 =
|
|
BX_CPU_THIS_PTR TLB.entry[tlbIndex].ppf | pageOffset;
|
|
BX_CPU_THIS_PTR address_xlation.pages = 1;
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif // BX_SupportGuest2HostTLB
|
|
|
|
access_linear(laddr, 2, pl, BX_RW, (void *) data);
|
|
return;
|
|
}
|
|
}
|
|
write_virtual_checks(seg, offset, 2);
|
|
goto accessOK;
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::read_RMW_virtual_dword(unsigned s, Bit32u offset, Bit32u *data)
|
|
{
|
|
Bit32u laddr;
|
|
bx_segment_reg_t *seg;
|
|
|
|
seg = &BX_CPU_THIS_PTR sregs[s];
|
|
if (seg->cache.valid & SegAccessWOK) {
|
|
if (offset < (seg->cache.u.segment.limit_scaled-2)) {
|
|
unsigned pl;
|
|
accessOK:
|
|
laddr = seg->cache.u.segment.base + offset;
|
|
BX_INSTR_MEM_DATA(laddr, 4, BX_READ);
|
|
pl = (CPL==3);
|
|
|
|
#if BX_SupportGuest2HostTLB
|
|
{
|
|
Bit32u lpf, tlbIndex, pageOffset;
|
|
|
|
pageOffset = laddr & 0xfff;
|
|
if (pageOffset <= 0xffc) { // Make sure access does not span 2 pages.
|
|
tlbIndex = BX_TLB_INDEX_OF(laddr);
|
|
lpf = laddr & 0xfffff000;
|
|
if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
|
|
Bit32u accessBits;
|
|
|
|
// See if the TLB entry privilege level allows us write access
|
|
// from this CPL.
|
|
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
|
|
if ( accessBits & (1 << (2 | pl)) ) {
|
|
// Current write access has privilege.
|
|
Bit32u hostPageAddr;
|
|
Bit32u *hostAddr;
|
|
hostPageAddr = accessBits & 0xfffff000;
|
|
if (hostPageAddr) {
|
|
hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
|
|
ReadHostDWordFromLittleEndian(hostAddr, *data);
|
|
BX_CPU_THIS_PTR address_xlation.paddress1 =
|
|
BX_CPU_THIS_PTR TLB.entry[tlbIndex].ppf | pageOffset;
|
|
BX_CPU_THIS_PTR address_xlation.pages = 1;
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif // BX_SupportGuest2HostTLB
|
|
|
|
access_linear(laddr, 4, pl, BX_RW, (void *) data);
|
|
return;
|
|
}
|
|
}
|
|
write_virtual_checks(seg, offset, 4);
|
|
goto accessOK;
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::write_RMW_virtual_byte(Bit8u val8)
|
|
{
|
|
BX_INSTR_MEM_DATA(BX_CPU_THIS_PTR address_xlation.paddress1, 1, BX_WRITE);
|
|
|
|
// address_xlation.pages must be 1
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(this,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 1, &val8);
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::write_RMW_virtual_word(Bit16u val16)
|
|
{
|
|
BX_INSTR_MEM_DATA(BX_CPU_THIS_PTR address_xlation.paddress1, 2, BX_WRITE);
|
|
|
|
if (BX_CPU_THIS_PTR address_xlation.pages == 1) {
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(this,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 2, &val16);
|
|
}
|
|
else {
|
|
#ifdef BX_LITTLE_ENDIAN
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(this,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 1, &val16);
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(this,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2, 1, ((Bit8u *) &val16) + 1);
|
|
#else
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(this,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 1, ((Bit8u *) &val16) + 1);
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(this,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2, 1, &val16);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::write_RMW_virtual_dword(Bit32u val32)
|
|
{
|
|
BX_INSTR_MEM_DATA(BX_CPU_THIS_PTR address_xlation.paddress1, 4, BX_WRITE);
|
|
|
|
if (BX_CPU_THIS_PTR address_xlation.pages == 1) {
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(this,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1, 4, &val32);
|
|
}
|
|
else {
|
|
#ifdef BX_LITTLE_ENDIAN
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(this,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1,
|
|
&val32);
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(this,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2,
|
|
((Bit8u *) &val32) + BX_CPU_THIS_PTR address_xlation.len1);
|
|
#else
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(this,
|
|
BX_CPU_THIS_PTR address_xlation.paddress1,
|
|
BX_CPU_THIS_PTR address_xlation.len1,
|
|
((Bit8u *) &val32) + (4 - BX_CPU_THIS_PTR address_xlation.len1));
|
|
BX_CPU_THIS_PTR mem->writePhysicalPage(this,
|
|
BX_CPU_THIS_PTR address_xlation.paddress2,
|
|
BX_CPU_THIS_PTR address_xlation.len2,
|
|
&val32);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
BX_CPU_C::write_virtual_qword(unsigned s, Bit32u offset, Bit64u *data)
|
|
{
|
|
Bit32u laddr;
|
|
bx_segment_reg_t *seg;
|
|
|
|
seg = &BX_CPU_THIS_PTR sregs[s];
|
|
if (seg->cache.valid & SegAccessWOK) {
|
|
if (offset <= (seg->cache.u.segment.limit_scaled-7)) {
|
|
unsigned pl;
|
|
accessOK:
|
|
laddr = seg->cache.u.segment.base + offset;
|
|
BX_INSTR_MEM_DATA(laddr, 8, BX_WRITE);
|
|
pl = (CPL==3);
|
|
|
|
#if BX_SupportGuest2HostTLB
|
|
{
|
|
Bit32u lpf, tlbIndex, pageOffset;
|
|
|
|
pageOffset = laddr & 0xfff;
|
|
if (pageOffset <= 0xff8) { // Make sure access does not span 2 pages.
|
|
tlbIndex = BX_TLB_INDEX_OF(laddr);
|
|
lpf = laddr & 0xfffff000;
|
|
if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
|
|
Bit32u accessBits;
|
|
|
|
// See if the TLB entry privilege level allows us write access
|
|
// from this CPL.
|
|
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
|
|
if ( accessBits & (1 << (2 | pl)) ) {
|
|
// Current write access has privilege.
|
|
Bit32u hostPageAddr;
|
|
Bit64u *hostAddr;
|
|
hostPageAddr = accessBits & 0xfffff000;
|
|
if (hostPageAddr) {
|
|
hostAddr = (Bit64u*) (hostPageAddr | pageOffset);
|
|
WriteHostQWordToLittleEndian(hostAddr, *data);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif // BX_SupportGuest2HostTLB
|
|
|
|
// all checks OK
|
|
access_linear(laddr, 8, pl, BX_WRITE, (void *) data);
|
|
return;
|
|
}
|
|
}
|
|
write_virtual_checks(seg, offset, 8);
|
|
goto accessOK;
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::read_virtual_qword(unsigned s, Bit32u offset, Bit64u *data)
|
|
{
|
|
Bit32u laddr;
|
|
bx_segment_reg_t *seg;
|
|
|
|
seg = &BX_CPU_THIS_PTR sregs[s];
|
|
if (seg->cache.valid & SegAccessROK) {
|
|
if (offset <= (seg->cache.u.segment.limit_scaled-7)) {
|
|
unsigned pl;
|
|
accessOK:
|
|
laddr = seg->cache.u.segment.base + offset;
|
|
BX_INSTR_MEM_DATA(laddr, 8, BX_READ);
|
|
pl = (CPL==3);
|
|
|
|
#if BX_SupportGuest2HostTLB
|
|
{
|
|
Bit32u pageOffset;
|
|
|
|
pageOffset = laddr & 0xfff;
|
|
if (pageOffset <= 0xff8) { // Make sure access does not span 2 pages.
|
|
Bit32u lpf, tlbIndex;
|
|
tlbIndex = BX_TLB_INDEX_OF(laddr);
|
|
lpf = laddr & 0xfffff000;
|
|
if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == (lpf | BX_CPU_THIS_PTR TLB.tlb_invalidate)) {
|
|
// See if the TLB entry privilege level allows us read access
|
|
// from this CPL.
|
|
Bit32u accessBits;
|
|
|
|
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
|
|
if ( accessBits & (1<<pl) ) { // Read this pl OK.
|
|
Bit32u hostPageAddr;
|
|
Bit64u *hostAddr;
|
|
hostPageAddr = accessBits & 0xfffff000;
|
|
if (hostPageAddr) {
|
|
hostAddr = (Bit64u*) (hostPageAddr | pageOffset);
|
|
ReadHostQWordFromLittleEndian(hostAddr, *data);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif // BX_SupportGuest2HostTLB
|
|
|
|
// all checks OK
|
|
access_linear(laddr, 8, pl, BX_READ, (void *) data);
|
|
return;
|
|
}
|
|
}
|
|
read_virtual_checks(seg, offset, 8);
|
|
goto accessOK;
|
|
}
|