Fixed representation and aligment of FPU/MMX register(s).
Description/justification: Endian Host byte order Guest (x86) byte order ====================================================== Little FFFFFFFFEEAAAAAA FFFFFFFFEEAAAAAA Big AAAAAAEEFFFFFFFF FFFFFFFFEEAAAAAA F - fraction/mmx E - exponent A - aligment
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@ -119,12 +119,28 @@ typedef union {
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#define MMXSQ(reg) (reg.s64)
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#define MMXSQ(reg) (reg.s64)
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#define MMXUQ(reg) (reg.u64)
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#define MMXUQ(reg) (reg.u64)
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// Endian Host byte order Guest (x86) byte order
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// ======================================================
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// Little FFFFFFFFEEAAAAAA FFFFFFFFEEAAAAAA
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// Big AAAAAAEEFFFFFFFF FFFFFFFFEEAAAAAA
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//
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// Legend: F - fraction/mmx
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// E - exponent
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// A - aligment
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typedef struct mmx_physical_reg_t
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typedef struct mmx_physical_reg_t
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{
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{
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#ifdef BX_BIG_ENDIAN
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Bit16u aligment1, aligment2, aligment3;
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Bit16u exp; /* 4 bytes: FP register exponent,
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set to 0xffff by all MMX commands */
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BxPackedMmxRegister packed_mmx_register;
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BxPackedMmxRegister packed_mmx_register;
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Bit16u exp; /* 4 bytes: exponent of FP register,
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#else
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set to 0xffff by all MMX commands */
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BxPackedMmxRegister packed_mmx_register;
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Bit32u aligment; /* 4 bytes: aligment */
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Bit16u exp; /* 4 bytes: FP register exponent,
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set to 0xffff by all MMX commands */
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Bit16u aligment1, aligment2, aligment3;
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#endif
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} BxMmxRegister;
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} BxMmxRegister;
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/* to be compatible with fpu register file */
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/* to be compatible with fpu register file */
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@ -1,6 +1,6 @@
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/*---------------------------------------------------------------------------+
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/*---------------------------------------------------------------------------+
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| fpu_emu.h |
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| fpu_emu.h |
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| $Id: fpu_emu.h,v 1.5 2001-10-06 03:53:46 bdenney Exp $
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| $Id: fpu_emu.h,v 1.6 2002-11-30 17:15:59 sshwarts Exp $
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| Copyright (C) 1992,1993,1994,1997 |
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| Copyright (C) 1992,1993,1994,1997 |
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| W. Metzenthen, 22 Parker St, Ormond, Vic 3163, |
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| W. Metzenthen, 22 Parker St, Ormond, Vic 3163, |
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@ -130,15 +130,26 @@ struct address {
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#endif
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#endif
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} GCC_ATTRIBUTE((packed));
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} GCC_ATTRIBUTE((packed));
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// Endian Host byte order Guest (x86) byte order
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// ======================================================
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// Little FFFFFFFFEEAAAAAA FFFFFFFFEEAAAAAA
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// Big AAAAAAEEFFFFFFFF FFFFFFFFEEAAAAAA
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//
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// Legend: F - fraction/mmx
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// E - exponent
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// A - aligment
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struct fpu__reg {
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struct fpu__reg {
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#ifdef EMU_BIG_ENDIAN
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#ifdef EMU_BIG_ENDIAN
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u16 aligment1, aligment2, aligment3;
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s16 exp; /* Signed quantity used in internal arithmetic. */
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u32 sigh;
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u32 sigh;
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u32 sigl;
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u32 sigl;
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s16 exp; /* Signed quantity used in internal arithmetic. */
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#else
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#else
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u32 sigl;
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u32 sigl;
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u32 sigh;
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u32 sigh;
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s16 exp; /* Signed quantity used in internal arithmetic. */
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s16 exp; /* Signed quantity used in internal arithmetic. */
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u16 aligment1, aligment2, aligment3;
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#endif
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#endif
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} GCC_ATTRIBUTE((aligned(16), packed));
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} GCC_ATTRIBUTE((aligned(16), packed));
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