Stanislav Shwartsman 3012e7c361 Fixed representation and aligment of FPU/MMX register(s). ... Description/justification: Endian Host byte order Guest (x86) byte order ====================================================== Little FFFFFFFFEEAAAAAA FFFFFFFFEEAAAAAA Big AAAAAAEEFFFFFFFF FFFFFFFFEEAAAAAA F - fraction/mmx E - exponent A - aligment		2002-11-30 17:15:59 +00:00
bochs	Fixed representation and aligment of FPU/MMX register(s).	2002-11-30 17:15:59 +00:00
bochs-performance	- add comments describing how blur-translate works	2002-04-17 22:51:58 +00:00
bochs-testing	- add results and conclusion	2002-11-19 15:56:26 +00:00
CVSROOT	- fixing { parameter	2002-03-21 07:15:06 +00:00
sfsite	Repairing index.html	2002-11-29 20:54:14 +00:00