From 3012e7c361eefba06945a397067b0423e00c1fd0 Mon Sep 17 00:00:00 2001
From: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
Date: Sat, 30 Nov 2002 17:15:59 +0000
Subject: [PATCH] Fixed representation and aligment of FPU/MMX register(s).
 Description/justification:

Endian  Host byte order         Guest (x86) byte order
======================================================
Little  FFFFFFFFEEAAAAAA        FFFFFFFFEEAAAAAA
Big     AAAAAAEEFFFFFFFF	FFFFFFFFEEAAAAAA

F - fraction/mmx
E - exponent
A - aligment
---
 bochs/cpu/i387.h    | 22 +++++++++++++++++++---
 bochs/fpu/fpu_emu.h | 15 +++++++++++++--
 2 files changed, 32 insertions(+), 5 deletions(-)

diff --git a/bochs/cpu/i387.h b/bochs/cpu/i387.h
index 31230804d..e0dbe6d0f 100644
--- a/bochs/cpu/i387.h
+++ b/bochs/cpu/i387.h
@@ -119,12 +119,28 @@ typedef union {
 #define MMXSQ(reg)  (reg.s64)
 #define MMXUQ(reg)  (reg.u64)
 
+// Endian  Host byte order         Guest (x86) byte order
+// ======================================================
+// Little  FFFFFFFFEEAAAAAA        FFFFFFFFEEAAAAAA
+// Big     AAAAAAEEFFFFFFFF        FFFFFFFFEEAAAAAA
+//
+// Legend: F - fraction/mmx
+//         E - exponent
+//         A - aligment
+
 typedef struct mmx_physical_reg_t
 {
+#ifdef BX_BIG_ENDIAN
+   Bit16u aligment1, aligment2, aligment3; 
+   Bit16u exp;      /* 4 bytes: FP register exponent, 
+                                   set to 0xffff by all MMX commands */
    BxPackedMmxRegister packed_mmx_register;
-   Bit16u exp;      /* 4 bytes: exponent of FP register, 
-                                    set to 0xffff by all MMX commands */
-   Bit32u aligment; /* 4 bytes: aligment */
+#else
+   BxPackedMmxRegister packed_mmx_register;
+   Bit16u exp;      /* 4 bytes: FP register exponent, 
+                                   set to 0xffff by all MMX commands */
+   Bit16u aligment1, aligment2, aligment3; 
+#endif
 } BxMmxRegister;
 
 /* to be compatible with fpu register file */
diff --git a/bochs/fpu/fpu_emu.h b/bochs/fpu/fpu_emu.h
index 97d6f7a4a..d27e636f4 100644
--- a/bochs/fpu/fpu_emu.h
+++ b/bochs/fpu/fpu_emu.h
@@ -1,6 +1,6 @@
 /*---------------------------------------------------------------------------+
  |  fpu_emu.h                                                                |
- |  $Id: fpu_emu.h,v 1.5 2001-10-06 03:53:46 bdenney Exp $
+ |  $Id: fpu_emu.h,v 1.6 2002-11-30 17:15:59 sshwarts Exp $
  |                                                                           |
  | Copyright (C) 1992,1993,1994,1997                                         |
  |                       W. Metzenthen, 22 Parker St, Ormond, Vic 3163,      |
@@ -130,15 +130,26 @@ struct address {
 #endif
 } GCC_ATTRIBUTE((packed));
 
+// Endian  Host byte order         Guest (x86) byte order
+// ======================================================
+// Little  FFFFFFFFEEAAAAAA        FFFFFFFFEEAAAAAA
+// Big     AAAAAAEEFFFFFFFF        FFFFFFFFEEAAAAAA
+//
+// Legend: F - fraction/mmx
+//         E - exponent
+//         A - aligment
+
 struct fpu__reg {
 #ifdef EMU_BIG_ENDIAN
+  u16 aligment1, aligment2, aligment3;
+  s16 exp;   /* Signed quantity used in internal arithmetic. */
   u32 sigh;
   u32 sigl;
-  s16 exp;   /* Signed quantity used in internal arithmetic. */
 #else
   u32 sigl;
   u32 sigh;
   s16 exp;   /* Signed quantity used in internal arithmetic. */
+  u16 aligment1, aligment2, aligment3;
 #endif
 } GCC_ATTRIBUTE((aligned(16), packed));