2004-06-18 18:11:11 +04:00
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/////////////////////////////////////////////////////////////////////////
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2011-02-25 01:05:47 +03:00
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// $Id$
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2005-03-21 00:19:38 +03:00
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/////////////////////////////////////////////////////////////////////////
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2004-06-18 18:11:11 +04:00
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//
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2017-05-06 00:09:27 +03:00
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// Copyright (c) 2003-2017 Stanislav Shwartsman
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2007-03-24 00:27:13 +03:00
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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2004-06-18 18:11:11 +04:00
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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2009-02-08 20:29:34 +03:00
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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2005-05-12 22:07:48 +04:00
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//
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2004-06-18 18:11:11 +04:00
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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2006-03-07 01:03:16 +03:00
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#include "cpu/cpu.h"
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2004-06-18 18:11:11 +04:00
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_FPU
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2017-10-20 00:27:25 +03:00
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#include "cpu/decoder/ia_opcodes.h"
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2015-05-02 23:08:36 +03:00
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extern float_status_t i387cw_to_softfloat_status_word(Bit16u control_word);
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2008-04-05 01:05:37 +04:00
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2004-06-18 18:11:11 +04:00
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#include "softfloatx80.h"
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static int status_word_flags_fpu_compare(int float_relation)
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{
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switch(float_relation) {
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case float_relation_unordered:
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return (FPU_SW_C0|FPU_SW_C2|FPU_SW_C3);
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case float_relation_greater:
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return (0);
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case float_relation_less:
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return (FPU_SW_C0);
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case float_relation_equal:
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return (FPU_SW_C3);
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}
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2009-03-11 00:43:11 +03:00
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return (-1); // should never get here
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2004-06-18 18:11:11 +04:00
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}
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void BX_CPU_C::write_eflags_fpu_compare(int float_relation)
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{
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switch(float_relation) {
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case float_relation_unordered:
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setEFlagsOSZAPC(EFlagsZFMask | EFlagsPFMask | EFlagsCFMask);
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break;
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case float_relation_greater:
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2014-10-22 22:24:33 +04:00
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clearEFlagsOSZAPC();
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2004-06-18 18:11:11 +04:00
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break;
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case float_relation_less:
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2014-10-22 22:24:33 +04:00
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clearEFlagsOSZAPC();
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assert_CF();
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2004-06-18 18:11:11 +04:00
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break;
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case float_relation_equal:
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2014-10-22 22:24:33 +04:00
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clearEFlagsOSZAPC();
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assert_ZF();
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2004-06-18 18:11:11 +04:00
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break;
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default:
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BX_PANIC(("write_eflags: unknown floating point compare relation"));
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}
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCOM_STi(bxInstruction_c *i)
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2004-06-18 18:11:11 +04:00
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{
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BX_CPU_THIS_PTR prepareFPU(i);
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2009-04-27 18:00:55 +04:00
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BX_CPU_THIS_PTR FPU_update_last_instruction(i);
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2004-06-18 18:11:11 +04:00
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2012-02-01 16:07:53 +04:00
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int pop_stack = 0;
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if (i->getIaOpcode() == BX_IA_FCOMP_STi)
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pop_stack = 1;
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2004-06-18 18:11:11 +04:00
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clear_C1();
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2012-08-05 17:52:40 +04:00
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if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src()))
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2004-06-18 18:11:11 +04:00
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{
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2017-05-05 23:56:13 +03:00
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FPU_exception(i, FPU_EX_Stack_Underflow);
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2009-04-13 02:07:59 +04:00
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setcc(FPU_SW_C0|FPU_SW_C2|FPU_SW_C3);
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2004-06-18 18:11:11 +04:00
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if(BX_CPU_THIS_PTR the_i387.is_IA_masked())
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{
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if (pop_stack)
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BX_CPU_THIS_PTR the_i387.FPU_pop();
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}
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2004-06-18 18:11:11 +04:00
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}
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2008-02-06 01:33:35 +03:00
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float_status_t status =
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2015-05-02 23:08:36 +03:00
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i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word());
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2004-06-18 18:11:11 +04:00
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2012-08-05 17:52:40 +04:00
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int rc = floatx80_compare(BX_READ_FPU_REG(0), BX_READ_FPU_REG(i->src()), status);
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2009-04-13 02:07:59 +04:00
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setcc(status_word_flags_fpu_compare(rc));
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2004-06-18 18:11:11 +04:00
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2017-05-05 23:56:13 +03:00
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if (! FPU_exception(i, status.float_exception_flags)) {
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2009-03-11 00:43:11 +03:00
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if (pop_stack)
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BX_CPU_THIS_PTR the_i387.FPU_pop();
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}
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2004-06-18 18:11:11 +04:00
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCOMI_ST0_STj(bxInstruction_c *i)
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2004-06-18 18:11:11 +04:00
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{
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BX_CPU_THIS_PTR prepareFPU(i);
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2009-04-27 18:00:55 +04:00
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BX_CPU_THIS_PTR FPU_update_last_instruction(i);
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2004-06-18 18:11:11 +04:00
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int pop_stack = i->b1() & 4;
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clear_C1();
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2012-08-05 17:52:40 +04:00
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if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src()))
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2004-06-18 18:11:11 +04:00
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{
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2017-05-05 23:56:13 +03:00
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FPU_exception(i, FPU_EX_Stack_Underflow);
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2009-04-13 02:07:59 +04:00
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setEFlagsOSZAPC(EFlagsZFMask | EFlagsPFMask | EFlagsCFMask);
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2004-06-18 18:11:11 +04:00
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if(BX_CPU_THIS_PTR the_i387.is_IA_masked())
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{
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if (pop_stack)
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BX_CPU_THIS_PTR the_i387.FPU_pop();
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}
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2004-06-18 18:11:11 +04:00
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}
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2008-02-06 01:33:35 +03:00
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float_status_t status =
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2015-05-02 23:08:36 +03:00
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i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word());
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2004-06-18 18:11:11 +04:00
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2012-08-05 17:52:40 +04:00
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int rc = floatx80_compare(BX_READ_FPU_REG(0), BX_READ_FPU_REG(i->src()), status);
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2009-04-13 02:07:59 +04:00
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BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
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2004-06-18 18:11:11 +04:00
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2017-05-05 23:56:13 +03:00
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if (! FPU_exception(i, status.float_exception_flags)) {
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2009-03-11 00:43:11 +03:00
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if (pop_stack)
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BX_CPU_THIS_PTR the_i387.FPU_pop();
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}
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2004-06-18 18:11:11 +04:00
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FUCOMI_ST0_STj(bxInstruction_c *i)
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2004-06-18 18:11:11 +04:00
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{
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BX_CPU_THIS_PTR prepareFPU(i);
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2009-04-27 18:00:55 +04:00
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BX_CPU_THIS_PTR FPU_update_last_instruction(i);
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2004-06-18 18:11:11 +04:00
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int pop_stack = i->b1() & 4;
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clear_C1();
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2012-08-05 17:52:40 +04:00
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if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src()))
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2004-06-18 18:11:11 +04:00
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{
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2017-05-05 23:56:13 +03:00
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FPU_exception(i, FPU_EX_Stack_Underflow);
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2009-04-13 02:07:59 +04:00
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setEFlagsOSZAPC(EFlagsZFMask | EFlagsPFMask | EFlagsCFMask);
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2004-06-18 18:11:11 +04:00
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if(BX_CPU_THIS_PTR the_i387.is_IA_masked())
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{
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if (pop_stack)
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BX_CPU_THIS_PTR the_i387.FPU_pop();
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}
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2004-06-18 18:11:11 +04:00
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}
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2008-02-06 01:33:35 +03:00
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float_status_t status =
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2015-05-02 23:08:36 +03:00
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i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word());
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2004-06-18 18:11:11 +04:00
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2012-08-05 17:52:40 +04:00
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int rc = floatx80_compare_quiet(BX_READ_FPU_REG(0), BX_READ_FPU_REG(i->src()), status);
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2009-04-13 02:07:59 +04:00
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BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
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2004-06-18 18:11:11 +04:00
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2017-05-05 23:56:13 +03:00
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if (! FPU_exception(i, status.float_exception_flags)) {
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2009-03-11 00:43:11 +03:00
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if (pop_stack)
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BX_CPU_THIS_PTR the_i387.FPU_pop();
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}
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2004-06-18 18:11:11 +04:00
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FUCOM_STi(bxInstruction_c *i)
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2004-06-18 18:11:11 +04:00
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{
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BX_CPU_THIS_PTR prepareFPU(i);
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2009-04-27 18:00:55 +04:00
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BX_CPU_THIS_PTR FPU_update_last_instruction(i);
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2004-06-18 18:11:11 +04:00
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2012-02-01 16:07:53 +04:00
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int pop_stack = 0;
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if (i->getIaOpcode() == BX_IA_FUCOMP_STi)
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pop_stack = 1;
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2004-06-18 18:11:11 +04:00
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2012-08-05 17:52:40 +04:00
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if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src()))
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2004-06-18 18:11:11 +04:00
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{
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2017-05-05 23:56:13 +03:00
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FPU_exception(i, FPU_EX_Stack_Underflow);
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2009-04-13 02:07:59 +04:00
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setcc(FPU_SW_C0|FPU_SW_C2|FPU_SW_C3);
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2004-06-18 18:11:11 +04:00
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if(BX_CPU_THIS_PTR the_i387.is_IA_masked())
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{
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if (pop_stack)
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BX_CPU_THIS_PTR the_i387.FPU_pop();
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}
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2004-06-18 18:11:11 +04:00
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}
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2008-02-06 01:33:35 +03:00
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float_status_t status =
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2015-05-02 23:08:36 +03:00
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i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word());
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2004-06-18 18:11:11 +04:00
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2012-08-05 17:52:40 +04:00
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int rc = floatx80_compare_quiet(BX_READ_FPU_REG(0), BX_READ_FPU_REG(i->src()), status);
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2009-04-13 02:07:59 +04:00
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setcc(status_word_flags_fpu_compare(rc));
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2004-06-18 18:11:11 +04:00
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2017-05-05 23:56:13 +03:00
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if (! FPU_exception(i, status.float_exception_flags)) {
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2009-03-11 00:43:11 +03:00
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if (pop_stack)
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BX_CPU_THIS_PTR the_i387.FPU_pop();
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}
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2004-06-18 18:11:11 +04:00
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCOM_SINGLE_REAL(bxInstruction_c *i)
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2004-06-18 18:11:11 +04:00
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{
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BX_CPU_THIS_PTR prepareFPU(i);
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2012-02-01 16:07:53 +04:00
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int rc, pop_stack = 0;
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if (i->getIaOpcode() == BX_IA_FCOMP_SINGLE_REAL)
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pop_stack = 1;
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2004-06-18 18:11:11 +04:00
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2015-05-17 00:06:59 +03:00
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RMAddr(i) = BX_CPU_RESOLVE_ADDR(i);
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2008-04-26 23:38:53 +04:00
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float32 load_reg = read_virtual_dword(i->seg(), RMAddr(i));
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2009-04-27 18:00:55 +04:00
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BX_CPU_THIS_PTR FPU_update_last_instruction(i);
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2004-06-18 18:11:11 +04:00
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clear_C1();
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if (IS_TAG_EMPTY(0))
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{
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2017-05-05 23:56:13 +03:00
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FPU_exception(i, FPU_EX_Stack_Underflow);
|
2009-04-13 02:07:59 +04:00
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setcc(FPU_SW_C0|FPU_SW_C2|FPU_SW_C3);
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2004-06-18 18:11:11 +04:00
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if(BX_CPU_THIS_PTR the_i387.is_IA_masked())
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{
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if (pop_stack)
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BX_CPU_THIS_PTR the_i387.FPU_pop();
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}
|
2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2004-06-18 18:11:11 +04:00
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}
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|
2008-02-06 01:33:35 +03:00
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float_status_t status =
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2015-05-02 23:08:36 +03:00
|
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i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word());
|
2004-06-18 18:11:11 +04:00
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2009-05-21 16:20:06 +04:00
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floatx80 a = BX_READ_FPU_REG(0);
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|
2009-05-28 20:31:08 +04:00
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if (floatx80_is_nan(a) || floatx80_is_unsupported(a) || float32_is_nan(load_reg)) {
|
2009-05-21 16:20:06 +04:00
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rc = float_relation_unordered;
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float_raise(status, float_flag_invalid);
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|
}
|
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else {
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|
|
rc = floatx80_compare(a, float32_to_floatx80(load_reg, status), status);
|
|
|
|
}
|
2009-04-13 02:07:59 +04:00
|
|
|
setcc(status_word_flags_fpu_compare(rc));
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2017-05-05 23:56:13 +03:00
|
|
|
if (! FPU_exception(i, status.float_exception_flags)) {
|
2009-03-11 00:43:11 +03:00
|
|
|
if (pop_stack)
|
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCOM_DOUBLE_REAL(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
|
|
|
|
2012-02-01 16:07:53 +04:00
|
|
|
int rc, pop_stack = 0;
|
|
|
|
if (i->getIaOpcode() == BX_IA_FCOMP_DOUBLE_REAL)
|
|
|
|
pop_stack = 1;
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2015-05-17 00:06:59 +03:00
|
|
|
RMAddr(i) = BX_CPU_RESOLVE_ADDR(i);
|
2008-04-26 23:38:53 +04:00
|
|
|
float64 load_reg = read_virtual_qword(i->seg(), RMAddr(i));
|
|
|
|
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
|
|
|
|
2004-06-18 18:11:11 +04:00
|
|
|
clear_C1();
|
|
|
|
|
|
|
|
if (IS_TAG_EMPTY(0))
|
|
|
|
{
|
2017-05-05 23:56:13 +03:00
|
|
|
FPU_exception(i, FPU_EX_Stack_Underflow);
|
2009-04-13 02:07:59 +04:00
|
|
|
setcc(FPU_SW_C0|FPU_SW_C2|FPU_SW_C3);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
if(BX_CPU_THIS_PTR the_i387.is_IA_masked())
|
|
|
|
{
|
|
|
|
if (pop_stack)
|
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word());
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2009-05-21 16:20:06 +04:00
|
|
|
floatx80 a = BX_READ_FPU_REG(0);
|
|
|
|
|
2009-05-28 20:31:08 +04:00
|
|
|
if (floatx80_is_nan(a) || floatx80_is_unsupported(a) || float64_is_nan(load_reg)) {
|
2009-05-21 16:20:06 +04:00
|
|
|
rc = float_relation_unordered;
|
|
|
|
float_raise(status, float_flag_invalid);
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
rc = floatx80_compare(a, float64_to_floatx80(load_reg, status), status);
|
|
|
|
}
|
2009-04-13 02:07:59 +04:00
|
|
|
setcc(status_word_flags_fpu_compare(rc));
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2017-05-05 23:56:13 +03:00
|
|
|
if (! FPU_exception(i, status.float_exception_flags)) {
|
2009-03-11 00:43:11 +03:00
|
|
|
if (pop_stack)
|
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FICOM_WORD_INTEGER(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
|
|
|
|
2012-02-01 16:07:53 +04:00
|
|
|
int pop_stack = 0;
|
|
|
|
if (i->getIaOpcode() == BX_IA_FICOMP_WORD_INTEGER)
|
|
|
|
pop_stack = 1;
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2015-05-17 00:06:59 +03:00
|
|
|
RMAddr(i) = BX_CPU_RESOLVE_ADDR(i);
|
2008-04-26 23:38:53 +04:00
|
|
|
Bit16s load_reg = (Bit16s) read_virtual_word(i->seg(), RMAddr(i));
|
|
|
|
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
|
|
|
|
2004-06-18 18:11:11 +04:00
|
|
|
clear_C1();
|
|
|
|
|
|
|
|
if (IS_TAG_EMPTY(0))
|
|
|
|
{
|
2017-05-05 23:56:13 +03:00
|
|
|
FPU_exception(i, FPU_EX_Stack_Underflow);
|
2009-04-13 02:07:59 +04:00
|
|
|
setcc(FPU_SW_C0|FPU_SW_C2|FPU_SW_C3);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
if(BX_CPU_THIS_PTR the_i387.is_IA_masked())
|
|
|
|
{
|
|
|
|
if (pop_stack)
|
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word());
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
int rc = floatx80_compare(BX_READ_FPU_REG(0),
|
2009-04-13 02:07:59 +04:00
|
|
|
int32_to_floatx80((Bit32s)(load_reg)), status);
|
|
|
|
setcc(status_word_flags_fpu_compare(rc));
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2017-05-05 23:56:13 +03:00
|
|
|
if (! FPU_exception(i, status.float_exception_flags)) {
|
2009-03-11 00:43:11 +03:00
|
|
|
if (pop_stack)
|
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FICOM_DWORD_INTEGER(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
|
|
|
|
2012-02-01 16:07:53 +04:00
|
|
|
int pop_stack = 0;
|
|
|
|
if (i->getIaOpcode() == BX_IA_FICOMP_DWORD_INTEGER)
|
|
|
|
pop_stack = 1;
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2015-05-17 00:06:59 +03:00
|
|
|
RMAddr(i) = BX_CPU_RESOLVE_ADDR(i);
|
2008-04-26 23:38:53 +04:00
|
|
|
Bit32s load_reg = (Bit32s) read_virtual_dword(i->seg(), RMAddr(i));
|
|
|
|
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
|
|
|
|
2004-06-18 18:11:11 +04:00
|
|
|
clear_C1();
|
|
|
|
|
|
|
|
if (IS_TAG_EMPTY(0))
|
|
|
|
{
|
2017-05-05 23:56:13 +03:00
|
|
|
FPU_exception(i, FPU_EX_Stack_Underflow);
|
2009-04-13 02:07:59 +04:00
|
|
|
setcc(FPU_SW_C0|FPU_SW_C2|FPU_SW_C3);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
if(BX_CPU_THIS_PTR the_i387.is_IA_masked())
|
|
|
|
{
|
|
|
|
if (pop_stack)
|
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word());
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2009-03-11 00:43:11 +03:00
|
|
|
int rc = floatx80_compare(BX_READ_FPU_REG(0), int32_to_floatx80(load_reg), status);
|
2009-04-13 02:07:59 +04:00
|
|
|
setcc(status_word_flags_fpu_compare(rc));
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2017-05-05 23:56:13 +03:00
|
|
|
if (! FPU_exception(i, status.float_exception_flags)) {
|
2009-03-11 00:43:11 +03:00
|
|
|
if (pop_stack)
|
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* DE D9 */
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCOMPP(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
clear_C1();
|
|
|
|
|
|
|
|
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(1))
|
|
|
|
{
|
2017-05-05 23:56:13 +03:00
|
|
|
FPU_exception(i, FPU_EX_Stack_Underflow);
|
2009-04-13 02:07:59 +04:00
|
|
|
setcc(FPU_SW_C0|FPU_SW_C2|FPU_SW_C3);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
if(BX_CPU_THIS_PTR the_i387.is_IA_masked())
|
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word());
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
int rc = floatx80_compare(BX_READ_FPU_REG(0), BX_READ_FPU_REG(1), status);
|
2009-04-13 02:07:59 +04:00
|
|
|
setcc(status_word_flags_fpu_compare(rc));
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2017-05-05 23:56:13 +03:00
|
|
|
if (! FPU_exception(i, status.float_exception_flags)) {
|
2009-03-11 00:43:11 +03:00
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* DA E9 */
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FUCOMPP(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(1))
|
|
|
|
{
|
2017-05-05 23:56:13 +03:00
|
|
|
FPU_exception(i, FPU_EX_Stack_Underflow);
|
2009-04-13 02:07:59 +04:00
|
|
|
setcc(FPU_SW_C0|FPU_SW_C2|FPU_SW_C3);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
if(BX_CPU_THIS_PTR the_i387.is_IA_masked())
|
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word());
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
int rc = floatx80_compare_quiet(BX_READ_FPU_REG(0), BX_READ_FPU_REG(1), status);
|
2009-04-13 02:07:59 +04:00
|
|
|
setcc(status_word_flags_fpu_compare(rc));
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2017-05-05 23:56:13 +03:00
|
|
|
if (! FPU_exception(i, status.float_exception_flags)) {
|
2009-03-11 00:43:11 +03:00
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* D9 E4 */
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FTST(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
clear_C1();
|
|
|
|
|
2009-04-13 02:07:59 +04:00
|
|
|
if (IS_TAG_EMPTY(0)) {
|
2017-05-05 23:56:13 +03:00
|
|
|
FPU_exception(i, FPU_EX_Stack_Underflow);
|
2009-04-13 02:07:59 +04:00
|
|
|
setcc(FPU_SW_C0|FPU_SW_C2|FPU_SW_C3);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
2009-04-13 02:07:59 +04:00
|
|
|
else {
|
|
|
|
extern const floatx80 Const_Z;
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2009-04-13 02:07:59 +04:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word());
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2009-04-13 02:07:59 +04:00
|
|
|
int rc = floatx80_compare(BX_READ_FPU_REG(0), Const_Z, status);
|
2009-03-11 00:43:11 +03:00
|
|
|
setcc(status_word_flags_fpu_compare(rc));
|
2017-05-05 23:56:13 +03:00
|
|
|
FPU_exception(i, status.float_exception_flags);
|
2009-04-13 02:07:59 +04:00
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* D9 E5 */
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FXAM(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
floatx80 reg = BX_READ_FPU_REG(0);
|
|
|
|
int sign = floatx80_sign(reg);
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
/*
|
|
|
|
* Examine the contents of the ST(0) register and sets the condition
|
|
|
|
* code flags C0, C2 and C3 in the FPU status word to indicate the
|
2004-06-18 18:11:11 +04:00
|
|
|
* class of value or number in the register.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (IS_TAG_EMPTY(0))
|
|
|
|
{
|
|
|
|
setcc(FPU_SW_C3|FPU_SW_C1|FPU_SW_C0);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
float_class_t aClass = floatx80_class(reg);
|
|
|
|
|
|
|
|
switch(aClass)
|
|
|
|
{
|
|
|
|
case float_zero:
|
|
|
|
setcc(FPU_SW_C3|FPU_SW_C1);
|
|
|
|
break;
|
2008-02-06 01:33:35 +03:00
|
|
|
|
2014-03-10 01:42:11 +04:00
|
|
|
case float_SNaN:
|
|
|
|
case float_QNaN:
|
2004-06-18 18:11:11 +04:00
|
|
|
// unsupported handled as NaNs
|
|
|
|
if (floatx80_is_unsupported(reg)) {
|
2008-02-06 01:33:35 +03:00
|
|
|
setcc(FPU_SW_C1);
|
2004-06-18 18:11:11 +04:00
|
|
|
} else {
|
|
|
|
setcc(FPU_SW_C1|FPU_SW_C0);
|
|
|
|
}
|
|
|
|
break;
|
2008-02-06 01:33:35 +03:00
|
|
|
|
2004-06-18 18:11:11 +04:00
|
|
|
case float_negative_inf:
|
|
|
|
case float_positive_inf:
|
|
|
|
setcc(FPU_SW_C2|FPU_SW_C1|FPU_SW_C0);
|
|
|
|
break;
|
2008-02-06 01:33:35 +03:00
|
|
|
|
2004-06-18 18:11:11 +04:00
|
|
|
case float_denormal:
|
|
|
|
setcc(FPU_SW_C3|FPU_SW_C2|FPU_SW_C1);
|
|
|
|
break;
|
2008-02-06 01:33:35 +03:00
|
|
|
|
2004-06-18 18:11:11 +04:00
|
|
|
case float_normalized:
|
|
|
|
setcc(FPU_SW_C2|FPU_SW_C1);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
/*
|
|
|
|
* The C1 flag is set to the sign of the value in ST(0), regardless
|
2004-06-18 18:11:11 +04:00
|
|
|
* of whether the register is empty or full.
|
|
|
|
*/
|
|
|
|
if (! sign)
|
|
|
|
clear_C1();
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
2008-04-05 01:05:37 +04:00
|
|
|
|
|
|
|
#endif
|